2016-01-27 22:31:39 +11:00
|
|
|
#include <ws/ws.hpp>
|
|
|
|
|
|
|
|
namespace WonderSwan {
|
|
|
|
|
|
|
|
CPU cpu;
|
|
|
|
#include "memory.cpp"
|
|
|
|
|
|
|
|
auto CPU::Enter() -> void {
|
|
|
|
cpu.main();
|
|
|
|
}
|
|
|
|
|
|
|
|
auto CPU::main() -> void {
|
|
|
|
while(true) {
|
|
|
|
if(scheduler.sync == Scheduler::SynchronizeMode::CPU) {
|
|
|
|
scheduler.sync = Scheduler::SynchronizeMode::All;
|
|
|
|
scheduler.exit(Scheduler::ExitReason::SynchronizeEvent);
|
|
|
|
}
|
|
|
|
|
|
|
|
exec();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
auto CPU::step(uint clocks) -> void {
|
|
|
|
ppu.clock -= clocks;
|
|
|
|
if(ppu.clock < 0) co_switch(ppu.thread);
|
|
|
|
|
|
|
|
apu.clock -= clocks;
|
|
|
|
if(apu.clock < 0) co_switch(apu.thread);
|
|
|
|
}
|
|
|
|
|
2016-01-28 22:39:49 +11:00
|
|
|
auto CPU::wait(uint clocks) -> void {
|
|
|
|
step(clocks);
|
|
|
|
}
|
|
|
|
|
|
|
|
auto CPU::read(uint20 addr) -> uint8 {
|
2016-01-27 22:31:39 +11:00
|
|
|
return bus.read(addr);
|
|
|
|
}
|
|
|
|
|
2016-01-28 22:39:49 +11:00
|
|
|
auto CPU::write(uint20 addr, uint8 data) -> void {
|
2016-01-27 22:31:39 +11:00
|
|
|
return bus.write(addr, data);
|
|
|
|
}
|
|
|
|
|
2016-01-28 22:39:49 +11:00
|
|
|
auto CPU::in(uint16 port) -> uint16 {
|
|
|
|
return iomap[port]->portRead(port);
|
|
|
|
}
|
|
|
|
|
|
|
|
auto CPU::out(uint16 port, uint16 data) -> void {
|
|
|
|
return iomap[port]->portWrite(port, data);
|
|
|
|
}
|
|
|
|
|
2016-01-27 22:31:39 +11:00
|
|
|
auto CPU::power() -> void {
|
|
|
|
V30MZ::power();
|
|
|
|
create(CPU::Enter, 3072000);
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|