Update to bsnes v058 release.

We've tested the latest release on at least a dozen computers now, all seems to be in order for a release.
Changelog:
    - added 21fx support (more on this later)
    - added movie recording and playback support
    - added rewind support (enable under Settings->Configuration->Advanced, use backspace key to rewind)
    - added speedup (fast forward) and slowdown key bindings
    - audio no longer stutters on Windows when moving or resizing the main window
    - co-processors can now specify their own clock rates instead of sharing the S-CPU clock rate
    - Super Game Boy 2 now runs at the correct hardware speed, and not 2.4% faster like the Super Game Boy 1 does
    - added Vsync support to the Windows OpenGL driver (Intel graphics drivers do not support this option, because their engineers are lazy)
    - OpenGL driver no longer re-initializes when changing video synchronization, helps pixel shaders
    - refactored user interface compilation; now split into several object files, auto-generated MOC files placed under src/obj/
    - worked around a bug in the PulseAudio sound server that was causing the ALSA output driver to lock up [BearOso]
    - rewrote and simplified the save state manager, it is no longer a part of the core
    - S-DD1 and SPC7110 can now access up to 256MB via their MMCs
    - re-added background and OAM layer toggling under the tools dialog
    - added config file options to adjust emulation speed levels (config.system.speed*)
    - added snesreader, snesfilter and supergameboy support to the OS X port
    - added a really neat pixel shader that can perform point scaling to non-even multiples, eg it looks great even with aspect correction [Fes]
    - upgraded to Qt 4.6.0 official
Debugger changelog:
    - added memory export and import to the memory editor
    - added bus usage analyzer: logs opcodes, memory reads, memory writes and M/X states to usage.bin file
    - added disassembler that can trace both forward and backward from the current execution address
    - extended read/write breakpoints to the S-SMP
    - re-added trace masking option
Errata: there is one known bug in Qt 4.6.0 that affects the Windows port: menus attached to buttons show up as invisible on Windows Vista and above. I only use this on the file load dialog options button, and only to toggle the information pane on and off. Given that this is less severe than the bugs in the beta versions, I've upgraded anyway. I'll submit a bug report to the Qt team for this shortly. Also, my sincerest thanks to Bradley Hughes from the Qt development team for quickly fixing this show-stopper bug that greatly affected performance in bsnes v056.

license.txt

@@ -1,84 +0,0 @@
-bsnes (TM) Reference License
-Copyright (C) 2004 - 2008 byuu
-All rights reserved
-
-1. Definitions
-
-The terms "reproduce", "reproduction", "distribute" and "distribution" have the
-same meaning here as under U.S. copyright law.
-
-"The software" means this software package as a whole, including, but not
-limited to, this license, binaries, source code, documentation, and data.
-
-"You" means the licensee of the software.
-
-"The licensor" means the copyright holder of the software, byuu.
-
-2. Grant of Rights
-
-Subject to the terms of this license, the licensor grants you a
-non-transferable, non-exclusive, worldwide, royalty-free copyright license to
-reproduce the software for non-commercial use only, provided the software
-remains unmodified, and there is no charge for the software itself, its' use,
-nor for the medium upon which the software is distributed. The reproduction of
-modified or derivative works of the software is strictly prohibited, except when
-transmitted solely to the licensor.
-
-3. Limitations
-
-This license does not grant you any rights to use the licensor's name, logo or
-trademarks.
-
-The software is provided "as is", and any express or implied warranties,
-including, but not limited to, the implied warranties of merchantability and
-fitness for a particular purpose are disclaimed. In no event shall the licensor
-be liable for any direct, indirect, incidental, special, exemplary, or
-consequential damages (including, but not limited to, procurement of substitute
-goods or services; loss of use, data, or profits; or business interruption)
-however caused and on any theory of liability, whether in contract, strict
-liability, or tort (including negligence or otherwise) arising in any way out of
-the use of the software, even if advised of the possibility of such damage.
-
-In the event that this license is determined to be invalid or unenforceable, the
-Grant of Rights will become null and void, and no rights shall be granted to the
-licensee, within the scope of U.S. copyright law.
-
-4. Exemptions
-
-The software includes the work of other copyright holders, which is licensed
-under different agreements, and exempt from this license. Below is a complete
-list of all such software, and their respective copyright holders and licenses.
-Further, respective source code files are labeled with their correct licensing
-information in the header. The lack of such a header indicates said file falls
-under the bsnes license.
-
-HQ2x filter, author: MaxST, license: LGPL
-JMA decompressor, author: NSRT Team, license: GPL*
-NTSC filter, author: blargg, license: LGPL
-zlib decompressor, license: zlib license
-
-(* bsnes has received an exemption from the copyright holder to use this work.)
-
-The software also includes works which have been released to the public domain,
-which are not bound to any licensing agreements. Below is a complete list of all
-such software.
-
-libco, author: byuu
-S-DD1 decompressor, author: Andreas Naive
-SPC7110 decompressor, author: neviksti
-
-Any software listed above as exemptions may be relicensed individually from
-bsnes under their respective terms. However, no bsnes licensed portions can be
-combined with such a derivative work.
-
-The software also includes the work of other copyright holders, which is
-licensed under the terms of the bsnes license, with permission to do so from the
-respective authors. Below is a complete list of all such software.
-
-Cx4 emu, authors: anomie, Overload, zsKnight, Nach
-DSP-1 emu, authors: Overload, John Weidman, Neviksti, Andreas Naive
-DSP-2 emu, author: Overload
-DSP-3 emu, authors: John Weidman, Kris Bleakley, Lancer, z80 gaiden
-DSP-4 emu, authors: Dreamer Nom, John Weidman, Kris Bleakley, Nach, z80 gaiden
-S-DSP emu, author: blargg
-ST-010 emu, authors: John Weidman, Matthew Kendora, Overload, Feather

readme.txt

@@ -1,106 +0,0 @@
-bsnes
-Version: 0.034
-Author: byuu
-
-========
-General:
-========
-
-bsnes is a Super Nintendo / Super Famicom emulator that began on
-October 14th, 2004.
-
-The latest version can be downloaded from:
-http://byuu.org/
-
-Please see license.txt for important licensing information.
-
-==============
-Configuration:
-==============
-
-bsnes has two configuration files: bsnes.cfg, for program settings; and
-locale.cfg, for localization.
-
-For each file, bsnes will start by looking inside the same folder where the
-bsnes executable is located. If said file is not found, it will then check your
-user profile folder. On Windows, this is located at "%APPDATA%/.bsnes". On all
-other operating systems, this is located at "~/.bsnes". If said file is still
-not found, it will automatically be created in your user profile folder.
-
-If you wish to use bsnes in single-user mode, be sure that both files exist
-inside the same folder as the bsnes executable. If they do not, you can simply
-create new blank files and bsnes will use them in the future.
-
-If you wish to use bsnes in multi-user mode, simply delete these two files from
-the bsnes executable directory if they exist.
-
-If you wish to have multiple configuration profiles for the same user, you will
-need to make copies of the bsnes executable, and use each one in single-user
-mode.
-
-==================
-Known Limitations:
-==================
-
-S-CPU
-- Multiply / divide register delays not implemented
-- "Glitch" when reading joypad registers during auto polling not implemented
-
-S-PPU
-- Uses scanline-based renderer. This is very inaccurate, but few (if any)
-  games rely on mid-scanline writes to function correctly
-- Does not support FirstSprite+Y priority
-- OAM / CGRAM accesses during active display not supported correctly
-- RTO flags are not calculated on frames that are skipped when frameskipping
-  is enabled. This provides a major speedup, however it will cause in issues
-  in games that test these flags, eg the SNES Test Program Electronics Test.
-  Turning frameskipping off will allow RTO flag calculation on every frame
-
-Hardware Bugs
-- S-CPU.r1 HDMA crashing bug not emulated
-- S-CPU<>S-SMP communication bus conflicts not emulated
-
-=====================
-Unsupported Hardware:
-=====================
-
-SA-1
-Coprocessor used in many popular games, including:
-- Dragon Ball Z Hyper Dimension
-- Kirby Super Star
-- Kirby's Dreamland 3
-- Marvelous
-- SD Gundam G-NEXT
-- Super Mario RPG
-
-Super FX
-Coprocessor used in many popular games, including:
-- Doom
-- Star Fox
-- Star Fox 2 (unreleased beta)
-- Super Mario World 2: Yoshi's Island
-
-ST-011
-SETA DSP used by Quick-move Shogi Match with Nidan Rank-holder Morita
-
-ST-018
-SETA RISC CPU used by Quick-move Shogi Match with Nidan Rank-holder Morita 2
-
-Super Gameboy
-Cartridge passthrough used for playing Gameboy games
-
-========================
-Unsupported Controllers:
-========================
-
-Mouse
-Super Scope
-Justifier
-
-=============
-Contributors:
-=============
-
-Andreas Naive, anomie, blargg, DMV27, FitzRoy, GIGO, Jonas Quinn, kode54, krom,
-mudlord, Nach, neviksti, Overload, RedDwarf, Richard Bannister, tetsuo55, TRAC,
-zones

src/Makefile

@@ -1,55 +1,53 @@
-include lib/nall/Makefile.string
-prefix = /usr/local
+include lib/nall/Makefile
+include lib/nall/Makefile-qt
+ui = ui_qt
 
 ################
 ### compiler ###
 ################
 
-ifneq ($(findstring gcc,$(compiler)),) # GCC family
-  flags = -O3 -fomit-frame-pointer -Ilib
-  c = $(compiler) $(flags)
-  cpp = $(subst cc,++,$(compiler)) $(flags)
-  obj = o
-  rule = -c $< -o $@
-  link = -s
-  mkbin = -o$1
-  mkdef = -D$1
-  mklib = -l$1
-else ifeq ($(compiler),cl) # Visual C++
-  flags = /nologo /wd4355 /wd4996 /O2 /EHsc /Ilib
-  c = cl $(flags)
-  cpp = cl $(flags)
-  obj = obj
-  rule = /c $< /Fo$@
-  link = /link
-  mkbin = /Fe$1
-  mkdef = /D$1
-  mklib = $1.lib
-else
-  unknown_compiler: help;
-endif
+c     := $(compiler)
+cpp   := $(subst cc,++,$(compiler))
+flags := -O3 -fomit-frame-pointer -Ilib
+link  :=
 
-##########
-### os ###
-##########
+# profile-guided instrumentation:
+# flags += -fprofile-generate
+# link += -lgcov
 
-ifeq ($(platform),x) # X11
-  ruby = video.glx video.xv video.sdl audio.openal audio.oss audio.alsa audio.ao input.sdl input.x
-  link += `pkg-config --libs gtk+-2.0`
-  link += $(call mklib,Xtst)
-  delete = rm -f $1
-else ifeq ($(platform),win) # Windows
-  ruby = video.direct3d video.wgl video.directdraw video.gdi audio.directsound input.directinput
-  link += $(if $(findstring mingw,$(compiler)),-mwindows)
-  link += $(call mklib,uuid)
-  link += $(call mklib,kernel32)
-  link += $(call mklib,user32)
-  link += $(call mklib,gdi32)
-  link += $(call mklib,shell32)
-  link += $(call mklib,winmm)
-  link += $(call mklib,comdlg32)
-  link += $(call mklib,comctl32)
-  delete = $(if $(findstring i586-mingw-gcc,$(compiler)),rm -f $1,del $(subst /,\,$1))
+# profile-guided optimization:
+# flags += -fprofile-use
+
+################
+### platform ###
+################
+
+ifeq ($(platform),x)
+  link += -s
+
+  ruby := video.glx video.xv video.qtraster video.sdl
+  ruby += audio.alsa audio.openal audio.oss audio.pulseaudio audio.ao
+  ruby += input.sdl input.x
+
+  link += $(if $(findstring audio.openal,$(ruby)),-lopenal)
+else ifeq ($(platform),osx)
+  ruby := video.qtopengl video.qtraster
+  ruby += audio.openal
+  ruby += input.carbon
+
+  link += $(if $(findstring audio.openal,$(ruby)),-framework OpenAL)
+else ifeq ($(platform),win)
+  link += -mwindows -mthreads
+# link += -mconsole -mthreads
+  link += -s -luuid -lkernel32 -luser32 -lgdi32 -lshell32
+  # statically link Qt for Windows build
+  link += -enable-stdcall-fixup -Wl,-enable-auto-import -Wl,-enable-runtime-pseudo-reloc
+
+  ruby := video.direct3d video.wgl video.directdraw video.gdi video.qtraster
+  ruby += audio.directsound
+  ruby += input.rawinput input.directinput
+
+  link += $(if $(findstring audio.openal,$(ruby)),-lopenal32)
 else
   unknown_platform: help;
 endif
@@ -58,200 +56,154 @@ endif
 ### ruby ###
 ############
 
-rubyflags =
-rubyflags += $(if $(findstring .sdl,$(ruby)),`sdl-config --cflags`)
+rubyflags := $(call ifhas,.sdl,$(ruby),`sdl-config --cflags`)
+rubyflags += $(call ifhas,.qt,$(ruby),$(qtinc))
 
-link += $(if $(findstring video.direct3d,$(ruby)),$(call mklib,d3d9))
-link += $(if $(findstring video.directdraw,$(ruby)),$(call mklib,ddraw))
-link += $(if $(findstring video.glx,$(ruby)),$(call mklib,GL))
-link += $(if $(findstring video.wgl,$(ruby)),$(call mklib,opengl32))
-link += $(if $(findstring video.xv,$(ruby)),$(call mklib,Xv))
-link += $(if $(findstring audio.alsa,$(ruby)),$(call mklib,asound))
-link += $(if $(findstring audio.ao,$(ruby)),$(call mklib,ao))
-link += $(if $(findstring audio.directsound,$(ruby)),$(call mklib,dsound))
-link += $(if $(findstring audio.openal,$(ruby)),$(if $(call streq,$(platform),x),$(call mklib,openal),$(call mklib,openal32)))
-link += $(if $(findstring input.directinput,$(ruby)),$(call mklib,dinput8) $(call mklib,dxguid))
-link += $(if $(findstring input.sdl,$(ruby)),`sdl-config --libs`)
+link += $(call ifhas,.sdl,$(ruby),`sdl-config --libs`)
+link += $(call ifhas,video.direct3d,$(ruby),-ld3d9)
+link += $(call ifhas,video.directdraw,$(ruby),-lddraw)
+link += $(call ifhas,video.glx,$(ruby),-lGL)
+link += $(call ifhas,video.wgl,$(ruby),-lopengl32)
+link += $(call ifhas,video.xv,$(ruby),-lXv)
+link += $(call ifhas,audio.alsa,$(ruby),-lasound)
+link += $(call ifhas,audio.ao,$(ruby),-lao)
+link += $(call ifhas,audio.directsound,$(ruby),-ldsound)
+link += $(call ifhas,audio.pulseaudio,$(ruby),-lpulse-simple)
+link += $(call ifhas,input.directinput,$(ruby),-ldinput8 -ldxguid)
+link += $(call ifhas,input.rawinput,$(ruby),-ldinput8 -ldxguid)
 
-####################################
-### main target and dependencies ###
-####################################
+###############
+### objects ###
+###############
 
-objects = main libco hiro ruby libfilter string reader cart cheat \
-  memory smemory cpu scpu smp ssmp sdsp ppu bppu snes \
-  bsx srtc sdd1 spc7110 cx4 dsp1 dsp2 dsp3 dsp4 obc1 st010
+objects := libco ruby
+objects += system cartridge cheat
+objects += memory smemory cpu cpucore scpu smp smpcore ssmp sdsp ppu bppu
+objects += supergameboy superfx sa1
+objects += bsx srtc sdd1 spc7110 cx4 dsp1 dsp2 dsp3 dsp4 obc1 st010 st011 st018
+objects += 21fx
 
-ifeq ($(enable_gzip),true)
-  objects += adler32 compress crc32 deflate gzio inffast inflate inftrees ioapi trees unzip zip zutil
-  flags += $(call mkdef,GZIP_SUPPORT)
-endif
-
-ifeq ($(enable_jma),true)
-  objects += jma jcrc32 lzmadec 7zlzma iiostrm inbyte lzma winout
-  flags += $(call mkdef,JMA_SUPPORT)
-endif
-
-objects := $(patsubst %,obj/%.$(obj),$(objects))
-rubydef := $(foreach c,$(subst .,_,$(call strupper,$(ruby))),$(call mkdef,$c))
-
-# Windows resource file
-ifeq ($(platform),win)
-  ifeq ($(compiler),cl)
-    objects += obj/bsnes.res
-  else ifneq ($(findstring gcc,$(compiler)),)
-    objects += obj/bsnesrc.$(obj)
-  endif
-endif
-
-################
-### implicit ###
-################
+######################
+### implicit rules ###
+######################
 
 compile = \
   $(strip \
     $(if $(filter %.c,$<), \
-      $(c) $1 $(rule), \
+      $(c) $(flags) $1 -c $< -o $@, \
       $(if $(filter %.cpp,$<), \
-        $(cpp) $1 $(rule) \
+        $(cpp) $(flags) $1 -c $< -o $@ \
       ) \
     ) \
   )
 
-%.$(obj): $<; $(call compile)
+%.o: $<; $(call compile)
 
 all: build;
 
-############
-### main ###
-############
-
-obj/main.$(obj): ui/main.cpp ui/* ui/base/* ui/loader/* ui/settings/*
-obj/bsnes.res: ui/bsnes.rc; rc /r /foobj/bsnes.res ui/bsnes.rc
-obj/bsnesrc.$(obj): ui/bsnes.rc; windres ui/bsnes.rc obj/bsnesrc.$(obj)
+include $(ui)/Makefile
+objects := $(patsubst %,obj/%.o,$(objects))
+rubydef := $(foreach c,$(subst .,_,$(call strupper,$(ruby))),-D$c)
 
 #################
 ### libraries ###
 #################
 
-obj/ruby.$(obj): lib/ruby/ruby.cpp lib/ruby/*
+obj/ruby.o: lib/ruby/ruby.cpp $(call rwildcard,lib/ruby/*)
 	$(call compile,$(rubydef) $(rubyflags))
-obj/hiro.$(obj): lib/hiro/hiro.cpp lib/hiro/* lib/hiro/gtk/* lib/hiro/win/*
-	$(call compile,$(if $(call streq,$(platform),x),`pkg-config --cflags gtk+-2.0`))
-obj/libco.$(obj):     lib/libco/libco.c lib/libco/*
-	$(call compile,-static)
-obj/libfilter.$(obj): lib/libfilter/libfilter.cpp lib/libfilter/*
-obj/string.$(obj):    lib/nall/string.cpp lib/nall/*
+obj/libco.o: lib/libco/libco.c lib/libco/*
 
 #################
 ### utilities ###
 #################
 
-obj/reader.$(obj): reader/reader.cpp reader/*
-obj/cart.$(obj)  : cart/cart.cpp cart/*
-obj/cheat.$(obj) : cheat/cheat.cpp cheat/*
+obj/cartridge.o: cartridge/cartridge.cpp cartridge/*
+obj/cheat.o    : cheat/cheat.cpp cheat/*
 
 ##############
 ### memory ###
 ##############
 
-obj/memory.$(obj) : memory/memory.cpp memory/*
-obj/smemory.$(obj): memory/smemory/smemory.cpp memory/smemory/* memory/smemory/mapper/*
+obj/memory.o : memory/memory.cpp memory/*
+obj/smemory.o: memory/smemory/smemory.cpp $(call rwildcard,memory/smemory/)
 
 ###########
 ### cpu ###
 ###########
 
-obj/cpu.$(obj) : cpu/cpu.cpp cpu/*
-obj/scpu.$(obj): cpu/scpu/scpu.cpp cpu/scpu/* cpu/scpu/core/* cpu/scpu/dma/* cpu/scpu/memory/* cpu/scpu/mmio/* cpu/scpu/timing/*
+obj/cpu.o    : cpu/cpu.cpp cpu/*
+obj/cpucore.o: cpu/core/core.cpp $(call rwildcard,cpu/core/)
+obj/scpu.o   : cpu/scpu/scpu.cpp $(call rwildcard,cpu/scpu/)
 
 ###########
 ### smp ###
 ###########
 
-obj/smp.$(obj) : smp/smp.cpp smp/*
-obj/ssmp.$(obj): smp/ssmp/ssmp.cpp smp/ssmp/* smp/ssmp/core/* smp/ssmp/memory/* smp/ssmp/timing/*
+obj/smp.o    : smp/smp.cpp smp/*
+obj/smpcore.o: smp/core/core.cpp $(call rwildcard,smp/core/)
+obj/ssmp.o   : smp/ssmp/ssmp.cpp $(call rwildcard,smp/ssmp/)
 
 ###########
 ### dsp ###
 ###########
 
-obj/adsp.$(obj): dsp/adsp/adsp.cpp dsp/adsp/*
-obj/bdsp.$(obj): dsp/bdsp/bdsp.cpp dsp/bdsp/*
-obj/sdsp.$(obj): dsp/sdsp/sdsp.cpp dsp/sdsp/*
+obj/adsp.o: dsp/adsp/adsp.cpp dsp/adsp/*
+obj/sdsp.o: dsp/sdsp/sdsp.cpp dsp/sdsp/*
 
 ###########
 ### ppu ###
 ###########
 
-obj/ppu.$(obj) : ppu/ppu.cpp ppu/*
-obj/bppu.$(obj): ppu/bppu/bppu.cpp ppu/bppu/*
+obj/ppu.o : ppu/ppu.cpp ppu/*
+obj/bppu.o: ppu/bppu/bppu.cpp $(call rwildcard,ppu/bppu/)
 
-############
-### snes ###
-############
+##############
+### system ###
+##############
 
-obj/snes.$(obj): snes/snes.cpp snes/* snes/scheduler/* snes/video/* snes/audio/* snes/input/*
+obj/system.o: system/system.cpp $(call rwildcard,system/)
 
 #####################
 ### special chips ###
 #####################
 
-obj/bsx.$(obj)    : chip/bsx/bsx.cpp chip/bsx/*
-obj/srtc.$(obj)   : chip/srtc/srtc.cpp chip/srtc/*
-obj/sdd1.$(obj)   : chip/sdd1/sdd1.cpp chip/sdd1/*
-obj/spc7110.$(obj): chip/spc7110/spc7110.cpp chip/spc7110/*
-obj/cx4.$(obj)    : chip/cx4/cx4.cpp chip/cx4/*
-obj/dsp1.$(obj)   : chip/dsp1/dsp1.cpp chip/dsp1/*
-obj/dsp2.$(obj)   : chip/dsp2/dsp2.cpp chip/dsp2/*
-obj/dsp3.$(obj)   : chip/dsp3/dsp3.cpp chip/dsp3/*
-obj/dsp4.$(obj)   : chip/dsp4/dsp4.cpp chip/dsp4/*
-obj/obc1.$(obj)   : chip/obc1/obc1.cpp chip/obc1/*
-obj/st010.$(obj)  : chip/st010/st010.cpp chip/st010/*
-
-############
-### zlib ###
-############
-
-obj/adler32.$(obj) : reader/zlib/adler32.c reader/zlib/*
-obj/compress.$(obj): reader/zlib/compress.c reader/zlib/*
-obj/crc32.$(obj)   : reader/zlib/crc32.c reader/zlib/*
-obj/deflate.$(obj) : reader/zlib/deflate.c reader/zlib/*
-obj/gzio.$(obj)    : reader/zlib/gzio.c reader/zlib/*
-obj/inffast.$(obj) : reader/zlib/inffast.c reader/zlib/*
-obj/inflate.$(obj) : reader/zlib/inflate.c reader/zlib/*
-obj/inftrees.$(obj): reader/zlib/inftrees.c reader/zlib/*
-obj/ioapi.$(obj)   : reader/zlib/ioapi.c reader/zlib/*
-obj/trees.$(obj)   : reader/zlib/trees.c reader/zlib/*
-obj/unzip.$(obj)   : reader/zlib/unzip.c reader/zlib/*
-obj/zip.$(obj)     : reader/zlib/zip.c reader/zlib/*
-obj/zutil.$(obj)   : reader/zlib/zutil.c reader/zlib/*
-
-###########
-### jma ###
-###########
-
-obj/jma.$(obj)    : reader/jma/jma.cpp reader/jma/*
-obj/jcrc32.$(obj) : reader/jma/jcrc32.cpp reader/jma/*
-obj/lzmadec.$(obj): reader/jma/lzmadec.cpp reader/jma/*
-obj/7zlzma.$(obj) : reader/jma/7zlzma.cpp reader/jma/*
-obj/iiostrm.$(obj): reader/jma/iiostrm.cpp reader/jma/*
-obj/inbyte.$(obj) : reader/jma/inbyte.cpp reader/jma/*
-obj/lzma.$(obj)   : reader/jma/lzma.cpp reader/jma/*
-obj/winout.$(obj) : reader/jma/winout.cpp reader/jma/*
+obj/supergameboy.o: chip/supergameboy/supergameboy.cpp $(call rwildcard,chip/supergameboy/)
+obj/superfx.o     : chip/superfx/superfx.cpp $(call rwildcard,chip/superfx/)
+obj/sa1.o         : chip/sa1/sa1.cpp $(call rwildcard,chip/sa1/)
+obj/bsx.o         : chip/bsx/bsx.cpp chip/bsx/*
+obj/srtc.o        : chip/srtc/srtc.cpp chip/srtc/*
+obj/sdd1.o        : chip/sdd1/sdd1.cpp chip/sdd1/*
+obj/spc7110.o     : chip/spc7110/spc7110.cpp chip/spc7110/*
+obj/cx4.o         : chip/cx4/cx4.cpp chip/cx4/*
+obj/dsp1.o        : chip/dsp1/dsp1.cpp chip/dsp1/*
+obj/dsp2.o        : chip/dsp2/dsp2.cpp chip/dsp2/*
+obj/dsp3.o        : chip/dsp3/dsp3.cpp chip/dsp3/*
+obj/dsp4.o        : chip/dsp4/dsp4.cpp chip/dsp4/*
+obj/obc1.o        : chip/obc1/obc1.cpp chip/obc1/*
+obj/st010.o       : chip/st010/st010.cpp chip/st010/*
+obj/st011.o       : chip/st011/st011.cpp chip/st011/*
+obj/st018.o       : chip/st018/st018.cpp chip/st018/*
+obj/21fx.o        : chip/21fx/21fx.cpp chip/21fx/*
 
 ###############
 ### targets ###
 ###############
 
-build: $(objects)
-	$(strip $(cpp) $(call mkbin,../bsnes) $(objects) $(link))
+build: ui_build $(objects)
+ifeq ($(platform),osx)
+	test -d ../bsnes.app || mkdir -p ../bsnes.app/Contents/MacOS
+	$(strip $(cpp) -o ../bsnes.app/Contents/MacOS/bsnes $(objects) $(link))
+else
+	$(strip $(cpp) -o ../bsnes $(objects) $(link))
+endif
 
 install:
 	install -D -m 755 ../bsnes $(DESTDIR)$(prefix)/bin/bsnes
-	install -D -m 644 data/bsnes.png $(DESTDIR)$(prefix)/share/icons/bsnes.png
+	install -D -m 644 data/bsnes.png $(DESTDIR)$(prefix)/share/pixmaps/bsnes.png
+	install -D -m 644 data/bsnes.desktop $(DESTDIR)$(prefix)/share/applications/bsnes.desktop
 
-clean:
-	-@$(call delete,obj/*.$(obj))
+clean: ui_clean
+	-@$(call delete,obj/*.o)
 	-@$(call delete,*.res)
 	-@$(call delete,*.pgd)
 	-@$(call delete,*.pgc)
@@ -270,11 +222,6 @@ help:
 	@echo "  gcc              - GCC compiler"
 	@echo "  mingw32-gcc      - MinGW compiler"
 	@echo "  i586-mingw32-gcc - MinGW cross compiler"
-	@echo "  cl               - Visual C++"
 	@echo ""
-	@echo "Available options:"
-	@echo "  enable_gzip=[true|false] - Enable ZIP / GZ support (default=false)"
-	@echo "  enable_jma=[true|false]  - Enable JMA support (default=false)"
-	@echo ""
-	@echo "Example: $(MAKE) platform=x compiler=gcc enable_gzip=true"
+	@echo "Example: $(MAKE) platform=x compiler=gcc"
 	@echo ""

src/base.h

@@ -1,43 +0,0 @@
-#define BSNES_VERSION "0.034"
-#define BSNES_TITLE   "bsnes v" BSNES_VERSION
-
-#define BUSCORE sBus
-#define CPUCORE sCPU
-#define SMPCORE sSMP
-#define DSPCORE sDSP
-#define PPUCORE bPPU
-
-//S-DSP can be encapsulated into a state machine using #define magic
-//this avoids ~2.048m co_switch() calls per second (~5% speedup)
-#define USE_STATE_MACHINE
-
-//FAST_FRAMESKIP disables calculation of RTO during frameskip
-//frameskip offers near-zero speedup if RTO is calculated
-//accuracy is not affected by this define when frameskipping is off
-#define FAST_FRAMESKIP
-
-//game genie + pro action replay code support (~2% speed hit)
-#define CHEAT_SYSTEM
-
-#include <nall/algorithm.hpp>
-#include <nall/array.hpp>
-#include <nall/bit.hpp>
-#include <nall/config.hpp>
-#include <nall/detect.hpp>
-#include <nall/function.hpp>
-#include <nall/modulo.hpp>
-#include <nall/new.hpp>
-#include <nall/sort.hpp>
-#include <nall/stdint.hpp>
-#include <nall/string.hpp>
-#include <nall/vector.hpp>
-using namespace nall;
-
-#include <libco/libco.h>
-#include <bbase.h>
-
-//platform-specific global functions
-void alert(const char*, ...);
-void dprintf(const char*, ...);
-
-#include "interface.h"

src/base.hpp

@@ -0,0 +1,45 @@
+static const char bsnesVersion[] = "0.058";
+static const char bsnesTitle[] = "bsnes";
+static const unsigned bsnesSerializerVersion = 4;
+
+//S-DSP can be encapsulated into a state machine using #define magic
+//this avoids ~2.048m co_switch() calls per second (~5% speedup)
+#define DSP_STATE_MACHINE
+
+//game genie + pro action replay code support (~2% speed hit)
+#define CHEAT_SYSTEM
+
+//enable debugging extensions (~15% speed hit)
+//#define DEBUGGER
+
+#include <libco/libco.h>
+
+#include <nall/algorithm.hpp>
+#include <nall/array.hpp>
+#include <nall/bit.hpp>
+#include <nall/detect.hpp>
+#include <nall/dl.hpp>
+#include <nall/endian.hpp>
+#include <nall/file.hpp>
+#include <nall/function.hpp>
+#include <nall/moduloarray.hpp>
+#include <nall/platform.hpp>
+#include <nall/priorityqueue.hpp>
+#include <nall/property.hpp>
+#include <nall/serializer.hpp>
+#include <nall/stdint.hpp>
+#include <nall/string.hpp>
+#include <nall/utility.hpp>
+#include <nall/vector.hpp>
+using namespace nall;
+
+typedef int8_t   int8;
+typedef int16_t  int16;
+typedef int32_t  int32;
+typedef int64_t  int64;
+typedef uint8_t  uint8;
+typedef uint16_t uint16;
+typedef uint32_t uint32;
+typedef uint64_t uint64;
+
+#include "interface.hpp"

src/cart/cart.cpp

@@ -1,141 +0,0 @@
-#include "../base.h"
-#define CART_CPP
-
-#include <nall/crc32.hpp>
-#include <nall/ups.hpp>
-
-#include "cart_normal.cpp"
-#include "cart_bsx.cpp"
-#include "cart_bsc.cpp"
-#include "cart_st.cpp"
-
-#include "cart_file.cpp"
-#include "cart_header.cpp"
-
-namespace memory {
-  MappedRAM cartrom, cartram, cartrtc;
-  MappedRAM bscram;
-  MappedRAM stArom, stAram;
-  MappedRAM stBrom, stBram;
-};
-
-Cartridge cartridge;
-
-Cartridge::MemoryMapper Cartridge::mapper() { return info.mapper; }
-Cartridge::Region Cartridge::region() { return info.region; }
-
-bool Cartridge::loaded() { return cart.loaded; }
-
-void Cartridge::load_begin(CartridgeType cart_type) {
-  cart.rom = cart.ram = cart.rtc = 0;
-  bs.ram   = 0;
-  stA.rom  = stA.ram  = 0;
-  stB.rom  = stB.ram  = 0;
-
-  cart.rom_size = cart.ram_size = cart.rtc_size = 0;
-  bs.ram_size   = 0;
-  stA.rom_size  = stA.ram_size  = 0;
-  stB.rom_size  = stB.ram_size  = 0;
-
-  info.type = cart_type;
-  info.patched = false;
-
-  info.bsxbase  = false;
-  info.bsxcart  = false;
-  info.bsxflash = false;
-  info.st       = false;
-
-  info.superfx    = false;
-  info.sa1        = false;
-  info.srtc       = false;
-  info.sdd1       = false;
-  info.spc7110    = false;
-  info.spc7110rtc = false;
-  info.cx4        = false;
-  info.dsp1       = false;
-  info.dsp2       = false;
-  info.dsp3       = false;
-  info.dsp4       = false;
-  info.obc1       = false;
-  info.st010      = false;
-  info.st011      = false;
-  info.st018      = false;
-
-  info.dsp1_mapper = DSP1Unmapped;
-
-  info.header_index = 0xffc0;
-  info.mapper = LoROM;
-  info.name[0] = 0;
-  info.region = NTSC;
-
-  info.rom_size = 0;
-  info.ram_size = 0;
-}
-
-void Cartridge::load_end() {
-  memory::cartrom.map(cart.rom, cart.rom_size);
-  memory::cartram.map(cart.ram, cart.ram_size);
-  memory::cartrtc.map(cart.rtc, cart.rtc_size);
-  memory::bscram.map(bs.ram, bs.ram_size);
-  memory::stArom.map(stA.rom, stA.rom_size);
-  memory::stAram.map(stA.ram, stA.ram_size);
-  memory::stBrom.map(stB.rom, stB.rom_size);
-  memory::stBram.map(stB.ram, stB.ram_size);
-
-  memory::cartrom.write_protect(true);
-  memory::cartram.write_protect(false);
-  memory::bscram.write_protect(true);
-  memory::stArom.write_protect(true);
-  memory::stAram.write_protect(false);
-  memory::stBrom.write_protect(true);
-  memory::stBram.write_protect(false);
-
-  if(fexists(get_cheat_filename(cart.fn, "cht"))) {
-    cheat.clear();
-    cheat.load(cheatfn);
-  }
-
-  cart.loaded = true;
-  bus.load_cart();
-}
-
-bool Cartridge::unload() {
-  if(cart.loaded == false) return false;
-
-  bus.unload_cart();
-
-  switch(info.type) {
-    case CartridgeNormal:      unload_cart_normal(); break;
-    case CartridgeBSX:         unload_cart_bsx();    break;
-    case CartridgeBSC:         unload_cart_bsc();    break;
-    case CartridgeSufamiTurbo: unload_cart_st();     break;
-  }
-
-  if(cart.rom) { delete[] cart.rom; cart.rom = 0; }
-  if(cart.ram) { delete[] cart.ram; cart.ram = 0; }
-  if(cart.rtc) { delete[] cart.rtc; cart.rtc = 0; }
-  if(bs.ram)   { delete[] bs.ram;   bs.ram   = 0; }
-  if(stA.rom)  { delete[] stA.rom;  stA.rom  = 0; }
-  if(stA.ram)  { delete[] stA.ram;  stA.ram  = 0; }
-  if(stB.rom)  { delete[] stB.rom;  stB.rom  = 0; }
-  if(stB.ram)  { delete[] stB.ram;  stB.ram  = 0; }
-
-  char fn[PATH_MAX];
-  strcpy(fn, cart.fn);
-  modify_extension(fn, "cht");
-  if(cheat.count() > 0 || fexists(get_cheat_filename(cart.fn, "cht"))) {
-    cheat.save(cheatfn);
-    cheat.clear();
-  }
-
-  cart.loaded = false;
-  return true;
-}
-
-Cartridge::Cartridge() {
-  cart.loaded = false;
-}
-
-Cartridge::~Cartridge() {
-  if(cart.loaded == true) unload();
-}

src/cart/cart.h

@@ -1,160 +0,0 @@
-class Cartridge {
-public:
-  enum CartridgeType {
-    CartridgeNormal,
-    CartridgeBSX,
-    CartridgeBSC,
-    CartridgeSufamiTurbo,
-  };
-
-  enum HeaderField {
-    CART_NAME = 0x00,
-    MAPPER    = 0x15,
-    ROM_TYPE  = 0x16,
-    ROM_SIZE  = 0x17,
-    RAM_SIZE  = 0x18,
-    REGION    = 0x19,
-    COMPANY   = 0x1a,
-    VERSION   = 0x1b,
-    ICKSUM    = 0x1c,
-    CKSUM     = 0x1e,
-    RESL      = 0x3c,
-    RESH      = 0x3d,
-  };
-
-  enum Region {
-    NTSC,
-    PAL,
-  };
-
-  enum MemoryMapper {
-    LoROM,
-    HiROM,
-    ExLoROM,
-    ExHiROM,
-    SPC7110ROM,
-    BSXROM,
-    BSCLoROM,
-    BSCHiROM,
-    STROM,
-  };
-
-  enum DSP1MemoryMapper {
-    DSP1Unmapped,
-    DSP1LoROM1MB,
-    DSP1LoROM2MB,
-    DSP1HiROM,
-  };
-
-  struct {
-    bool loaded;
-    char fn[PATH_MAX];
-    uint8 *rom, *ram, *rtc;
-    uint rom_size, ram_size, rtc_size;
-  } cart;
-
-  struct {
-    char fn[PATH_MAX];
-    uint8 *ram;
-    uint ram_size;
-  } bs;
-
-  struct {
-    char fn[PATH_MAX];
-    uint8 *rom, *ram;
-    uint rom_size, ram_size;
-  } stA, stB;
-
-  struct {
-    CartridgeType type;
-
-    uint32 crc32;
-    char filename[PATH_MAX * 4];
-    char name[128];
-    bool patched;
-
-    Region region;
-    MemoryMapper mapper;
-    uint rom_size;
-    uint ram_size;
-
-    bool bsxbase;
-    bool bsxcart;
-    bool bsxflash;
-    bool st;
-    bool superfx;
-    bool sa1;
-    bool srtc;
-    bool sdd1;
-    bool spc7110;
-    bool spc7110rtc;
-    bool cx4;
-    bool dsp1;
-    bool dsp2;
-    bool dsp3;
-    bool dsp4;
-    bool obc1;
-    bool st010;
-    bool st011;
-    bool st018;
-
-    DSP1MemoryMapper dsp1_mapper;
-
-    uint header_index;
-  } info;
-
-  MemoryMapper mapper();
-  Region region();
-
-  void load_cart_normal(const char*);
-  void load_cart_bsx(const char*, const char*);
-  void load_cart_bsc(const char*, const char*);
-  void load_cart_st(const char*, const char*, const char*);
-
-  void unload_cart_normal();
-  void unload_cart_bsx();
-  void unload_cart_bsc();
-  void unload_cart_st();
-
-  bool loaded();
-  void load_begin(CartridgeType);
-  void load_end();
-  bool unload();
-
-  void find_header();
-  void read_header();
-  void read_extended_header();
-
-  enum CompressionMode {
-    CompressionNone,    //always load without compression
-    CompressionInspect, //use file header inspection
-    CompressionAuto,    //use file extension or file header inspection (configured by user)
-  };
-  bool load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression = CompressionNone);
-  bool save_file(const char *fn, uint8 *data, uint size);
-  bool apply_patch(const uint8_t *pdata, unsigned psize, uint8_t *&data, unsigned &size);
-  char* modify_extension(char *filename, const char *extension);
-  char* get_base_filename(char *filename);
-  char* get_path_filename(char *filename, const char *path, const char *source, const char *extension);
-  char* get_patch_filename(const char *source, const char *extension);
-  char* get_save_filename(const char *source, const char *extension);
-  char* get_cheat_filename(const char *source, const char *extension);
-
-  Cartridge();
-  ~Cartridge();
-
-private:
-  char patchfn[PATH_MAX];
-  char savefn[PATH_MAX];
-  char rtcfn[PATH_MAX];
-  char cheatfn[PATH_MAX];
-};
-
-namespace memory {
-  extern MappedRAM cartrom, cartram, cartrtc;
-  extern MappedRAM bscram;
-  extern MappedRAM stArom, stAram;
-  extern MappedRAM stBrom, stBram;
-};
-
-extern Cartridge cartridge;

src/cart/cart_bsc.cpp

@@ -1,65 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_bsc(const char *base, const char *slot) {
-  if(!base || !*base) return;
-
-  strcpy(cart.fn, base);
-  strcpy(bs.fn, slot ? slot : "");
-  load_begin(CartridgeBSC);
-
-  uint8_t *data = 0;
-  unsigned size;
-  load_file(cart.fn, data, size, CompressionAuto);
-  cart.rom = data, cart.rom_size = size;
-
-  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
-    apply_patch(data, size, cart.rom, cart.rom_size);
-    delete[] data;
-  }
-
-  if(*bs.fn) {
-    if(load_file(bs.fn, data, size, CompressionAuto) == true) {
-      info.bsxflash = true;
-      bs.ram = data, bs.ram_size = size;
-      if(load_file(get_patch_filename(bs.fn, "ups"), data, size, CompressionInspect) == true) {
-        apply_patch(data, size, bs.ram, bs.ram_size);
-        delete[] data;
-      }
-    }
-  }
-
-  find_header();
-  read_header();
-
-  info.mapper = cartridge.info.header_index == 0x7fc0 ? BSCLoROM : BSCHiROM;
-  info.region = NTSC;
-
-  if(info.ram_size > 0) {
-    cart.ram = new uint8_t[cart.ram_size = info.ram_size];
-    memset(cart.ram, 0xff, cart.ram_size);
-
-    if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
-      memcpy(cart.ram, data, min(size, cart.ram_size));
-      delete[] data;
-    }
-  }
-
-  load_end();
-
-  //set base filename
-  strcpy(info.filename, cart.fn);
-  get_base_filename(info.filename);
-  if(*bs.fn) {
-    char filenameBS[PATH_MAX];
-    strcpy(filenameBS, bs.fn);
-    get_base_filename(filenameBS);
-    strcat(info.filename, " + ");
-    strcat(info.filename, filenameBS);
-  }
-}
-
-void Cartridge::unload_cart_bsc() {
-  if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_bsx.cpp

@@ -1,61 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_bsx(const char *base, const char *slot) {
-  if(!base || !*base) return;
-
-  strcpy(cart.fn, base);
-  strcpy(bs.fn, slot ? slot : "");
-
-  load_begin(CartridgeBSX);
-  info.bsxbase = true;
-  info.bsxcart = true;
-  info.mapper = BSXROM;
-  info.region = NTSC;
-
-  uint8_t *data = 0;
-  unsigned size;
-  load_file(cart.fn, data, size, CompressionAuto);
-  cart.rom = data, cart.rom_size = size;
-  cart.ram = 0, cart.ram_size = 0;
-
-  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
-    apply_patch(data, size, cart.rom, cart.rom_size);
-    delete[] data;
-  }
-
-  memset(bsxcart.sram.handle (), 0x00, bsxcart.sram.size ());
-  memset(bsxcart.psram.handle(), 0x00, bsxcart.psram.size());
-
-  if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
-    memcpy(bsxcart.sram.handle (), data, min(bsxcart.sram.size (), size));
-    delete[] data;
-  }
-
-  if(load_file(get_save_filename(cart.fn, "psr"), data, size, CompressionNone) == true) {
-    memcpy(bsxcart.psram.handle(), data, min(bsxcart.psram.size(), size));
-    delete[] data;
-  }
-
-  if(*bs.fn) {
-    if(load_file(bs.fn, data, size, CompressionAuto) == true) {
-      info.bsxflash = true;
-      bs.ram = data, bs.ram_size = size;
-      if(load_file(get_patch_filename(bs.fn, "ups"), data, size, CompressionInspect) == true) {
-        apply_patch(data, size, bs.ram, bs.ram_size);
-        delete[] data;
-      }
-    }
-  }
-
-  load_end();
-
-  strcpy(info.filename, !*bs.fn ? cart.fn : bs.fn);
-  get_base_filename(info.filename);
-}
-
-void Cartridge::unload_cart_bsx() {
-  save_file(get_save_filename(cart.fn, "srm"), bsxcart.sram.handle (), bsxcart.sram.size ());
-  save_file(get_save_filename(cart.fn, "psr"), bsxcart.psram.handle(), bsxcart.psram.size());
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_file.cpp

@@ -1,177 +0,0 @@
-#ifdef CART_CPP
-
-#include "../reader/filereader.h"
-
-#if defined(GZIP_SUPPORT)
-  #include "../reader/gzreader.h"
-  #include "../reader/zipreader.h"
-#endif
-
-#if defined(JMA_SUPPORT)
-  #include "../reader/jmareader.h"
-#endif
-
-char* Cartridge::modify_extension(char *filename, const char *extension) {
-  int i;
-  for(i = strlen(filename); i >= 0; i--) {
-    if(filename[i] == '.') break;
-    if(filename[i] == '/') break;
-    if(filename[i] == '\\') break;
-  }
-  if(i > 0 && filename[i] == '.') filename[i] = 0;
-  strcat(filename, ".");
-  strcat(filename, extension);
-  return filename;
-}
-
-//remove directory information and file extension ("/foo/bar.ext" -> "bar")
-char* Cartridge::get_base_filename(char *filename) {
-  //remove extension
-  for(int i = strlen(filename) - 1; i >= 0; i--) {
-    if(filename[i] == '.') {
-      filename[i] = 0;
-      break;
-    }
-  }
-
-  //remove directory information
-  for(int i = strlen(filename) - 1; i >= 0; i--) {
-    if(filename[i] == '/' || filename[i] == '\\') {
-      i++;
-      char *output = filename;
-      while(true) {
-        *output++ = filename[i];
-        if(!filename[i]) break;
-        i++;
-      }
-      break;
-    }
-  }
-}
-
-char* Cartridge::get_path_filename(char *filename, const char *path, const char *source, const char *extension) {
-  strcpy(filename, source);
-  for(char *p = filename; *p; p++) { if(*p == '\\') *p = '/'; }
-  modify_extension(filename, extension);
-
-  //override path with user-specified folder, if one was defined
-  if(*path) {
-    lstring part;
-    split(part, "/", filename);
-    string fn = path;
-    if(strend(fn, "/") == false) strcat(fn, "/");
-    strcat(fn, part[count(part) - 1]);
-    strcpy(filename, fn);
-
-    //resolve relative path, if found
-    if(strbegin(fn, "./") == true) {
-      ltrim(fn, "./");
-      strcpy(filename, config::path.base);
-      strcat(filename, fn);
-    }
-  }
-
-  return filename;
-}
-
-char* Cartridge::get_patch_filename(const char *source, const char *extension) {
-  return get_path_filename(patchfn, config::path.patch, source, extension);
-}
-
-char* Cartridge::get_save_filename(const char *source, const char *extension) {
-  return get_path_filename(savefn, config::path.save, source, extension);
-}
-
-char* Cartridge::get_cheat_filename(const char *source, const char *extension) {
-  return get_path_filename(cheatfn, config::path.cheat, source, extension);
-}
-
-bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression) {
-  if(fexists(fn) == false) return false;
-
-  Reader::Type filetype = Reader::Normal;
-  if(compression == CompressionInspect) filetype = Reader::detect(fn, true);
-  if(compression == CompressionAuto) filetype = Reader::detect(fn, config::file.autodetect_type);
-
-  switch(filetype) {
-    default:
-      dprintf("* Warning: filetype detected as unsupported compression type.");
-      dprintf("* Will attempt to load as uncompressed file -- may fail.");
-    case Reader::Normal: {
-      FileReader ff(fn);
-      if(!ff.ready()) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-      size = ff.size();
-      data = ff.read();
-    } break;
-
-    #ifdef GZIP_SUPPORT
-    case Reader::GZIP: {
-      GZReader gf(fn);
-      if(!gf.ready()) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-      size = gf.size();
-      data = gf.read();
-    } break;
-
-    case Reader::ZIP: {
-      ZipReader zf(fn);
-      size = zf.size();
-      data = zf.read();
-    } break;
-    #endif
-
-    #ifdef JMA_SUPPORT
-    case Reader::JMA: {
-      try {
-        JMAReader jf(fn);
-        size = jf.size();
-        data = jf.read();
-      } catch(JMA::jma_errors jma_error) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-    } break;
-    #endif
-  }
-
-  return true;
-}
-
-bool Cartridge::apply_patch(const uint8_t *pdata, const unsigned psize, uint8_t *&data, unsigned &size) {
-  uint8_t *outdata = 0;
-  unsigned outsize;
-  ups patcher;
-  ups::result result = patcher.apply(pdata, psize, data, size, outdata, outsize);
-
-  bool apply = false;
-  if(result == ups::ok) apply = true;
-  if(config::file.bypass_patch_crc32 == true) {
-    if(result == ups::input_crc32_invalid) apply = true;
-    if(result == ups::output_crc32_invalid) apply = true;
-  }
-
-  if(apply == true) {
-    delete[] data;
-    data = new uint8_t[size = outsize];
-    memcpy(data, outdata, outsize);
-  } else {
-    dprintf("* Warning: patch application failed!");
-  }
-
-  if(outdata) delete[] outdata;
-}
-
-bool Cartridge::save_file(const char *fn, uint8 *data, uint size) {
-  FILE *fp = fopen(fn, "wb");
-  if(!fp) return false;
-  fwrite(data, 1, size, fp);
-  fclose(fp);
-  return true;
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_header.cpp

@@ -1,197 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::read_header() {
-  uint8 *rom = cart.rom;
-  uint index = info.header_index;
-  uint8 mapper   = rom[index + MAPPER];
-  uint8 rom_type = rom[index + ROM_TYPE];
-  uint8 rom_size = rom[index + ROM_SIZE];
-  uint8 company  = rom[index + COMPANY];
-  uint8 region   = rom[index + REGION] & 0x7f;
-
-  //detect presence of BS-X flash cartridge connector (reads extended header information)
-  bool has_bsxflash = false;
-  if(rom[index - 14] == 'Z') {
-    if(rom[index - 11] == 'J') {
-      uint8 n13 = rom[index - 13];
-      if((n13 >= 'A' && n13 <= 'Z') || (n13 >= '0' && n13 <= '9')) {
-        if(company == 0x33 || (rom[index - 10] == 0x00 && rom[index - 4] == 0x00)) {
-          has_bsxflash = true;
-        }
-      }
-    }
-  }
-
-  if(has_bsxflash == true) {
-    info.mapper = index == 0x7fc0 ? BSCLoROM : BSCHiROM;
-  } else if(index == 0x7fc0 && cart.rom_size >= 0x401000) {
-    info.mapper = ExLoROM;
-  } else if(index == 0x7fc0 && mapper == 0x32) {
-    info.mapper = ExLoROM;
-  } else if(index == 0x7fc0) {
-    info.mapper = LoROM;
-  } else if(index == 0xffc0) {
-    info.mapper = HiROM;
-  } else { //index == 0x40ffc0
-    info.mapper = ExHiROM;
-  }
-
-  if(mapper == 0x20 && (rom_type == 0x13 || rom_type == 0x14 || rom_type == 0x15 || rom_type == 0x1a)) {
-    info.superfx = true;
-  }
-
-  if(mapper == 0x23 && (rom_type == 0x34 || rom_type == 0x35)) {
-    info.sa1 = true;
-  }
-
-  if(mapper == 0x35 && rom_type == 0x55) {
-    info.srtc = true;
-  }
-
-  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
-    info.sdd1 = true;
-  }
-
-  if(mapper == 0x3a && (rom_type == 0xf5 || rom_type == 0xf9)) {
-    info.spc7110 = true;
-    info.spc7110rtc = (rom_type == 0xf9);
-    info.mapper = SPC7110ROM;
-  }
-
-  if(mapper == 0x20 && rom_type == 0xf3) {
-    info.cx4 = true;
-  }
-
-  if((mapper == 0x20 || mapper == 0x21) && rom_type == 0x03) {
-    info.dsp1 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x05 && company != 0xb2) {
-    info.dsp1 = true;
-  }
-
-  if(mapper == 0x31 && (rom_type == 0x03 || rom_type == 0x05)) {
-    info.dsp1 = true;
-  }
-
-  if(info.dsp1 == true) {
-    if((mapper & 0x2f) == 0x20 && cart.rom_size <= 0x100000) {
-      info.dsp1_mapper = DSP1LoROM1MB;
-    } else if((mapper & 0x2f) == 0x20) {
-      info.dsp1_mapper = DSP1LoROM2MB;
-    } else if((mapper & 0x2f) == 0x21) {
-      info.dsp1_mapper = DSP1HiROM;
-    }
-  }
-
-  if(mapper == 0x20 && rom_type == 0x05) {
-    info.dsp2 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x05 && company == 0xb2) {
-    info.dsp3 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x03) {
-    info.dsp4 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x25) {
-    info.obc1 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0xf6 && rom_size >= 10) {
-    info.st010 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0xf6 && rom_size < 10) {
-    info.st011 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0xf5) {
-    info.st018 = true;
-  }
-
-  if(rom[info.header_index + RAM_SIZE] & 7) {
-    info.ram_size = 1024 << (rom[info.header_index + RAM_SIZE] & 7);
-  } else {
-    info.ram_size = 0;
-  }
-
-  //0, 1, 13 = NTSC; 2 - 12 = PAL
-  info.region = (region <= 1 || region >= 13) ? NTSC : PAL;
-
-  memcpy(&info.name, &rom[info.header_index + CART_NAME], 21);
-  info.name[21] = 0;
-  trim(info.name);
-
-  //convert undisplayable characters (half-width katakana, etc) to '?' characters
-  for(int i = 0; i < 21; i++) {
-    if(info.name[i] & 0x80) info.name[i] = '?';
-  }
-
-  //always display something
-  if(!info.name[0]) strcpy(info.name, "(untitled)");
-}
-
-void Cartridge::find_header() {
-  int32 score_lo = 0, score_hi = 0, score_ex = 0;
-  uint8_t *rom = cart.rom;
-
-  if(cart.rom_size < 0x010000) {
-    //cart too small to be anything but lorom
-    info.header_index = 0x007fc0;
-    return;
-  }
-
-  if((rom[0x7fc0 + MAPPER] & ~0x10) == 0x20) score_lo++;
-  if((rom[0xffc0 + MAPPER] & ~0x10) == 0x21) score_hi++;
-
-  if(rom[0x7fc0 + ROM_TYPE] < 0x08) score_lo++;
-  if(rom[0xffc0 + ROM_TYPE] < 0x08) score_hi++;
-
-  if(rom[0x7fc0 + ROM_SIZE] < 0x10) score_lo++;
-  if(rom[0xffc0 + ROM_SIZE] < 0x10) score_hi++;
-
-  if(rom[0x7fc0 + RAM_SIZE] < 0x08) score_lo++;
-  if(rom[0xffc0 + RAM_SIZE] < 0x08) score_hi++;
-
-  if(rom[0x7fc0 + REGION] < 14) score_lo++;
-  if(rom[0xffc0 + REGION] < 14) score_hi++;
-
-  if(rom[0x7fc0 + COMPANY] < 3) score_lo++;
-  if(rom[0xffc0 + COMPANY] < 3) score_hi++;
-
-  if(rom[0x7fc0 + RESH] & 0x80) score_lo += 2;
-  if(rom[0xffc0 + RESH] & 0x80) score_hi += 2;
-
-  uint16 cksum, icksum;
-  cksum  = rom[0x7fc0 +  CKSUM] | (rom[0x7fc0 +  CKSUM + 1] << 8);
-  icksum = rom[0x7fc0 + ICKSUM] | (rom[0x7fc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_lo += 8;
-  }
-
-  cksum  = rom[0xffc0 +  CKSUM] | (rom[0xffc0 +  CKSUM + 1] << 8);
-  icksum = rom[0xffc0 + ICKSUM] | (rom[0xffc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_hi += 8;
-  }
-
-  if(cart.rom_size < 0x401000) {
-    score_ex = 0;
-  } else {
-    if(rom[0x7fc0 + MAPPER] == 0x32) score_lo++;
-    else score_ex += 12;
-  }
-
-  if(score_lo >= score_hi && score_lo >= score_ex) {
-    info.header_index = 0x007fc0;
-  } else if(score_hi >= score_ex) {
-    info.header_index = 0x00ffc0;
-  } else {
-    info.header_index = 0x40ffc0;
-  }
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_normal.cpp

@@ -1,64 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_normal(const char *filename) {
-  if(!filename || !*filename) return;
-
-  uint8_t *data = 0;
-  unsigned size;
-  if(load_file(filename, data, size, CompressionAuto) == false) return;
-  strcpy(cart.fn, filename);
-
-  load_begin(CartridgeNormal);
-
-  //load ROM data, ignore 512-byte header if detected
-  if((size & 0x7fff) != 512) {
-    cart.rom = new uint8_t[cart.rom_size = size];
-    memcpy(cart.rom, data, size);
-  } else {
-    cart.rom = new uint8_t[cart.rom_size = size - 512];
-    memcpy(cart.rom, data + 512, size - 512);
-  }
-  delete[] data;
-
-  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
-    apply_patch(data, size, cart.rom, cart.rom_size);
-    delete[] data;
-    info.patched = true;
-  }
-
-  info.crc32 = crc32_calculate(cart.rom, cart.rom_size);
-
-  find_header();
-  read_header();
-
-  if(info.ram_size > 0) {
-    cart.ram = new uint8_t[cart.ram_size = info.ram_size];
-    memset(cart.ram, 0xff, cart.ram_size);
-
-    if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
-      memcpy(cart.ram, data, min(size, cart.ram_size));
-      delete[] data;
-    }
-  }
-
-  if(info.srtc || info.spc7110rtc) {
-    cart.rtc = new(zeromemory) uint8_t[cart.rtc_size = 20];
-    if(load_file(get_save_filename(cart.fn, "rtc"), data, size, CompressionNone) == true) {
-      memcpy(cart.rtc, data, min(size, cart.rtc_size));
-      delete[] data;
-    }
-  }
-
-  load_end();
-
-  //set base filename
-  strcpy(info.filename, cart.fn);
-  get_base_filename(info.filename);
-}
-
-void Cartridge::unload_cart_normal() {
-  if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
-  if(cart.rtc) save_file(get_save_filename(cart.fn, "rtc"), cart.rtc, cart.rtc_size);
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_st.cpp

@@ -1,96 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_st(const char *base, const char *slotA, const char *slotB) {
-  if(!base || !*base) return;
-
-  strcpy(cart.fn, base);
-  strcpy(stA.fn, slotA ? slotA : "");
-  strcpy(stB.fn, slotB ? slotB : "");
-
-  load_begin(CartridgeSufamiTurbo);
-  info.st = true;
-  info.mapper = STROM;
-  info.region = NTSC;
-
-  uint8_t *data = 0;
-  unsigned size;
-  if(load_file(cart.fn, data, size, CompressionAuto) == true) {
-    cart.rom = new(zeromemory) uint8_t[cart.rom_size = 0x040000];
-    memcpy(cart.rom, data, min(size, cart.rom_size));
-    delete[] data;
-    if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
-      apply_patch(data, size, cart.rom, cart.rom_size);
-      delete[] data;
-    }
-  }
-
-  if(*stA.fn) {
-    if(load_file(stA.fn, data, size, CompressionAuto) == true) {
-      stA.rom = new(zeromemory) uint8_t[stA.rom_size = 0x100000];
-      memcpy(stA.rom, data, min(size, stA.rom_size));
-      delete[] data;
-      if(load_file(get_patch_filename(stA.fn, "ups"), data, size, CompressionInspect) == true) {
-        apply_patch(data, size, stA.rom, stA.rom_size);
-        delete[] data;
-      }
-
-      stA.ram = new uint8_t[stA.ram_size = 0x020000];
-      memset(stA.ram, 0xff, stA.ram_size);
-
-      if(load_file(get_save_filename(stA.fn, "srm"), data, size, CompressionNone) == true) {
-        memcpy(stA.ram, data, min(size, 0x020000U));
-        delete[] data;
-      }
-    }
-  }
-
-  if(*stB.fn) {
-    if(load_file(stB.fn, data, size, CompressionAuto) == true) {
-      stB.rom = new(zeromemory) uint8_t[stB.rom_size = 0x100000];
-      memcpy(stB.rom, data, min(size, stB.rom_size));
-      delete[] data;
-      if(load_file(get_patch_filename(stB.fn, "ups"), data, size, CompressionInspect) == true) {
-        apply_patch(data, size, stB.rom, stB.rom_size);
-        delete[] data;
-      }
-
-      stB.ram = new uint8_t[stB.ram_size = 0x020000];
-      memset(stB.ram, 0xff, stB.ram_size);
-
-      if(load_file(get_save_filename(stB.fn, "srm"), data, size, CompressionNone) == true) {
-        memcpy(stB.ram, data, min(size, 0x020000U));
-        delete[] data;
-      }
-    }
-  }
-
-  load_end();
-
-  //set base filename
-  if(!*stA.fn && !*stB.fn) {
-    strcpy(info.filename, cart.fn);
-    get_base_filename(info.filename);
-  } else if(*stA.fn && !*stB.fn) {
-    strcpy(info.filename, stA.fn);
-    get_base_filename(info.filename);
-  } else if(!*stA.fn && *stB.fn) {
-    strcpy(info.filename, stB.fn);
-    get_base_filename(info.filename);
-  } else {
-    char filenameA[PATH_MAX], filenameB[PATH_MAX];
-    strcpy(filenameA, stA.fn);
-    get_base_filename(filenameA);
-    strcpy(filenameB, stB.fn);
-    get_base_filename(filenameB);
-    strcpy(info.filename, filenameA);
-    strcat(info.filename, " + ");
-    strcat(info.filename, filenameB);
-  }
-}
-
-void Cartridge::unload_cart_st() {
-  if(stA.ram) save_file(get_save_filename(stA.fn, "srm"), stA.ram, stA.ram_size);
-  if(stB.ram) save_file(get_save_filename(stB.fn, "srm"), stB.ram, stB.ram_size);
-}
-
-#endif //ifdef CART_CPP

src/cartridge/cartridge.cpp

@@ -0,0 +1,231 @@
+#include <../base.hpp>
+#include <nall/crc32.hpp>
+#include <nall/sha256.hpp>
+
+#define CARTRIDGE_CPP
+namespace SNES {
+
+#include "header.cpp"
+#include "gameboyheader.cpp"
+
+namespace memory {
+  MappedRAM cartrom, cartram, cartrtc;
+  MappedRAM bsxflash, bsxram, bsxpram;
+  MappedRAM stArom, stAram;
+  MappedRAM stBrom, stBram;
+  MappedRAM gbrom, gbram, gbrtc;
+};
+
+Cartridge cartridge;
+
+void Cartridge::load(Mode cartridge_mode) {
+  cartinfo_t cartinfo;
+  read_header(cartinfo, memory::cartrom.data(), memory::cartrom.size());
+  set_cartinfo(cartinfo);
+
+  set(mode, cartridge_mode);
+
+  if(cartinfo.ram_size > 0) {
+    memory::cartram.map(allocate<uint8_t>(cartinfo.ram_size, 0xff), cartinfo.ram_size);
+  }
+
+  if(cartinfo.srtc || cartinfo.spc7110rtc) {
+    memory::cartrtc.map(allocate<uint8_t>(20, 0xff), 20);
+  }
+
+  if(mode() == ModeBsx) {
+    memory::bsxram.map (allocate<uint8_t>( 32 * 1024, 0xff),  32 * 1024);
+    memory::bsxpram.map(allocate<uint8_t>(512 * 1024, 0xff), 512 * 1024);
+  }
+
+  if(mode() == ModeSufamiTurbo) {
+    if(memory::stArom.data()) memory::stAram.map(allocate<uint8_t>(128 * 1024, 0xff), 128 * 1024);
+    if(memory::stBrom.data()) memory::stBram.map(allocate<uint8_t>(128 * 1024, 0xff), 128 * 1024);
+  }
+
+  if(mode() == ModeSuperGameBoy) {
+    if(memory::gbrom.data()) {
+      unsigned ram_size = gameboy_ram_size();
+      unsigned rtc_size = gameboy_rtc_size();
+
+      if(ram_size) memory::gbram.map(allocate<uint8_t>(ram_size, 0xff), ram_size);
+      if(rtc_size) memory::gbrtc.map(allocate<uint8_t>(rtc_size, 0x00), rtc_size);
+    }
+  }
+
+  memory::cartrom.write_protect(true);
+  memory::cartram.write_protect(false);
+  memory::cartrtc.write_protect(false);
+  memory::bsxflash.write_protect(true);
+  memory::bsxram.write_protect(false);
+  memory::bsxpram.write_protect(false);
+  memory::stArom.write_protect(true);
+  memory::stAram.write_protect(false);
+  memory::stBrom.write_protect(true);
+  memory::stBram.write_protect(false);
+  memory::gbrom.write_protect(true);
+  memory::gbram.write_protect(false);
+  memory::gbrtc.write_protect(false);
+
+  unsigned checksum = ~0;
+  for(unsigned n = 0; n < memory::cartrom.size(); n++) checksum = crc32_adjust(checksum, memory::cartrom[n]);
+  if(memory::bsxflash.size() != 0 && memory::bsxflash.size() != ~0)
+  for(unsigned n = 0; n < memory::bsxflash.size(); n++) checksum = crc32_adjust(checksum, memory::bsxflash[n]);
+  if(memory::stArom.size() != 0 && memory::stArom.size() != ~0)
+  for(unsigned n = 0; n < memory::stArom.size(); n++) checksum = crc32_adjust(checksum, memory::stArom[n]);
+  if(memory::stBrom.size() != 0 && memory::stBrom.size() != ~0)
+  for(unsigned n = 0; n < memory::stBrom.size(); n++) checksum = crc32_adjust(checksum, memory::stBrom[n]);
+  if(memory::gbrom.size() != 0 && memory::gbrom.size() != ~0)
+  for(unsigned n = 0; n < memory::gbrom.size(); n++) checksum = crc32_adjust(checksum, memory::gbrom[n]);
+  set(crc32, ~checksum);
+
+#if 0
+  fprintf(stdout, "crc32  = %.8x\n", crc32());
+
+  sha256_ctx sha;
+  uint8_t shahash[32];
+  sha256_init(&sha);
+  sha256_chunk(&sha, memory::cartrom.data(), memory::cartrom.size());
+  sha256_final(&sha);
+  sha256_hash(&sha, shahash);
+
+  fprintf(stdout, "sha256 = ");
+  for(unsigned i = 0; i < 32; i++) fprintf(stdout, "%.2x", shahash[i]);
+  fprintf(stdout, "\n");
+#endif
+
+  bus.load_cart();
+  system.serialize_init();
+  set(loaded, true);
+}
+
+void Cartridge::unload() {
+  memory::cartrom.reset();
+  memory::cartram.reset();
+  memory::cartrtc.reset();
+  memory::bsxflash.reset();
+  memory::bsxram.reset();
+  memory::bsxpram.reset();
+  memory::stArom.reset();
+  memory::stAram.reset();
+  memory::stBrom.reset();
+  memory::stBram.reset();
+  memory::gbrom.reset();
+  memory::gbram.reset();
+  memory::gbrtc.reset();
+
+  if(loaded() == false) return;
+  bus.unload_cart();
+  set(loaded, false);
+}
+
+Cartridge::Type Cartridge::detect_image_type(uint8_t *data, unsigned size) const {
+  cartinfo_t info;
+  read_header(info, data, size);
+  return info.type;
+}
+
+bool Cartridge::has_21fx() const { return s21fx.exists(); }
+
+void Cartridge::serialize(serializer &s) {
+  if(memory::cartram.size() != 0 && memory::cartram.size() != ~0) {
+    s.array(memory::cartram.data(), memory::cartram.size());
+  }
+
+  if(memory::cartrtc.size() != 0 && memory::cartrtc.size() != ~0) {
+    s.array(memory::cartrtc.data(), memory::cartrtc.size());
+  }
+
+  if(memory::bsxram.size() != 0 && memory::bsxram.size() != ~0) {
+    s.array(memory::bsxram.data(), memory::bsxram.size());
+  }
+
+  if(memory::bsxpram.size() != 0 && memory::bsxpram.size() != ~0) {
+    s.array(memory::bsxpram.data(), memory::bsxpram.size());
+  }
+
+  if(memory::stAram.size() != 0 && memory::stAram.size() != ~0) {
+    s.array(memory::stAram.data(), memory::stAram.size());
+  }
+
+  if(memory::stBram.size() != 0 && memory::stBram.size() != ~0) {
+    s.array(memory::stBram.data(), memory::stBram.size());
+  }
+
+  if(memory::gbram.size() != 0 && memory::gbram.size() != ~0) {
+    s.array(memory::gbram.data(), memory::gbram.size());
+  }
+
+  if(memory::gbrtc.size() != 0 && memory::gbrtc.size() != ~0) {
+    s.array(memory::gbrtc.data(), memory::gbrtc.size());
+  }
+}
+
+Cartridge::Cartridge() {
+  set(loaded, false);
+  unload();
+}
+
+Cartridge::~Cartridge() {
+  unload();
+}
+
+void Cartridge::set_cartinfo(const Cartridge::cartinfo_t &source) {
+  set(region,         source.region);
+  set(mapper,         source.mapper);
+  set(dsp1_mapper,    source.dsp1_mapper);
+
+  set(has_bsx_slot,   source.bsx_slot);
+  set(has_superfx,    source.superfx);
+  set(has_sa1,        source.sa1);
+  set(has_srtc,       source.srtc);
+  set(has_sdd1,       source.sdd1);
+  set(has_spc7110,    source.spc7110);
+  set(has_spc7110rtc, source.spc7110rtc);
+  set(has_cx4,        source.cx4);
+  set(has_dsp1,       source.dsp1);
+  set(has_dsp2,       source.dsp2);
+  set(has_dsp3,       source.dsp3);
+  set(has_dsp4,       source.dsp4);
+  set(has_obc1,       source.obc1);
+  set(has_st010,      source.st010);
+  set(has_st011,      source.st011);
+  set(has_st018,      source.st018);
+}
+
+//==========
+//cartinfo_t
+//==========
+
+void Cartridge::cartinfo_t::reset() {
+  type        = TypeUnknown;
+  mapper      = LoROM;
+  dsp1_mapper = DSP1Unmapped;
+  region      = NTSC;
+
+  rom_size = 0;
+  ram_size = 0;
+
+  bsx_slot   = false;
+  superfx    = false;
+  sa1        = false;
+  srtc       = false;
+  sdd1       = false;
+  spc7110    = false;
+  spc7110rtc = false;
+  cx4        = false;
+  dsp1       = false;
+  dsp2       = false;
+  dsp3       = false;
+  dsp4       = false;
+  obc1       = false;
+  st010      = false;
+  st011      = false;
+  st018      = false;
+}
+
+Cartridge::cartinfo_t::cartinfo_t() {
+  reset();
+}
+
+}

src/cartridge/cartridge.hpp

@@ -0,0 +1,135 @@
+class Cartridge : public property {
+public:
+  enum Mode {
+    ModeNormal,
+    ModeBsxSlotted,
+    ModeBsx,
+    ModeSufamiTurbo,
+    ModeSuperGameBoy,
+  };
+
+  enum Type {
+    TypeNormal,
+    TypeBsxSlotted,
+    TypeBsxBios,
+    TypeBsx,
+    TypeSufamiTurboBios,
+    TypeSufamiTurbo,
+    TypeSuperGameBoyBios,
+    TypeGameBoy,
+    TypeUnknown,
+  };
+
+  enum Region {
+    NTSC,
+    PAL,
+  };
+
+  enum MemoryMapper {
+    LoROM,
+    HiROM,
+    ExLoROM,
+    ExHiROM,
+    SuperFXROM,
+    SA1ROM,
+    SPC7110ROM,
+    BSCLoROM,
+    BSCHiROM,
+    BSXROM,
+    STROM,
+  };
+
+  enum DSP1MemoryMapper {
+    DSP1Unmapped,
+    DSP1LoROM1MB,
+    DSP1LoROM2MB,
+    DSP1HiROM,
+  };
+
+  //properties can be read via operator(), eg "if(cartridge.loaded() == true)";
+  //warning: if loaded() == false, no other property is considered valid!
+
+  property_t<bool> loaded;  //is a base cartridge inserted?
+  property_t<unsigned> crc32;  //crc32 of all files sans headers
+
+  property_t<Mode> mode;
+  property_t<Region> region;
+  property_t<MemoryMapper> mapper;
+  property_t<DSP1MemoryMapper> dsp1_mapper;
+
+  property_t<bool> has_bsx_slot;
+  property_t<bool> has_superfx;
+  property_t<bool> has_sa1;
+  property_t<bool> has_srtc;
+  property_t<bool> has_sdd1;
+  property_t<bool> has_spc7110, has_spc7110rtc;
+  property_t<bool> has_cx4;
+  property_t<bool> has_dsp1, has_dsp2, has_dsp3, has_dsp4;
+  property_t<bool> has_obc1;
+  property_t<bool> has_st010, has_st011, has_st018;
+  bool has_21fx() const;
+
+  //main interface
+  void load(Mode);
+  void unload();
+  Type detect_image_type(uint8_t *data, unsigned size) const;
+
+  void serialize(serializer&);
+  Cartridge();
+  ~Cartridge();
+
+private:
+  struct cartinfo_t {
+    Type type;
+    Region region;
+    MemoryMapper mapper;
+    DSP1MemoryMapper dsp1_mapper;
+    unsigned rom_size, ram_size;
+
+    bool bsx_slot;
+    bool superfx;
+    bool sa1;
+    bool srtc;
+    bool sdd1;
+    bool spc7110, spc7110rtc;
+    bool cx4;
+    bool dsp1, dsp2, dsp3, dsp4;
+    bool obc1;
+    bool st010, st011, st018;
+
+    void reset();
+    cartinfo_t();
+  };
+
+  enum HeaderField {
+    CartName    = 0x00,
+    Mapper      = 0x15,
+    RomType     = 0x16,
+    RomSize     = 0x17,
+    RamSize     = 0x18,
+    CartRegion  = 0x19,
+    Company     = 0x1a,
+    Version     = 0x1b,
+    Complement  = 0x1c,  //inverse checksum
+    Checksum    = 0x1e,
+    ResetVector = 0x3c,
+  };
+
+  void read_header(cartinfo_t &info, const uint8_t *data, unsigned size) const;
+  unsigned find_header(const uint8_t *data, unsigned size) const;
+  unsigned score_header(const uint8_t *data, unsigned size, unsigned addr) const;
+  void set_cartinfo(const cartinfo_t&);
+
+  unsigned gameboy_ram_size() const;
+  unsigned gameboy_rtc_size() const;
+};
+
+namespace memory {
+  extern MappedRAM cartrom, cartram, cartrtc;
+  extern MappedRAM bsxflash, bsxram, bsxpram;
+  extern MappedRAM stArom, stAram;
+  extern MappedRAM stBrom, stBram;
+  extern MappedRAM gbrom, gbram, gbrtc;
+};
+
+extern Cartridge cartridge;

src/cartridge/gameboyheader.cpp

@@ -0,0 +1,22 @@
+#ifdef CARTRIDGE_CPP
+
+unsigned Cartridge::gameboy_ram_size() const {
+  if(memory::gbrom.size() < 512) return 0;
+  switch(memory::gbrom[0x0149]) {
+    case 0x00: return   0 * 1024;
+    case 0x01: return   8 * 1024;
+    case 0x02: return   8 * 1024;
+    case 0x03: return  32 * 1024;
+    case 0x04: return 128 * 1024;
+    case 0x05: return 128 * 1024;
+    default:   return 128 * 1024;
+  }
+}
+
+unsigned Cartridge::gameboy_rtc_size() const {
+  if(memory::gbrom.size() < 512) return 0;
+  if(memory::gbrom[0x0147] == 0x0f || memory::gbrom[0x0147] == 0x10) return 4;
+  return 0;
+}
+
+#endif

src/cartridge/header.cpp

@@ -0,0 +1,294 @@
+#ifdef CARTRIDGE_CPP
+
+void Cartridge::read_header(cartinfo_t &info, const uint8_t *data, unsigned size) const {
+  info.reset();
+
+  //=====================
+  //detect Game Boy carts
+  //=====================
+
+  if(size >= 0x0140) {
+    if(data[0x0104] == 0xce && data[0x0105] == 0xed && data[0x0106] == 0x66 && data[0x0107] == 0x66
+    && data[0x0108] == 0xcc && data[0x0109] == 0x0d && data[0x010a] == 0x00 && data[0x010b] == 0x0b) {
+      info.type = TypeGameBoy;
+      return;
+    }
+  }
+
+  const unsigned index = find_header(data, size);
+  const uint8 mapper   = data[index + Mapper];
+  const uint8 rom_type = data[index + RomType];
+  const uint8 rom_size = data[index + RomSize];
+  const uint8 company  = data[index + Company];
+  const uint8 region   = data[index + CartRegion] & 0x7f;
+
+  info.ram_size = 1024 << (data[index + RamSize] & 7);
+  if(info.ram_size == 1024) info.ram_size = 0;  //no RAM present, eg RamSize == 0
+
+  //0, 1, 13 = NTSC; 2 - 12 = PAL
+  info.region = (region <= 1 || region >= 13) ? NTSC : PAL;
+
+  //=======================
+  //detect BS-X flash carts
+  //=======================
+
+  if(data[index + 0x13] == 0x00 || data[index + 0x13] == 0xff) {
+    if(data[index + 0x14] == 0x00) {
+      const uint8_t n15 = data[index + 0x15];
+      if(n15 == 0x00 || n15 == 0x80 || n15 == 0x84 || n15 == 0x9c || n15 == 0xbc || n15 == 0xfc) {
+        if(data[index + 0x1a] == 0x33 || data[index + 0x1a] == 0xff) {
+          info.type = TypeBsx;
+          info.mapper = BSXROM;
+          info.region = NTSC;  //BS-X only released in Japan
+          return;
+        }
+      }
+    }
+  }
+
+  //=========================
+  //detect Sufami Turbo carts
+  //=========================
+
+  if(!memcmp(data, "BANDAI SFC-ADX", 14)) {
+    if(!memcmp(data + 16, "SFC-ADX BACKUP", 14)) {
+      info.type = TypeSufamiTurboBios;
+    } else {
+      info.type = TypeSufamiTurbo;
+    }
+    info.mapper = STROM;
+    info.region = NTSC;  //Sufami Turbo only released in Japan
+    return;              //RAM size handled internally by load_cart_st();
+  }
+
+  //==========================
+  //detect Super Game Boy BIOS
+  //==========================
+
+  if(!memcmp(data + index, "Super GAMEBOY", 13)) {
+    info.type = TypeSuperGameBoyBios;
+    return;
+  }
+
+  //=====================
+  //detect standard carts
+  //=====================
+
+  //detect presence of BS-X flash cartridge connector (reads extended header information)
+  if(data[index - 14] == 'Z') {
+    if(data[index - 11] == 'J') {
+      uint8 n13 = data[index - 13];
+      if((n13 >= 'A' && n13 <= 'Z') || (n13 >= '0' && n13 <= '9')) {
+        if(company == 0x33 || (data[index - 10] == 0x00 && data[index - 4] == 0x00)) {
+          info.bsx_slot = true;
+        }
+      }
+    }
+  }
+
+  if(info.bsx_slot == true) {
+    if(!memcmp(data + index, "Satellaview BS-X     ", 21)) {
+      //BS-X base cart
+      info.type = TypeBsxBios;
+      info.mapper = BSXROM;
+      info.region = NTSC;  //BS-X only released in Japan
+      return;              //RAM size handled internally by load_cart_bsx() -> BSXCart class
+    } else {
+      info.type = TypeBsxSlotted;
+      info.mapper = (index == 0x7fc0 ? BSCLoROM : BSCHiROM);
+    }
+  } else {
+    //standard cart
+    info.type = TypeNormal;
+
+    if(index == 0x7fc0 && size >= 0x401000) {
+      info.mapper = ExLoROM;
+    } else if(index == 0x7fc0 && mapper == 0x32) {
+      info.mapper = ExLoROM;
+    } else if(index == 0x7fc0) {
+      info.mapper = LoROM;
+    } else if(index == 0xffc0) {
+      info.mapper = HiROM;
+    } else {  //index == 0x40ffc0
+      info.mapper = ExHiROM;
+    }
+  }
+
+  if(mapper == 0x20 && (rom_type == 0x13 || rom_type == 0x14 || rom_type == 0x15 || rom_type == 0x1a)) {
+    info.superfx = true;
+    info.mapper = SuperFXROM;
+    info.ram_size = 1024 << (data[index - 3] & 7);
+    if(info.ram_size == 1024) info.ram_size = 0;
+  }
+
+  if(mapper == 0x23 && (rom_type == 0x32 || rom_type == 0x34 || rom_type == 0x35)) {
+    info.sa1 = true;
+    info.mapper = SA1ROM;
+  }
+
+  if(mapper == 0x35 && rom_type == 0x55) {
+    info.srtc = true;
+  }
+
+  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
+    info.sdd1 = true;
+  }
+
+  if(mapper == 0x3a && (rom_type == 0xf5 || rom_type == 0xf9)) {
+    info.spc7110 = true;
+    info.spc7110rtc = (rom_type == 0xf9);
+    info.mapper = SPC7110ROM;
+  }
+
+  if(mapper == 0x20 && rom_type == 0xf3) {
+    info.cx4 = true;
+  }
+
+  if((mapper == 0x20 || mapper == 0x21) && rom_type == 0x03) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x05 && company != 0xb2) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x31 && (rom_type == 0x03 || rom_type == 0x05)) {
+    info.dsp1 = true;
+  }
+
+  if(info.dsp1 == true) {
+    if((mapper & 0x2f) == 0x20 && size <= 0x100000) {
+      info.dsp1_mapper = DSP1LoROM1MB;
+    } else if((mapper & 0x2f) == 0x20) {
+      info.dsp1_mapper = DSP1LoROM2MB;
+    } else if((mapper & 0x2f) == 0x21) {
+      info.dsp1_mapper = DSP1HiROM;
+    }
+  }
+
+  if(mapper == 0x20 && rom_type == 0x05) {
+    info.dsp2 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x05 && company == 0xb2) {
+    info.dsp3 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x03) {
+    info.dsp4 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x25) {
+    info.obc1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf6 && rom_size >= 10) {
+    info.st010 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf6 && rom_size < 10) {
+    info.st011 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf5) {
+    info.st018 = true;
+  }
+}
+
+unsigned Cartridge::find_header(const uint8_t *data, unsigned size) const {
+  unsigned score_lo = score_header(data, size, 0x007fc0);
+  unsigned score_hi = score_header(data, size, 0x00ffc0);
+  unsigned score_ex = score_header(data, size, 0x40ffc0);
+  if(score_ex) score_ex += 4;  //favor ExHiROM on images > 32mbits
+
+  if(score_lo >= score_hi && score_lo >= score_ex) {
+    return 0x007fc0;
+  } else if(score_hi >= score_ex) {
+    return 0x00ffc0;
+  } else {
+    return 0x40ffc0;
+  }
+}
+
+unsigned Cartridge::score_header(const uint8_t *data, unsigned size, unsigned addr) const {
+  if(size < addr + 64) return 0;  //image too small to contain header at this location?
+  int score = 0;
+
+  uint16 resetvector = data[addr + ResetVector] | (data[addr + ResetVector + 1] << 8);
+  uint16 checksum    = data[addr + Checksum   ] | (data[addr + Checksum    + 1] << 8);
+  uint16 complement  = data[addr + Complement ] | (data[addr + Complement  + 1] << 8);
+
+  uint8 resetop = data[(addr & ~0x7fff) | (resetvector & 0x7fff)];  //first opcode executed upon reset
+  uint8 mapper  = data[addr + Mapper] & ~0x10;                      //mask off irrelevent FastROM-capable bit
+
+  //$00:[000-7fff] contains uninitialized RAM and MMIO.
+  //reset vector must point to ROM at $00:[8000-ffff] to be considered valid.
+  if(resetvector < 0x8000) return 0;
+
+  //some images duplicate the header in multiple locations, and others have completely
+  //invalid header information that cannot be relied upon.
+  //below code will analyze the first opcode executed at the specified reset vector to
+  //determine the probability that this is the correct header.
+
+  //most likely opcodes
+  if(resetop == 0x78  //sei
+  || resetop == 0x18  //clc (clc; xce)
+  || resetop == 0x38  //sec (sec; xce)
+  || resetop == 0x9c  //stz $nnnn (stz $4200)
+  || resetop == 0x4c  //jmp $nnnn
+  || resetop == 0x5c  //jml $nnnnnn
+  ) score += 8;
+
+  //plausible opcodes
+  if(resetop == 0xc2  //rep #$nn
+  || resetop == 0xe2  //sep #$nn
+  || resetop == 0xad  //lda $nnnn
+  || resetop == 0xae  //ldx $nnnn
+  || resetop == 0xac  //ldy $nnnn
+  || resetop == 0xaf  //lda $nnnnnn
+  || resetop == 0xa9  //lda #$nn
+  || resetop == 0xa2  //ldx #$nn
+  || resetop == 0xa0  //ldy #$nn
+  || resetop == 0x20  //jsr $nnnn
+  || resetop == 0x22  //jsl $nnnnnn
+  ) score += 4;
+
+  //implausible opcodes
+  if(resetop == 0x40  //rti
+  || resetop == 0x60  //rts
+  || resetop == 0x6b  //rtl
+  || resetop == 0xcd  //cmp $nnnn
+  || resetop == 0xec  //cpx $nnnn
+  || resetop == 0xcc  //cpy $nnnn
+  ) score -= 4;
+
+  //least likely opcodes
+  if(resetop == 0x00  //brk #$nn
+  || resetop == 0x02  //cop #$nn
+  || resetop == 0xdb  //stp
+  || resetop == 0x42  //wdm
+  || resetop == 0xff  //sbc $nnnnnn,x
+  ) score -= 8;
+
+  //at times, both the header and reset vector's first opcode will match ...
+  //fallback and rely on info validity in these cases to determine more likely header.
+
+  //a valid checksum is the biggest indicator of a valid header.
+  if((checksum + complement) == 0xffff && (checksum != 0) && (complement != 0)) score += 4;
+
+  if(addr == 0x007fc0 && mapper == 0x20) score += 2;  //0x20 is usually LoROM
+  if(addr == 0x00ffc0 && mapper == 0x21) score += 2;  //0x21 is usually HiROM
+  if(addr == 0x007fc0 && mapper == 0x22) score += 2;  //0x22 is usually ExLoROM
+  if(addr == 0x40ffc0 && mapper == 0x25) score += 2;  //0x25 is usually ExHiROM
+
+  if(data[addr + Company] == 0x33) score += 2;        //0x33 indicates extended header
+  if(data[addr + RomType] < 0x08) score++;
+  if(data[addr + RomSize] < 0x10) score++;
+  if(data[addr + RamSize] < 0x08) score++;
+  if(data[addr + CartRegion] < 14) score++;
+
+  if(score < 0) score = 0;
+  return score;
+}
+
+#endif

src/cc.bat

@@ -1,3 +1,3 @@
-::@make platform=win compiler=mingw32-gcc
-@make platform=win compiler=mingw32-gcc enable_gzip=true enable_jma=true
+@mingw32-make
+
 @pause

src/cc.sh

@@ -1,2 +0,0 @@
-make platform=x compiler=gcc
-#make platform=x compiler=gcc enable_gzip=true enable_jma=true

src/cheat/cheat-inline.hpp

@@ -0,0 +1,3 @@
+unsigned Cheat::count() const { return code.size(); }
+bool Cheat::active() const { return cheat_enabled; }
+bool Cheat::exists(unsigned addr) const { return mask[addr >> 3] & 1 << (addr & 7); }

src/cheat/cheat.cpp

@@ -1,98 +1,352 @@
-#include "../base.h"
-#include "../reader/filereader.h"
+#include <../base.hpp>
+
+#define CHEAT_CPP
+namespace SNES {
 
 Cheat cheat;
 
-/*****
- * string <> binary code translation routines
- * decode() "7e1234:56" ->  0x7e123456
- * encode()  0x7e123456 -> "7e1234:56"
- *****/
+Cheat::cheat_t& Cheat::cheat_t::operator=(const Cheat::cheat_t& source) {
+  enabled = source.enabled;
+  code = source.code;
+  desc = source.desc;
+  count = source.count;
+
+  addr.reset();
+  data.reset();
+  for(unsigned n = 0; n < count; n++) {
+    addr[n] = source.addr[n];
+    data[n] = source.data[n];
+  }
+
+  return *this;
+}
+
+//used to sort cheat code list by description
+bool Cheat::cheat_t::operator<(const Cheat::cheat_t& source) {
+  return strcmp(desc, source.desc) < 0;
+}
+
+//parse item ("0123-4567+89AB-CDEF"), return cheat_t item
+//return true if code is valid, false otherwise
+bool Cheat::decode(const char *s, Cheat::cheat_t &item) const {
+  item.enabled = false;
+  item.count = 0;
+
+  string code = s;
+  code.replace(" ", "");
+
+  lstring list;
+  list.split("+", code);
+
+  for(unsigned n = 0; n < list.size(); n++) {
+    unsigned addr;
+    uint8_t data;
+    type_t type;
+    if(decode(list[n], addr, data, type) == false) {
+      item.count = 0;
+      return false;
+    }
+
+    item.addr[item.count] = addr;
+    item.data[item.count] = data;
+    item.count++;
+  }
+
+  return true;
+}
+
+//read() is used by MemBus::read() if Cheat::enabled(addr) returns true to look up cheat code.
+//returns true if cheat code was found, false if it was not.
+//when true, cheat code substitution value is stored in data.
+bool Cheat::read(unsigned addr, uint8_t &data) const {
+  addr = mirror_address(addr);
+  for(unsigned i = 0; i < code.size(); i++) {
+    if(enabled(i) == false) continue;
+
+    for(unsigned n = 0; n < code[i].count; n++) {
+      if(addr == mirror_address(code[i].addr[n])) {
+        data = code[i].data[n];
+        return true;
+      }
+    }
+  }
+
+  //code not found, or code is disabled
+  return false;
+}
+
+//==============
+//master control
+//==============
+
+//global cheat system enable/disable:
+//if disabled, *all* cheat codes are disabled;
+//otherwise only individually disabled codes are.
+
+bool Cheat::enabled() const {
+  return cheat_system_enabled;
+}
+
+void Cheat::enable() {
+  cheat_system_enabled = true;
+  cheat_enabled = (cheat_system_enabled && cheat_enabled_code_exists);
+}
+
+void Cheat::disable() {
+  cheat_system_enabled = false;
+  cheat_enabled = false;
+}
+
+//================================
+//cheat list manipulation routines
+//================================
+
+void Cheat::add(bool enable, const char *code_, const char *desc_) {
+  cheat_t item;
+  decode(code_, item);
+
+  unsigned i = code.size();
+  code[i] = item;
+  code[i].enabled = enable;
+  code[i].desc = desc_;
+  code[i].code = code_;
+  encode_description(code[i].desc);
+  update(code[i]);
+
+  update_cheat_status();
+}
+
+void Cheat::edit(unsigned i, bool enable, const char *code_, const char *desc_) {
+  cheat_t item;
+  decode(code_, item);
+
+  //disable current code and clear from code lookup table
+  code[i].enabled = false;
+  update(code[i]);
+
+  code[i] = item;
+  code[i].enabled = enable;
+  code[i].desc = desc_;
+  code[i].code = code_;
+  encode_description(code[i].desc);
+  update(code[i]);
+
+  update_cheat_status();
+}
+
+bool Cheat::remove(unsigned i) {
+  unsigned size = code.size();
+  if(i >= size) return false;  //also verifies size cannot be < 1
+
+  for(unsigned n = i; n < size - 1; n++) code[n] = code[n + 1];
+  code.resize(size - 1);
+
+  update_cheat_status();
+  return true;
+}
+
+bool Cheat::get(unsigned i, cheat_t &item) const {
+  if(i >= code.size()) return false;
+
+  item = code[i];
+  decode_description(item.desc);
+  return true;
+}
+
+//==============================
+//cheat status modifier routines
+//==============================
+
+bool Cheat::enabled(unsigned i) const {
+  return (i < code.size() ? code[i].enabled : false);
+}
+
+void Cheat::enable(unsigned i) {
+  if(i >= code.size()) return;
+
+  code[i].enabled = true;
+  update(code[i]);
+  update_cheat_status();
+}
+
+void Cheat::disable(unsigned i) {
+  if(i >= code.size()) return;
+
+  code[i].enabled = false;
+  update(code[i]);
+  update_cheat_status();
+}
+
+//===============================
+//cheat file load / save routines
+//
+//file format:
+//"description", status, nnnn-nnnn[+nnnn-nnnn...]\r\n
+//...
+//===============================
+
+void Cheat::load(string data) {
+  data.replace("\r", "");
+  data.qreplace(" ", "");
+
+  lstring line;
+  line.split("\n", data);
+  for(unsigned i = 0; i < line.size(); i++) {
+    lstring part;
+    part.qsplit(",", line[i]);
+    if(part.size() != 3) continue;
+    trim(part[2], "\"");
+    add(part[0] == "enabled", /* code = */ part[1], /* desc = */ part[2]);
+  }
+}
+
+string Cheat::save() const {
+  string data;
+  for(unsigned i = 0; i < code.size(); i++) {
+    data << (code[i].enabled ? "enabled," : "disabled,")
+         << code[i].code << ","
+         << "\"" << code[i].desc << "\"\r\n";
+  }
+  return data;
+}
+
+void Cheat::clear() {
+  cheat_enabled_code_exists = false;
+  memset(mask, 0, 0x200000);
+  code.reset();
+}
+
+Cheat::Cheat() : cheat_system_enabled(true) {
+  clear();
+}
+
+//==================
+//internal functions
+//==================
+
+//string <> binary code translation routines
+//decode() "7e123456" -> 0x7e123456
+//encode() 0x7e123456 -> "7e123456"
+
+bool Cheat::decode(const char *s, unsigned &addr, uint8_t &data, type_t &type) const {
+  string t = s;
+  strlower(t);
+
+  #define ischr(n) ((n >= '0' && n <= '9') || (n >= 'a' && n <= 'f'))
+
+  if(strlen(t) == 8 || (strlen(t) == 9 && t[6] == ':')) {
+    //strip ':'
+    if(strlen(t) == 9 && t[6] == ':') t = string() << substr(t, 0, 6) << substr(t, 7);
+    //validate input
+    for(unsigned i = 0; i < 8; i++) if(!ischr(t[i])) return false;
 
-bool Cheat::decode(char *str, uint32 &addr, uint8 &data, uint8 &type) {
-  string t, part;
-  strcpy(t, str);
-  strlower(t());
-  if(strlen(t) == 8 || (strlen(t) == 9 && t()[6] == ':')) {
     type = ProActionReplay;
-    replace(t, ":", "");
-    uint32 r = strhex((const char*)t);
+    unsigned r = strhex((const char*)t);
     addr = r >> 8;
     data = r & 0xff;
     return true;
-  } else if(strlen(t) == 9 && t()[4] == '-') {
+  } else if(strlen(t) == 9 && t[4] == '-') {
+    //strip '-'
+    t = string() << substr(t, 0, 4) << substr(t, 5);
+    //validate input
+    for(unsigned i = 0; i < 8; i++) if(!ischr(t[i])) return false;
+
     type = GameGenie;
-    replace(t, "-", "");
     strtr(t, "df4709156bc8a23e", "0123456789abcdef");
-    uint32 r = strhex((const char*)t);
+    unsigned r = strhex((const char*)t);
     //8421 8421 8421 8421 8421 8421
     //abcd efgh ijkl mnop qrst uvwx
     //ijkl qrst opab cduv wxef ghmn
-    addr = (!!(r & 0x002000) << 23) | (!!(r & 0x001000) << 22) |
-           (!!(r & 0x000800) << 21) | (!!(r & 0x000400) << 20) |
-           (!!(r & 0x000020) << 19) | (!!(r & 0x000010) << 18) |
-           (!!(r & 0x000008) << 17) | (!!(r & 0x000004) << 16) |
-           (!!(r & 0x800000) << 15) | (!!(r & 0x400000) << 14) |
-           (!!(r & 0x200000) << 13) | (!!(r & 0x100000) << 12) |
-           (!!(r & 0x000002) << 11) | (!!(r & 0x000001) << 10) |
-           (!!(r & 0x008000) <<  9) | (!!(r & 0x004000) <<  8) |
-           (!!(r & 0x080000) <<  7) | (!!(r & 0x040000) <<  6) |
-           (!!(r & 0x020000) <<  5) | (!!(r & 0x010000) <<  4) |
-           (!!(r & 0x000200) <<  3) | (!!(r & 0x000100) <<  2) |
-           (!!(r & 0x000080) <<  1) | (!!(r & 0x000040) <<  0);
+    addr = (!!(r & 0x002000) << 23) | (!!(r & 0x001000) << 22)
+         | (!!(r & 0x000800) << 21) | (!!(r & 0x000400) << 20)
+         | (!!(r & 0x000020) << 19) | (!!(r & 0x000010) << 18)
+         | (!!(r & 0x000008) << 17) | (!!(r & 0x000004) << 16)
+         | (!!(r & 0x800000) << 15) | (!!(r & 0x400000) << 14)
+         | (!!(r & 0x200000) << 13) | (!!(r & 0x100000) << 12)
+         | (!!(r & 0x000002) << 11) | (!!(r & 0x000001) << 10)
+         | (!!(r & 0x008000) <<  9) | (!!(r & 0x004000) <<  8)
+         | (!!(r & 0x080000) <<  7) | (!!(r & 0x040000) <<  6)
+         | (!!(r & 0x020000) <<  5) | (!!(r & 0x010000) <<  4)
+         | (!!(r & 0x000200) <<  3) | (!!(r & 0x000100) <<  2)
+         | (!!(r & 0x000080) <<  1) | (!!(r & 0x000040) <<  0);
     data = r >> 24;
     return true;
+  } else {
+    return false;
   }
-  return false;
 }
 
-bool Cheat::encode(char *str, uint32 addr, uint8 data, uint8 type) {
+bool Cheat::encode(string &s, unsigned addr, uint8_t data, type_t type) const {
+  char t[16];
+
   if(type == ProActionReplay) {
-    sprintf(str, "%0.6x:%0.2x", addr, data);
+    sprintf(t, "%.6x%.2x", addr, data);
+    s = t;
     return true;
   } else if(type == GameGenie) {
-  uint32 r = addr;
-    addr = (!!(r & 0x008000) << 23) | (!!(r & 0x004000) << 22) |
-           (!!(r & 0x002000) << 21) | (!!(r & 0x001000) << 20) |
-           (!!(r & 0x000080) << 19) | (!!(r & 0x000040) << 18) |
-           (!!(r & 0x000020) << 17) | (!!(r & 0x000010) << 16) |
-           (!!(r & 0x000200) << 15) | (!!(r & 0x000100) << 14) |
-           (!!(r & 0x800000) << 13) | (!!(r & 0x400000) << 12) |
-           (!!(r & 0x200000) << 11) | (!!(r & 0x100000) << 10) |
-           (!!(r & 0x000008) <<  9) | (!!(r & 0x000004) <<  8) |
-           (!!(r & 0x000002) <<  7) | (!!(r & 0x000001) <<  6) |
-           (!!(r & 0x080000) <<  5) | (!!(r & 0x040000) <<  4) |
-           (!!(r & 0x020000) <<  3) | (!!(r & 0x010000) <<  2) |
-           (!!(r & 0x000800) <<  1) | (!!(r & 0x000400) <<  0);
-    sprintf(str, "%0.2x%0.2x-%0.4x", data, addr >> 16, addr & 0xffff);
-    strtr(str, "0123456789abcdef", "df4709156bc8a23e");
+    unsigned r = addr;
+    addr = (!!(r & 0x008000) << 23) | (!!(r & 0x004000) << 22)
+         | (!!(r & 0x002000) << 21) | (!!(r & 0x001000) << 20)
+         | (!!(r & 0x000080) << 19) | (!!(r & 0x000040) << 18)
+         | (!!(r & 0x000020) << 17) | (!!(r & 0x000010) << 16)
+         | (!!(r & 0x000200) << 15) | (!!(r & 0x000100) << 14)
+         | (!!(r & 0x800000) << 13) | (!!(r & 0x400000) << 12)
+         | (!!(r & 0x200000) << 11) | (!!(r & 0x100000) << 10)
+         | (!!(r & 0x000008) <<  9) | (!!(r & 0x000004) <<  8)
+         | (!!(r & 0x000002) <<  7) | (!!(r & 0x000001) <<  6)
+         | (!!(r & 0x080000) <<  5) | (!!(r & 0x040000) <<  4)
+         | (!!(r & 0x020000) <<  3) | (!!(r & 0x010000) <<  2)
+         | (!!(r & 0x000800) <<  1) | (!!(r & 0x000400) <<  0);
+    sprintf(t, "%.2x%.2x-%.4x", data, addr >> 16, addr & 0xffff);
+    strtr(t, "0123456789abcdef", "df4709156bc8a23e");
+    s = t;
     return true;
+  } else {
+    return false;
   }
-  return false;
 }
 
-/*****
- * address lookup table manipulation and mirroring
- * mirror_address() 0x000000 -> 0x7e0000
- * set() enable specified address, mirror accordingly
- * clear() disable specified address, mirror accordingly
- *****/
+//speed up S-CPU memory reads by disabling cheat code lookup when either:
+//a) cheat system is disabled by user, or b) no enabled cheat codes exist
+void Cheat::update_cheat_status() {
+  for(unsigned i = 0; i < code.size(); i++) {
+    if(code[i].enabled) {
+      cheat_enabled_code_exists = true;
+      cheat_enabled = (cheat_system_enabled && cheat_enabled_code_exists);
+      return;
+    }
+  }
+  cheat_enabled_code_exists = false;
+  cheat_enabled = false;
+}
 
-uint Cheat::mirror_address(uint addr) {
+//address lookup table manipulation and mirroring
+//mirror_address() 0x000000 -> 0x7e0000
+//set() enable specified address, mirror accordingly
+//clear() disable specified address, mirror accordingly
+unsigned Cheat::mirror_address(unsigned addr) const {
   if((addr & 0x40e000) != 0x0000) return addr;
   //8k WRAM mirror
   //$[00-3f|80-bf]:[0000-1fff] -> $7e:[0000-1fff]
   return (0x7e0000 + (addr & 0x1fff));
 }
 
-void Cheat::set(uint32 addr) {
+//updates mask[] table enabled bits;
+//must be called after modifying item.enabled state.
+void Cheat::update(const cheat_t &item) {
+  for(unsigned n = 0; n < item.count; n++) {
+    (item.enabled) ? set(item.addr[n]) : clear(item.addr[n]);
+  }
+}
+
+void Cheat::set(unsigned addr) {
   addr = mirror_address(addr);
 
   mask[addr >> 3] |= 1 << (addr & 7);
   if((addr & 0xffe000) == 0x7e0000) {
     //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
-    uint mirror;
-    for(int x = 0; x <= 0x3f; x++) {
+    unsigned mirror;
+    for(unsigned x = 0; x <= 0x3f; x++) {
       mirror = ((0x00 + x) << 16) + (addr & 0x1fff);
       mask[mirror >> 3] |= 1 << (mirror & 7);
       mirror = ((0x80 + x) << 16) + (addr & 0x1fff);
@@ -101,20 +355,20 @@ void Cheat::set(uint32 addr) {
   }
 }
 
-void Cheat::clear(uint32 addr) {
+void Cheat::clear(unsigned addr) {
   addr = mirror_address(addr);
 
-  //is there more than one cheat code using the same address
-  //(and likely a different override value) that is enabled?
-  //if so, do not clear code lookup table entry for this address.
-  uint8 r;
-  if(read(addr, r) == true)return;
+  //if there is more than one cheat code using the same address,
+  //(eg with a different override value) then do not clear code
+  //lookup table entry.
+  uint8_t r;
+  if(read(addr, r) == true) return;
 
   mask[addr >> 3] &= ~(1 << (addr & 7));
   if((addr & 0xffe000) == 0x7e0000) {
     //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
-    uint mirror;
-    for(int x = 0; x <= 0x3f; x++) {
+    unsigned mirror;
+    for(unsigned x = 0; x <= 0x3f; x++) {
       mirror = ((0x00 + x) << 16) + (addr & 0x1fff);
       mask[mirror >> 3] &= ~(1 << (mirror & 7));
       mirror = ((0x80 + x) << 16) + (addr & 0x1fff);
@@ -123,207 +377,19 @@ void Cheat::clear(uint32 addr) {
   }
 }
 
-/*****
- * read() is used by MemBus::read() if Cheat::enabled(addr)
- * returns true to look up cheat code.
- * returns true if cheat code was found, false if it was not.
- * when true, cheat code substitution value is stored in data.
- *****/
+//these two functions are used to safely store description text inside .cfg file format.
 
-bool Cheat::read(uint32 addr, uint8 &data) {
-  addr = mirror_address(addr);
-  for(int i = 0; i < cheat_count; i++) {
-    if(enabled(i) == false) continue;
-    if(addr == mirror_address(index[i].addr)) {
-      data = index[i].data;
-      return true;
-    }
-  }
-  //code not found, or code is disabled
-  return false;
+string& Cheat::encode_description(string &desc) const {
+  desc.replace("\"", "\\q");
+  desc.replace("\n", "\\n");
+  return desc;
 }
 
-/*****
- * update_cheat_status() will scan to see if any codes are
- * enabled. if any are, make sure the cheat system is on.
- * otherwise, turn cheat system off to speed up emulation.
- *****/
-
-void Cheat::update_cheat_status() {
-  for(unsigned i = 0; i < cheat_count; i++) {
-    if(index[i].enabled) {
-      cheat_enabled = true;
-      return;
-    }
-  }
-  cheat_enabled = false;
+string& Cheat::decode_description(string &desc) const {
+  desc.replace("\\q", "\"");
+  desc.replace("\\n", "\n");
+  return desc;
 }
 
-/*****
- * cheat list manipulation routines
- *****/
+};
 
-bool Cheat::add(bool enable, char *code, char *desc) {
-  if(cheat_count >= CheatLimit) return false;
-
-  uint32 addr, len;
-  uint8  data, type;
-  if(decode(code, addr, data, type) == false) return false;
-
-  index[cheat_count].enabled = enable;
-  index[cheat_count].addr = addr;
-  index[cheat_count].data = data;
-  len = strlen(code);
-  len = len > 16 ? 16 : len;
-  memcpy(index[cheat_count].code, code, len);
-  index[cheat_count].code[len] = 0;
-  len = strlen(desc);
-  len = len > 128 ? 128 : len;
-  memcpy(index[cheat_count].desc, desc, len);
-  index[cheat_count].desc[len] = 0;
-  cheat_count++;
-  (enable) ? set(addr) : clear(addr);
-
-  update_cheat_status();
-  return true;
-}
-
-bool Cheat::edit(uint32 n, bool enable, char *code, char *desc) {
-  if(n >= cheat_count) return false;
-
-  uint32 addr, len;
-  uint8  data, type;
-  if(decode(code, addr, data, type) == false) return false;
-
-  //disable current code and clear from code lookup table
-  index[n].enabled = false;
-  clear(index[n].addr);
-
-  //update code and enable in code lookup table
-  index[n].enabled = enable;
-  index[n].addr = addr;
-  index[n].data = data;
-  len = strlen(code);
-  len = len > 16 ? 16 : len;
-  memcpy(index[n].code, code, len);
-  index[n].code[len] = 0;
-  len = strlen(desc);
-  len = len > 128 ? 128 : len;
-  memcpy(index[n].desc, desc, len);
-  index[n].desc[len] = 0;
-  set(addr);
-
-  update_cheat_status();
-  return true;
-}
-
-bool Cheat::remove(uint32 n) {
-  if(n >= cheat_count) return false;
-
-  for(unsigned i = n; i < cheat_count; i++) {
-    index[i].enabled = index[i + 1].enabled;
-    index[i].addr    = index[i + 1].addr;
-    index[i].data    = index[i + 1].data;
-    strcpy(index[i].desc, index[i + 1].desc);
-  }
-
-  cheat_count--;
-
-  update_cheat_status();
-  return true;
-}
-
-bool Cheat::get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc) {
-  if(n >= cheat_count) return false;
-  enable = index[n].enabled;
-  addr   = index[n].addr;
-  data   = index[n].data;
-  strcpy(code, index[n].code);
-  strcpy(desc, index[n].desc);
-  return true;
-}
-
-/*****
- * code status modifier routines
- *****/
-
-bool Cheat::enabled(uint32 n) {
-  if(n >= cheat_count) return false;
-  return index[n].enabled;
-}
-
-void Cheat::enable(uint32 n) {
-  if(n >= cheat_count) return;
-  index[n].enabled = true;
-  set(index[n].addr);
-  update_cheat_status();
-}
-
-void Cheat::disable(uint32 n) {
-  if(n >= cheat_count) return;
-  index[n].enabled = false;
-  clear(index[n].addr);
-  update_cheat_status();
-}
-
-/*****
- * cheat file manipulation routines
- *****/
-
-/* file format: */
-/* nnnn-nnnn = status, "description" \r\n */
-/* ... */
-
-bool Cheat::load(const char *fn) {
-  string data;
-  if(!fread(data, fn)) return false;
-  replace(data, "\r\n", "\n");
-  qreplace(data, "=", ",");
-  qreplace(data, " ", "");
-
-  lstring line;
-  split(line, "\n", data);
-  for(unsigned i = 0; i < ::count(line); i++) {
-    lstring part;
-    split(part, ",", line[i]);
-    if(::count(part) != 3) continue;
-    trim(part[2], "\"");
-    add(part[1] == "enabled", part[0](), part[2]());
-  }
-
-  return true;
-}
-
-bool Cheat::save(const char *fn) {
-  FILE *fp = fopen(fn, "wb");
-  if(!fp) return false;
-  for(unsigned i = 0; i < cheat_count; i++) {
-    fprintf(fp, "%9s = %8s, \"%s\"\r\n",
-      index[i].code,
-      index[i].enabled ? "enabled" : "disabled",
-      index[i].desc);
-  }
-  fclose(fp);
-  return true;
-}
-
-/*****
- * initialization routines
- *****/
-
-void Cheat::clear() {
-  cheat_enabled = false;
-  cheat_count = 0;
-  memset(mask, 0, 0x200000);
-  for(unsigned i = 0; i <= CheatLimit; i++) {
-    index[i].enabled = false;
-    index[i].addr = 0x000000;
-    index[i].data = 0x00;
-    strcpy(index[i].code, "");
-    strcpy(index[i].desc, "");
-  }
-}
-
-Cheat::Cheat() {
-  clear();
-}

src/cheat/cheat.h

@@ -1,51 +0,0 @@
-class Cheat {
-public:
-  enum { CheatLimit = 1024 };
-
-  enum Type {
-    ProActionReplay,
-    GameGenie,
-  };
-
-  struct CheatIndex {
-    bool enabled;
-    uint32 addr;
-    uint8 data;
-    char code[ 16 + 1];
-    char desc[128 + 1];
-  } index[CheatLimit + 1];
-
-  bool cheat_enabled;
-  uint32 cheat_count;
-  uint8 mask[0x200000];
-
-  inline bool enabled() { return cheat_enabled; }
-  inline uint count() { return cheat_count; }
-  inline bool exists(uint32 addr) { return bool(mask[addr >> 3] & 1 << (addr & 7)); }
-
-  bool decode(char *str, uint32 &addr, uint8 &data, uint8 &type);
-  bool encode(char *str, uint32  addr, uint8  data, uint8  type);
-
-  bool read(uint32 addr, uint8 &data);
-
-  void update_cheat_status();
-  bool add(bool enable, char *code, char *desc);
-  bool edit(uint32 n, bool enable, char *code, char *desc);
-  bool get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc);
-  bool remove(uint32 n);
-  bool enabled(uint32 n);
-  void enable(uint32 n);
-  void disable(uint32 n);
-  bool load(const char *fn);
-  bool save(const char *fn);
-  void clear();
-
-  Cheat();
-
-private:
-  uint mirror_address(uint addr);
-  void set(uint32 addr);
-  void clear(uint32 addr);
-};
-
-extern Cheat cheat;

src/cheat/cheat.hpp

@@ -0,0 +1,69 @@
+class Cheat {
+public:
+  enum type_t {
+    ProActionReplay,
+    GameGenie,
+  };
+
+  struct cheat_t {
+    bool enabled;
+    string code;
+    string desc;
+
+    unsigned count;
+    array<unsigned> addr;
+    array<uint8_t> data;
+
+    cheat_t& operator=(const cheat_t&);
+    bool operator<(const cheat_t&);
+  };
+
+  bool decode(const char *s, cheat_t &item) const;
+  bool read(unsigned addr, uint8_t &data) const;
+
+  bool enabled() const;
+  void enable();
+  void disable();
+
+  inline unsigned count() const;
+  inline bool active() const;
+  inline bool exists(unsigned addr) const;
+
+  void add(bool enable, const char *code, const char *desc);
+  void edit(unsigned i, bool enable, const char *code, const char *desc);
+  bool remove(unsigned i);
+  bool get(unsigned i, cheat_t &item) const;
+
+  bool enabled(unsigned i) const;
+  void enable(unsigned i);
+  void disable(unsigned i);
+
+  void load(string data);
+  string save() const;
+  void clear();
+
+  Cheat();
+
+private:
+  bool cheat_enabled;  //cheat_enabled == (cheat_enabled_code_exists && cheat_system_enabled);
+  bool cheat_enabled_code_exists;
+  bool cheat_system_enabled;
+
+  uint8_t mask[0x200000];
+  vector<cheat_t> code;
+
+  bool decode(const char *str, unsigned &addr, uint8_t &data, type_t &type) const;
+  bool encode(string &str, unsigned addr, uint8_t data, type_t type) const;
+
+  void update_cheat_status();
+  unsigned mirror_address(unsigned addr) const;
+
+  void update(const cheat_t& item);
+  void set(unsigned addr);
+  void clear(unsigned addr);
+
+  string& encode_description(string &desc) const;
+  string& decode_description(string &desc) const;
+};
+
+extern Cheat cheat;

src/chip/21fx/21fx.cpp

@@ -0,0 +1,165 @@
+#include <../base.hpp>
+
+//$21f0  command port (r/w)
+//-------------------
+//$00  set data port address (sr[3-0] = address)
+//$01  set audio track number (sr[1-0] = track number)
+//$02  set volume (sr[1] = left, sr[0] = right)
+//$03  set audio state (sr[0].d1 = pause, sr[0].d0 = repeat)
+//
+//d7 = data port busy
+//d6 = audio port busy
+//d5 = audio playing
+//d4 = reserved (0)
+//d3-d0 = version (1)
+//
+//
+//$21f1  parameter port (w)
+//---------------------
+//(shift register)
+//
+//
+//$21f2  data port (r)
+//----------------
+//(auto-increment read port)
+
+#define S21FX_CPP
+namespace SNES {
+
+S21fx s21fx;
+
+#include "serialization.cpp"
+
+void S21fx::enter() {
+  scheduler.clock.cop_freq = 44100;
+
+  while(true) {
+    int16 left = 0, right = 0;
+
+    if((mmio.status & AudioPlaying) && !mmio.audio_pause) {
+      if(audiofile.open()) {
+        if(audiofile.end()) {
+          if(!mmio.audio_repeat) mmio.status &= ~AudioPlaying;
+          audiofile.seek(mmio.audio_offset = 58);
+        } else {
+          mmio.audio_offset += 4;
+          left = audiofile.readl(2);
+          right = audiofile.readl(2);
+        }
+      } else {
+        mmio.status &= ~AudioPlaying;
+      }
+    }
+
+    left  = sclamp<16>((double)left  * (double)mmio.audio_volume_left  / 255.0);
+    right = sclamp<16>((double)right * (double)mmio.audio_volume_right / 255.0);
+
+    audio.coprocessor_sample(left, right);
+    scheduler.addclocks_cop(1);
+    scheduler.sync_copcpu();
+  }
+}
+
+void S21fx::init() {
+}
+
+void S21fx::enable() {
+  audio.coprocessor_enable(true);
+  audio.coprocessor_frequency(44100.0);
+
+  for(unsigned i = 0x21f0; i <= 0x21f7; i++) {
+    memory::mmio.map(i, *this);
+  }
+
+  if(datafile.open()) datafile.close();
+  datafile.open(string() << basepath << "21fx.bin", file::mode_read);
+}
+
+void S21fx::power() {
+  reset();
+}
+
+void S21fx::reset() {
+  mmio.status = DataPortBusy | AudioBusy;
+  mmio.shift_register = 0;
+
+  mmio.data_offset  = 0;
+  mmio.audio_offset = 0;
+  mmio.audio_track  = 0;
+  mmio.audio_volume_left  = 255;
+  mmio.audio_volume_right = 255;
+  mmio.audio_repeat = false;
+  mmio.audio_pause  = false;
+}
+
+uint8 S21fx::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+
+  if(addr == 0x21f0) {
+    return mmio.status | 0x01;
+  }
+
+  if(addr == 0x21f2) {
+    if(mmio.status & DataPortBusy) return 0x00;
+    mmio.data_offset++;
+    if(datafile.open()) return datafile.read();
+    return 0x00;
+  }
+
+  return 0x00;
+}
+
+void S21fx::mmio_write(unsigned addr, uint8 data) {
+  addr &= 0xffff;
+
+  if(addr == 0x21f0) {
+    if(data == 0x00) {
+      mmio.data_offset = mmio.shift_register & 0xffffffff;
+      if(datafile.open()) {
+        datafile.seek(mmio.data_offset);
+      }
+      mmio.status &= ~DataPortBusy;
+    }
+
+    if(data == 0x01) {
+      mmio.audio_track = mmio.shift_register & 0xffff;
+      if(audiofile.open()) audiofile.close();
+      char track[16];
+      sprintf(track, "%.5u", mmio.audio_track);
+      if(audiofile.open(string() << basepath << "audio" << track << ".wav", file::mode_read)) {
+        audiofile.seek(mmio.audio_offset = 58);  //skip WAV header
+      }
+      mmio.status &= ~(AudioBusy | AudioPlaying);
+    }
+
+    if(data == 0x02) {
+      mmio.audio_volume_left  = mmio.shift_register >> 8;
+      mmio.audio_volume_right = mmio.shift_register >> 0;
+    }
+
+    if(data == 0x03) {
+      mmio.status |= AudioPlaying;
+      mmio.audio_repeat = mmio.shift_register & 1;
+      mmio.audio_pause  = mmio.shift_register & 2;
+    }
+
+    mmio.shift_register = 0;
+  }
+
+  if(addr == 0x21f1) {
+    mmio.shift_register = (mmio.shift_register << 8) | data;
+  }
+}
+
+void S21fx::base(const string& path) {
+  basepath = path;
+}
+
+bool S21fx::exists() {
+  return file::exists(string() << basepath << "21fx.bin");
+}
+
+S21fx::S21fx() {
+}
+
+}

src/chip/21fx/21fx.hpp

@@ -0,0 +1,44 @@
+class S21fx : public MMIO {
+public:
+  void enter();
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
+
+  void base(const string &path);
+  bool exists();
+
+  void serialize(serializer&);
+  S21fx();
+
+private:
+  string basepath;
+  file datafile;
+  file audiofile;
+
+  enum Flag {
+    DataPortBusy = 0x80,
+    AudioBusy    = 0x40,
+    AudioPlaying = 0x20,
+  };
+
+  struct MMIO {
+    uint8 status;
+    uint64 shift_register;
+
+    uint32 data_offset;
+    uint32 audio_offset;
+    uint16 audio_track;
+    uint8 audio_volume_left;
+    uint8 audio_volume_right;
+    bool audio_repeat;
+    bool audio_pause;
+  } mmio;
+};
+
+extern S21fx s21fx;

src/chip/21fx/serialization.cpp

@@ -0,0 +1,31 @@
+#ifdef S21FX_CPP
+
+void S21fx::serialize(serializer &s) {
+  s.integer(mmio.status);
+  s.integer(mmio.shift_register);
+
+  s.integer(mmio.data_offset);
+  s.integer(mmio.audio_offset);
+  s.integer(mmio.audio_track);
+  s.integer(mmio.audio_volume_left);
+  s.integer(mmio.audio_volume_right);
+  s.integer(mmio.audio_repeat);
+  s.integer(mmio.audio_pause);
+
+  //flush file handles and indices, as a different track may be playing,
+  //or the file offsets may be at the wrong location ...
+
+  if(datafile.open()) datafile.close();
+  if(datafile.open(string() << basepath << "21fx.bin", file::mode_read)) {
+    datafile.seek(mmio.data_offset);
+  }
+
+  if(audiofile.open()) audiofile.close();
+  char track[16];
+  sprintf(track, "%.5u", mmio.audio_track);
+  if(audiofile.open(string() << basepath << "audio" << track << ".wav", file::mode_read)) {
+    audiofile.seek(mmio.audio_offset);
+  }
+}
+
+#endif

src/chip/bsx/bsx.cpp

@@ -1,6 +1,10 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define BSX_CPP
+namespace SNES {
 
 #include "bsx_base.cpp"
 #include "bsx_cart.cpp"
 #include "bsx_flash.cpp"
+};
+

src/chip/bsx/bsx.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 mmio_read(uint addr);
-  void mmio_write(uint addr, uint8 data);
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
 
 private:
   struct {
@@ -29,19 +29,13 @@ public:
   void power();
   void reset();
 
-  uint8 mmio_read(uint addr);
-  void mmio_write(uint addr, uint8 data);
-
-  MappedRAM sram;
-  MappedRAM psram;
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
 
   BSXCart();
   ~BSXCart();
 
 private:
-  uint8 *sram_data;  //256kbit SRAM
-  uint8 *psram_data; //  4mbit PSRAM
-
   struct {
     uint8 r[16];
   } regs;
@@ -56,13 +50,13 @@ public:
   void power();
   void reset();
 
-  uint size();
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  unsigned size() const;
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 
 private:
   struct {
-    uint command;
+    unsigned command;
     uint8 write_old;
     uint8 write_new;
 

src/chip/bsx/bsx_base.cpp

@@ -1,5 +1,7 @@
 #ifdef BSX_CPP
 
+BSXBase bsxbase;
+
 void BSXBase::init() {
 }
 
@@ -15,7 +17,7 @@ void BSXBase::reset() {
   memset(&regs, 0x00, sizeof regs);
 }
 
-uint8 BSXBase::mmio_read(uint addr) {
+uint8 BSXBase::mmio_read(unsigned addr) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -28,13 +30,13 @@ uint8 BSXBase::mmio_read(uint addr) {
     case 0x2190: return regs.r2190;
 
     case 0x2192: {
-    uint counter = regs.r2192_counter++;
+      unsigned counter = regs.r2192_counter++;
       if(regs.r2192_counter >= 18) regs.r2192_counter = 0;
 
       if(counter == 0) {
-      time_t rawtime;
+        time_t rawtime;
         time(&rawtime);
-      tm *t = localtime(&rawtime);
+        tm *t = localtime(&rawtime);
 
         regs.r2192_hour   = t->tm_hour;
         regs.r2192_minute = t->tm_min;
@@ -42,11 +44,11 @@ uint8 BSXBase::mmio_read(uint addr) {
       }
 
       switch(counter) {
-        case  0: return 0x00; //???
-        case  1: return 0x00; //???
-        case  2: return 0x00; //???
-        case  3: return 0x00; //???
-        case  4: return 0x00; //???
+        case  0: return 0x00;  //???
+        case  1: return 0x00;  //???
+        case  2: return 0x00;  //???
+        case  3: return 0x00;  //???
+        case  4: return 0x00;  //???
         case  5: return 0x01;
         case  6: return 0x01;
         case  7: return 0x00;
@@ -55,11 +57,11 @@ uint8 BSXBase::mmio_read(uint addr) {
         case 10: return regs.r2192_second;
         case 11: return regs.r2192_minute;
         case 12: return regs.r2192_hour;
-        case 13: return 0x00; //???
-        case 14: return 0x00; //???
-        case 15: return 0x00; //???
-        case 16: return 0x00; //???
-        case 17: return 0x00; //???
+        case 13: return 0x00;  //???
+        case 14: return 0x00;  //???
+        case 15: return 0x00;  //???
+        case 16: return 0x00;  //???
+        case 17: return 0x00;  //???
       }
     } break;
 
@@ -73,7 +75,7 @@ uint8 BSXBase::mmio_read(uint addr) {
   return cpu.regs.mdr;
 }
 
-void BSXBase::mmio_write(uint addr, uint8 data) {
+void BSXBase::mmio_write(unsigned addr, uint8 data) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -134,4 +136,5 @@ void BSXBase::mmio_write(uint addr, uint8 data) {
   }
 }
 
-#endif //ifdef BSX_CPP
+#endif
+

src/chip/bsx/bsx_cart.cpp

@@ -1,5 +1,7 @@
 #ifdef BSX_CPP
 
+BSXCart bsxcart;
+
 void BSXCart::init() {
 }
 
@@ -12,7 +14,7 @@ void BSXCart::power() {
 }
 
 void BSXCart::reset() {
-  for(uint i = 0; i < 16; i++) regs.r[i] = 0x00;
+  for(unsigned i = 0; i < 16; i++) regs.r[i] = 0x00;
   regs.r[0x07] = 0x80;
   regs.r[0x08] = 0x80;
 
@@ -20,12 +22,14 @@ void BSXCart::reset() {
 }
 
 void BSXCart::update_memory_map() {
-  Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)psram;
+  Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)memory::bsxpram;
 
-  if((regs.r[0x02] & 0x80) == 0x00) { //LoROM mapping
+  if((regs.r[0x02] & 0x80) == 0x00) {
+    //LoROM mapping
     bus.map(Bus::MapLinear, 0x00, 0x7d, 0x8000, 0xffff, cart);
     bus.map(Bus::MapLinear, 0x80, 0xff, 0x8000, 0xffff, cart);
-  } else { //HiROM mapping
+  } else {
+    //HiROM mapping
     bus.map(Bus::MapShadow, 0x00, 0x3f, 0x8000, 0xffff, cart);
     bus.map(Bus::MapLinear, 0x40, 0x7d, 0x0000, 0xffff, cart);
     bus.map(Bus::MapShadow, 0x80, 0xbf, 0x8000, 0xffff, cart);
@@ -33,16 +37,16 @@ void BSXCart::update_memory_map() {
   }
 
   if(regs.r[0x03] & 0x80) {
-    bus.map(Bus::MapLinear, 0x60, 0x6f, 0x0000, 0xffff, psram);
-  //bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
+    bus.map(Bus::MapLinear, 0x60, 0x6f, 0x0000, 0xffff, memory::bsxpram);
+  //bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, memory::bsxpram);
   }
 
   if((regs.r[0x05] & 0x80) == 0x00) {
-    bus.map(Bus::MapLinear, 0x40, 0x4f, 0x0000, 0xffff, psram);
+    bus.map(Bus::MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::bsxpram);
   }
 
   if((regs.r[0x06] & 0x80) == 0x00) {
-    bus.map(Bus::MapLinear, 0x50, 0x5f, 0x0000, 0xffff, psram);
+    bus.map(Bus::MapLinear, 0x50, 0x5f, 0x0000, 0xffff, memory::bsxpram);
   }
 
   if(regs.r[0x07] & 0x80) {
@@ -53,47 +57,41 @@ void BSXCart::update_memory_map() {
     bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom);
   }
 
-  bus.map(Bus::MapShadow, 0x20, 0x3f, 0x6000, 0x7fff, psram);
-  bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
+  bus.map(Bus::MapShadow, 0x20, 0x3f, 0x6000, 0x7fff, memory::bsxpram);
+  bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, memory::bsxpram);
 }
 
-uint8 BSXCart::mmio_read(uint addr) {
-  if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
+uint8 BSXCart::mmio_read(unsigned addr) {
+  if((addr & 0xf0ffff) == 0x005000) {  //$[00-0f]:5000 MMIO
     uint8 n = (addr >> 16) & 15;
     return regs.r[n];
   }
 
-  if((addr & 0xf8f000) == 0x105000) { //$[10-17]:[5000-5fff] SRAM
-    return sram.read(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
+  if((addr & 0xf8f000) == 0x105000) {  //$[10-17]:[5000-5fff] SRAM
+    return memory::bsxram.read(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
   }
 
   return 0x00;
 }
 
-void BSXCart::mmio_write(uint addr, uint8 data) {
-  if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
+void BSXCart::mmio_write(unsigned addr, uint8 data) {
+  if((addr & 0xf0ffff) == 0x005000) {  //$[00-0f]:5000 MMIO
     uint8 n = (addr >> 16) & 15;
     regs.r[n] = data;
     if(n == 0x0e && data & 0x80) update_memory_map();
     return;
   }
 
-  if((addr & 0xf8f000) == 0x105000) { //$[10-17]:[5000-5fff] SRAM
-    return sram.write(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
+  if((addr & 0xf8f000) == 0x105000) {  //$[10-17]:[5000-5fff] SRAM
+    return memory::bsxram.write(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
   }
 }
 
 BSXCart::BSXCart() {
-  sram_data  = new uint8_t[ 32 * 1024];
-  psram_data = new uint8_t[512 * 1024];
-
-  sram.map (sram_data,   32 * 1024);
-  psram.map(psram_data, 512 * 1024);
 }
 
 BSXCart::~BSXCart() {
-  delete[] sram_data;
-  delete[] psram_data;
 }
 
-#endif //ifdef BSX_CPP
+#endif
+

src/chip/bsx/bsx_flash.cpp

@@ -1,5 +1,7 @@
 #ifdef BSX_CPP
 
+BSXFlash bsxflash;
+
 void BSXFlash::init() {}
 void BSXFlash::enable() {}
 
@@ -15,13 +17,14 @@ void BSXFlash::reset() {
   regs.flash_enable = false;
   regs.read_enable  = false;
   regs.write_enable = false;
+  memory::bsxflash.write_protect(!regs.write_enable);
 }
 
-uint BSXFlash::size() {
-  return memory::bscram.size();
+unsigned BSXFlash::size() const {
+  return memory::bsxflash.size();
 }
 
-uint8 BSXFlash::read(uint addr) {
+uint8 BSXFlash::read(unsigned addr) {
   if(addr == 0x0002) {
     if(regs.flash_enable) return 0x80;
   }
@@ -31,7 +34,7 @@ uint8 BSXFlash::read(uint addr) {
   }
 
   if(regs.read_enable && addr >= 0xff00 && addr <= 0xff13) {
-  //read flash cartridge vendor information
+    //read flash cartridge vendor information
     switch(addr - 0xff00) {
       case 0x00: return 0x4d;
       case 0x01: return 0x00;
@@ -39,24 +42,24 @@ uint8 BSXFlash::read(uint addr) {
       case 0x03: return 0x00;
       case 0x04: return 0x00;
       case 0x05: return 0x00;
-      case 0x06: return 0x2a; //0x2a = 8mbit, 0x2b = 16mbit (not known to exist, though BIOS recognizes ID)
+      case 0x06: return 0x2a;  //0x2a = 8mbit, 0x2b = 16mbit (not known to exist, though BIOS recognizes ID)
       case 0x07: return 0x00;
       default:   return 0x00;
     }
   }
 
-  return memory::bscram.read(addr);
+  return memory::bsxflash.read(addr);
 }
 
-void BSXFlash::write(uint addr, uint8 data) {
-//there exist both read-only and read-write BS-X flash cartridges ...
-//unfortunately, the vendor info is not stored inside memory dumps
-//of BS-X flashcarts, so it is impossible to determine whether a
-//given flashcart is writeable.
-//however, it has been observed that LoROM-mapped BS-X carts always
-//use read-write flashcarts, and HiROM-mapped BS-X carts always use
-//read-only flashcarts.
-//below is an unfortunately necessary workaround to this problem.
+void BSXFlash::write(unsigned addr, uint8 data) {
+  //there exist both read-only and read-write BS-X flash cartridges ...
+  //unfortunately, the vendor info is not stored inside memory dumps
+  //of BS-X flashcarts, so it is impossible to determine whether a
+  //given flashcart is writeable.
+  //however, it has been observed that LoROM-mapped BS-X carts always
+  //use read-write flashcarts, and HiROM-mapped BS-X carts always use
+  //read-only flashcarts.
+  //below is an unfortunately necessary workaround to this problem.
   if(cartridge.mapper() == Cartridge::BSCHiROM) return;
 
   if((addr & 0xff0000) == 0) {
@@ -64,11 +67,11 @@ void BSXFlash::write(uint addr, uint8 data) {
     regs.write_new = data;
 
     if(regs.write_enable && regs.write_old == regs.write_new) {
-      return memory::bscram.write(addr, data);
+      return memory::bsxflash.write(addr, data);
     }
   } else {
     if(regs.write_enable) {
-      return memory::bscram.write(addr, data);
+      return memory::bsxflash.write(addr, data);
     }
   }
 
@@ -107,7 +110,10 @@ void BSXFlash::write(uint addr, uint8 data) {
       regs.read_enable  = false;
       regs.write_enable = false;
     }
+
+    memory::bsxflash.write_protect(!regs.write_enable);
   }
 }
 
-#endif //ifdef BSX_CPP
+#endif
+

src/chip/chip.h

@@ -1,11 +0,0 @@
-#include "bsx/bsx.h"
-#include "srtc/srtc.h"
-#include "sdd1/sdd1.h"
-#include "spc7110/spc7110.h"
-#include "cx4/cx4.h"
-#include "dsp1/dsp1.h"
-#include "dsp2/dsp2.h"
-#include "dsp3/dsp3.h"
-#include "dsp4/dsp4.h"
-#include "obc1/obc1.h"
-#include "st010/st010.h"

src/chip/chip.hpp

@@ -0,0 +1,17 @@
+#include "supergameboy/supergameboy.hpp"
+#include "superfx/superfx.hpp"
+#include "sa1/sa1.hpp"
+#include "bsx/bsx.hpp"
+#include "srtc/srtc.hpp"
+#include "sdd1/sdd1.hpp"
+#include "spc7110/spc7110.hpp"
+#include "cx4/cx4.hpp"
+#include "dsp1/dsp1.hpp"
+#include "dsp2/dsp2.hpp"
+#include "dsp3/dsp3.hpp"
+#include "dsp4/dsp4.hpp"
+#include "obc1/obc1.hpp"
+#include "st010/st010.hpp"
+#include "st011/st011.hpp"
+#include "st018/st018.hpp"
+#include "21fx/21fx.hpp"

src/chip/cx4/cx4.cpp

@@ -1,36 +1,47 @@
-/*
-  C4 emulation
+//=============
+//Cx4 emulation
+//=============
+//Used in Rockman X2/X3 (Megaman X2/X3)
+//Portions (c) anomie, Overload, zsKnight, Nach, byuu
 
-  Used in Rockman X2/X3 (Megaman X2/X3)
-  Portions (c) anomie, Overload, zsKnight, Nach, byuu
-*/
+#include <../base.hpp>
 
-#include "../../base.h"
 #define CX4_CPP
+namespace SNES {
 
-#include "cx4data.cpp"
-#include "cx4fn.cpp"
-#include "cx4oam.cpp"
-#include "cx4ops.cpp"
+Cx4 cx4;
 
-void Cx4::init() {}
-void Cx4::enable() {}
+#include "serialization.cpp"
+#include "data.cpp"
+#include "functions.cpp"
+#include "oam.cpp"
+#include "opcodes.cpp"
+
+void Cx4::init() {
+}
+
+void Cx4::enable() {
+  bus.map(Bus::MapDirect, 0x00, 0x3f, 0x6000, 0x7fff, *this);
+  bus.map(Bus::MapDirect, 0x80, 0xbf, 0x6000, 0x7fff, *this);
+}
 
 uint32 Cx4::ldr(uint8 r) {
-uint16 addr = 0x0080 + (r * 3);
-  return (reg[addr]) | (reg[addr + 1] << 8) | (reg[addr + 2] << 16);
+  uint16 addr = 0x0080 + (r * 3);
+  return (reg[addr + 0] <<  0)
+       | (reg[addr + 1] <<  8)
+       | (reg[addr + 2] << 16);
 }
 
 void Cx4::str(uint8 r, uint32 data) {
-uint16 addr = 0x0080 + (r * 3);
-  reg[addr    ] = (data);
-  reg[addr + 1] = (data >> 8);
+  uint16 addr = 0x0080 + (r * 3);
+  reg[addr + 0] = (data >>  0);
+  reg[addr + 1] = (data >>  8);
   reg[addr + 2] = (data >> 16);
 }
 
 void Cx4::mul(uint32 x, uint32 y, uint32 &rl, uint32 &rh) {
-int64 rx = x & 0xffffff;
-int64 ry = y & 0xffffff;
+  int64 rx = x & 0xffffff;
+  int64 ry = y & 0xffffff;
   if(rx & 0x800000)rx |= ~0x7fffff;
   if(ry & 0x800000)ry |= ~0x7fffff;
 
@@ -67,8 +78,9 @@ void Cx4::immediate_reg(uint32 start) {
 }
 
 void Cx4::transfer_data() {
-uint32 src;
-uint16 dest, count;
+  uint32 src;
+  uint16 dest, count;
+
   src   = (reg[0x40]) | (reg[0x41] << 8) | (reg[0x42] << 16);
   count = (reg[0x43]) | (reg[0x44] << 8);
   dest  = (reg[0x45]) | (reg[0x46] << 8);
@@ -78,33 +90,33 @@ uint16 dest, count;
   }
 }
 
-void Cx4::write(uint addr, uint8 data) {
+void Cx4::write(unsigned addr, uint8 data) {
   addr &= 0x1fff;
 
   if(addr < 0x0c00) {
-  //ram
+    //ram
     ram[addr] = data;
     return;
   }
 
   if(addr < 0x1f00) {
-  //unmapped
+    //unmapped
     return;
   }
 
-//command register
+  //command register
   reg[addr & 0xff] = data;
 
   if(addr == 0x1f47) {
-  //memory transfer
+    //memory transfer
     transfer_data();
     return;
   }
 
   if(addr == 0x1f4f) {
-  //c4 command
+    //c4 command
     if(reg[0x4d] == 0x0e && !(data & 0xc3)) {
-    //c4 test command
+      //c4 test command
       reg[0x80] = data >> 2;
       return;
     }
@@ -150,17 +162,17 @@ void Cx4::writeb(uint16 addr, uint8 data) {
 }
 
 void Cx4::writew(uint16 addr, uint16 data) {
-  write(addr,     data);
+  write(addr + 0, data >> 0);
   write(addr + 1, data >> 8);
 }
 
 void Cx4::writel(uint16 addr, uint32 data) {
-  write(addr,     data);
+  write(addr + 0, data >>  0);
   write(addr + 1, data >>  8);
   write(addr + 2, data >> 16);
 }
 
-uint8 Cx4::read(uint addr) {
+uint8 Cx4::read(unsigned addr) {
   addr &= 0x1fff;
 
   if(addr < 0x0c00) {
@@ -194,3 +206,5 @@ void Cx4::reset() {
   memset(ram, 0, 0x0c00);
   memset(reg, 0, 0x0100);
 }
+
+};

src/chip/cx4/cx4.hpp

@@ -1,4 +1,15 @@
 class Cx4 : public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
+
+  void serialize(serializer&);
+
 private:
   uint8  ram[0x0c00];
   uint8  reg[0x0100];
@@ -15,9 +26,6 @@ private:
   int16 C4WFXVal, C4WFYVal, C4WFZVal, C4WFX2Val, C4WFY2Val, C4WFDist, C4WFScale;
   int16 C41FXVal, C41FYVal, C41FAngleRes, C41FDist, C41FDistVal;
 
-  double tanval;
-  double c4x,c4y,c4z, c4x2,c4y2,c4z2;
-
   void C4TransfWireFrame();
   void C4TransfWireFrame2();
   void C4CalcWireFrame();
@@ -82,16 +90,6 @@ public:
   void   writeb(uint16 addr, uint8 data);
   void   writew(uint16 addr, uint16 data);
   void   writel(uint16 addr, uint32 data);
-
-//
-
-  void   init();
-  void   enable();
-  void   power();
-  void   reset();
-
-  uint8  read (uint addr);
-  void   write(uint addr, uint8 data);
 };
 
 extern Cx4 cx4;

src/chip/cx4/data.cpp

@@ -184,4 +184,4 @@ const int16 Cx4::CosTable[512] = {
    32610,  32647,  32679,  32706,  32728,  32745,  32758,  32765
 };
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/functions.cpp

@@ -10,26 +10,27 @@
 
 //Wireframe Helpers
 void Cx4::C4TransfWireFrame() {
-  c4x = (double)C4WFXVal;
-  c4y = (double)C4WFYVal;
-  c4z = (double)C4WFZVal - 0x95;
+  double c4x = (double)C4WFXVal;
+  double c4y = (double)C4WFYVal;
+  double c4z = (double)C4WFZVal - 0x95;
+  double tanval, c4x2, c4y2, c4z2;
 
-//Rotate X
+  //Rotate X
   tanval = -(double)C4WFX2Val * PI * 2 / 128;
   c4y2   = c4y * ::cos(tanval) - c4z * ::sin(tanval);
   c4z2   = c4y * ::sin(tanval) + c4z * ::cos(tanval);
 
-//Rotate Y
+  //Rotate Y
   tanval = -(double)C4WFY2Val * PI * 2 / 128;
   c4x2   = c4x * ::cos(tanval)  + c4z2 * ::sin(tanval);
   c4z    = c4x * -::sin(tanval) + c4z2 * ::cos(tanval);
 
-//Rotate Z
+  //Rotate Z
   tanval = -(double)C4WFDist * PI * 2 / 128;
   c4x    = c4x2 * ::cos(tanval) - c4y2 * ::sin(tanval);
   c4y    = c4x2 * ::sin(tanval) + c4y2 * ::cos(tanval);
 
-//Scale
+  //Scale
   C4WFXVal = (int16)(c4x * C4WFScale / (0x90 * (c4z + 0x95)) * 0x95);
   C4WFYVal = (int16)(c4y * C4WFScale / (0x90 * (c4z + 0x95)) * 0x95);
 }
@@ -52,39 +53,41 @@ void Cx4::C4CalcWireFrame() {
 }
 
 void Cx4::C4TransfWireFrame2() {
-  c4x = (double)C4WFXVal;
-  c4y = (double)C4WFYVal;
-  c4z = (double)C4WFZVal;
+  double c4x = (double)C4WFXVal;
+  double c4y = (double)C4WFYVal;
+  double c4z = (double)C4WFZVal;
+  double tanval, c4x2, c4y2, c4z2;
 
-//Rotate X
+  //Rotate X
   tanval = -(double)C4WFX2Val * PI * 2 / 128;
   c4y2   = c4y * ::cos(tanval) - c4z * ::sin(tanval);
   c4z2   = c4y * ::sin(tanval) + c4z * ::cos(tanval);
 
-//Rotate Y
+  //Rotate Y
   tanval = -(double)C4WFY2Val * PI * 2 / 128;
   c4x2   = c4x * ::cos(tanval)  + c4z2 * ::sin(tanval);
   c4z    = c4x * -::sin(tanval) + c4z2 * ::cos(tanval);
 
-//Rotate Z
+  //Rotate Z
   tanval = -(double)C4WFDist * PI * 2 / 128;
   c4x    = c4x2 * ::cos(tanval) - c4y2 * ::sin(tanval);
   c4y    = c4x2 * ::sin(tanval) + c4y2 * ::cos(tanval);
 
-//Scale
+  //Scale
   C4WFXVal = (int16)(c4x * C4WFScale / 0x100);
   C4WFYVal = (int16)(c4y * C4WFScale / 0x100);
 }
 
 void Cx4::C4DrawWireFrame() {
-uint32 line = readl(0x1f80);
-uint32 point1, point2;
-int16 X1, Y1, Z1;
-int16 X2, Y2, Z2;
-uint8 Color;
+  uint32 line = readl(0x1f80);
+  uint32 point1, point2;
+  int16 X1, Y1, Z1;
+  int16 X2, Y2, Z2;
+  uint8 Color;
+
   for(int32 i = ram[0x0295]; i > 0; i--, line += 5) {
     if(bus.read(line) == 0xff && bus.read(line + 1) == 0xff) {
-    int32 tmp = line - 5;
+      int32 tmp = line - 5;
       while(bus.read(tmp + 2) == 0xff && bus.read(tmp + 3) == 0xff && (tmp + 2) >= 0) { tmp -= 5; }
       point1 = (read(0x1f82) << 16) | (bus.read(tmp + 2) << 8) | bus.read(tmp + 3);
     } else {
@@ -104,7 +107,7 @@ uint8 Color;
 }
 
 void Cx4::C4DrawLine(int32 X1, int32 Y1, int16 Z1, int32 X2, int32 Y2, int16 Z2, uint8 Color) {
-//Transform coordinates
+  //Transform coordinates
   C4WFXVal  = (int16)X1;
   C4WFYVal  = (int16)Y1;
   C4WFZVal  = Z1;
@@ -123,7 +126,7 @@ void Cx4::C4DrawLine(int32 X1, int32 Y1, int16 Z1, int32 X2, int32 Y2, int16 Z2,
   X2 = (C4WFXVal + 48) << 8;
   Y2 = (C4WFYVal + 48) << 8;
 
-//Get line info
+  //Get line info
   C4WFXVal  = (int16)(X1 >> 8);
   C4WFYVal  = (int16)(Y1 >> 8);
   C4WFX2Val = (int16)(X2 >> 8);
@@ -132,15 +135,15 @@ void Cx4::C4DrawLine(int32 X1, int32 Y1, int16 Z1, int32 X2, int32 Y2, int16 Z2,
   X2 = (int16)C4WFXVal;
   Y2 = (int16)C4WFYVal;
 
-//Render line
+  //Render line
   for(int32 i = C4WFDist ? C4WFDist : 1; i > 0; i--) {
     if(X1 > 0xff && Y1 > 0xff && X1 < 0x6000 && Y1 < 0x6000) {
-    uint16 addr = (((Y1 >> 8) >> 3) << 8) - (((Y1 >> 8) >> 3) << 6) + (((X1 >> 8) >> 3) << 4) + ((Y1 >> 8) & 7) * 2;
-    uint8 bit = 0x80 >> ((X1 >> 8) & 7);
+      uint16 addr = (((Y1 >> 8) >> 3) << 8) - (((Y1 >> 8) >> 3) << 6) + (((X1 >> 8) >> 3) << 4) + ((Y1 >> 8) & 7) * 2;
+      uint8 bit = 0x80 >> ((X1 >> 8) & 7);
       ram[addr + 0x300] &= ~bit;
       ram[addr + 0x301] &= ~bit;
-      if(Color & 1) { ram[addr + 0x300] |= bit; }
-      if(Color & 2) { ram[addr + 0x301] |= bit; }
+      if(Color & 1) ram[addr + 0x300] |= bit;
+      if(Color & 2) ram[addr + 0x301] |= bit;
     }
     X1 += X2;
     Y1 += Y2;
@@ -148,30 +151,31 @@ void Cx4::C4DrawLine(int32 X1, int32 Y1, int16 Z1, int32 X2, int32 Y2, int16 Z2,
 }
 
 void Cx4::C4DoScaleRotate(int row_padding) {
-int16 A, B, C, D;
+  int16 A, B, C, D;
+
+  //Calculate matrix
+  int32 XScale = readw(0x1f8f);
+  int32 YScale = readw(0x1f92);
 
-//Calculate matrix
-int32 XScale = readw(0x1f8f);
-int32 YScale = readw(0x1f92);
   if(XScale & 0x8000)XScale = 0x7fff;
   if(YScale & 0x8000)YScale = 0x7fff;
 
-  if(readw(0x1f80) == 0) { //no rotation
+  if(readw(0x1f80) == 0) {  //no rotation
     A = (int16)XScale;
     B = 0;
     C = 0;
     D = (int16)YScale;
-  } else if(readw(0x1f80) == 128) { //90 degree rotation
+  } else if(readw(0x1f80) == 128) {  //90 degree rotation
     A = 0;
     B = (int16)(-YScale);
     C = (int16)XScale;
     D = 0;
-  } else if(readw(0x1f80) == 256) { //180 degree rotation
+  } else if(readw(0x1f80) == 256) {  //180 degree rotation
     A = (int16)(-XScale);
     B = 0;
     C = 0;
     D = (int16)(-YScale);
-  } else if(readw(0x1f80) == 384) { //270 degree rotation
+  } else if(readw(0x1f80) == 384) {  //270 degree rotation
     A = 0;
     B = (int16)YScale;
     C = (int16)(-XScale);
@@ -183,28 +187,29 @@ int32 YScale = readw(0x1f92);
     D = (int16)  sar(CosTable[readw(0x1f80) & 0x1ff] * YScale, 15);
   }
 
-//Calculate Pixel Resolution
-uint8 w = read(0x1f89) & ~7;
-uint8 h = read(0x1f8c) & ~7;
+  //Calculate Pixel Resolution
+  uint8 w = read(0x1f89) & ~7;
+  uint8 h = read(0x1f8c) & ~7;
 
-//Clear the output RAM
+  //Clear the output RAM
   memset(ram, 0, (w + row_padding / 4) * h / 2);
 
-int32 Cx = (int16)readw(0x1f83);
-int32 Cy = (int16)readw(0x1f86);
+  int32 Cx = (int16)readw(0x1f83);
+  int32 Cy = (int16)readw(0x1f86);
 
-//Calculate start position (i.e. (Ox, Oy) = (0, 0))
-//The low 12 bits are fractional, so (Cx<<12) gives us the Cx we want in
-//the function. We do Cx*A etc normally because the matrix parameters
-//already have the fractional parts.
-int32 LineX = (Cx << 12) - Cx * A - Cx * B;
-int32 LineY = (Cy << 12) - Cy * C - Cy * D;
+  //Calculate start position (i.e. (Ox, Oy) = (0, 0))
+  //The low 12 bits are fractional, so (Cx<<12) gives us the Cx we want in
+  //the function. We do Cx*A etc normally because the matrix parameters
+  //already have the fractional parts.
+  int32 LineX = (Cx << 12) - Cx * A - Cx * B;
+  int32 LineY = (Cy << 12) - Cy * C - Cy * D;
+
+  //Start loop
+  uint32 X, Y;
+  uint8 byte;
+  int32 outidx = 0;
+  uint8 bit    = 0x80;
 
-//Start loop
-uint32 X, Y;
-uint8 byte;
-int32 outidx = 0;
-uint8 bit    = 0x80;
   for(int32 y = 0; y < h; y++) {
     X = LineX;
     Y = LineY;
@@ -212,16 +217,16 @@ uint8 bit    = 0x80;
       if((X >> 12) >= w || (Y >> 12) >= h) {
         byte = 0;
       } else {
-      uint32 addr = (Y >> 12) * w + (X >> 12);
+        uint32 addr = (Y >> 12) * w + (X >> 12);
         byte = read(0x600 + (addr >> 1));
         if(addr & 1) { byte >>= 4; }
       }
 
-    //De-bitplanify
-      if(byte & 1) { ram[outidx     ] |= bit; }
-      if(byte & 2) { ram[outidx +  1] |= bit; }
-      if(byte & 4) { ram[outidx + 16] |= bit; }
-      if(byte & 8) { ram[outidx + 17] |= bit; }
+      //De-bitplanify
+      if(byte & 1) ram[outidx     ] |= bit;
+      if(byte & 2) ram[outidx +  1] |= bit;
+      if(byte & 4) ram[outidx + 16] |= bit;
+      if(byte & 8) ram[outidx + 17] |= bit;
 
       bit >>= 1;
       if(!bit) {
@@ -229,7 +234,7 @@ uint8 bit    = 0x80;
         outidx += 32;
       }
 
-      X += A; //Add 1 to output x => add an A and a C
+      X += A;  //Add 1 to output x => add an A and a C
       Y += C;
     }
     outidx += 2 + row_padding;
@@ -238,9 +243,9 @@ uint8 bit    = 0x80;
     } else {
       outidx -= w * 4 + row_padding;
     }
-    LineX += B; //Add 1 to output y => add a B and a D
+    LineX += B;  //Add 1 to output y => add a B and a D
     LineY += D;
   }
 }
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/oam.cpp

@@ -2,35 +2,37 @@
 
 //Build OAM
 void Cx4::op00_00() {
-uint32 oamptr = ram[0x626] << 2;
+  uint32 oamptr = ram[0x626] << 2;
   for(int32 i = 0x1fd; i > oamptr && i >= 0; i -= 4) {
-  //clear oam-to-be
-    if(i >= 0)ram[i] = 0xe0;
+    //clear oam-to-be
+    if(i >= 0) ram[i] = 0xe0;
   }
 
-uint16 globalx, globaly;
-uint32 oamptr2;
-int16  sprx, spry;
-uint8  sprname, sprattr;
-uint8  sprcount;
+  uint16 globalx, globaly;
+  uint32 oamptr2;
+  int16  sprx, spry;
+  uint8  sprname, sprattr;
+  uint8  sprcount;
+
   globalx = readw(0x621);
   globaly = readw(0x623);
   oamptr2 = 0x200 + (ram[0x626] >> 2);
 
-  if(!ram[0x620])return;
+  if(!ram[0x620]) return;
 
   sprcount = 128 - ram[0x626];
-uint8 offset = (ram[0x626] & 3) * 2;
-uint32 srcptr = 0x220;
+  uint8 offset = (ram[0x626] & 3) * 2;
+  uint32 srcptr = 0x220;
+
   for(int i = ram[0x620]; i > 0 && sprcount > 0; i--, srcptr += 16) {
     sprx = readw(srcptr)     - globalx;
     spry = readw(srcptr + 2) - globaly;
     sprname = ram[srcptr + 5];
     sprattr = ram[srcptr + 4] | ram[srcptr + 6];
 
-  uint32 spraddr = readl(srcptr + 7);
+    uint32 spraddr = readl(srcptr + 7);
     if(bus.read(spraddr)) {
-    int16 x, y;
+      int16 x, y;
       for(int sprcnt = bus.read(spraddr++); sprcnt > 0 && sprcount > 0; sprcnt--, spraddr += 4) {
         x = (int8)bus.read(spraddr + 1);
         if(sprattr & 0x40) {
@@ -49,8 +51,8 @@ uint32 srcptr = 0x220;
             ram[oamptr + 2] = sprname + bus.read(spraddr + 3);
             ram[oamptr + 3] = sprattr ^ (bus.read(spraddr) & 0xc0);
             ram[oamptr2] &= ~(3 << offset);
-            if(x & 0x100)ram[oamptr2] |= 1 << offset;
-            if(bus.read(spraddr) & 0x20)ram[oamptr2] |= 2 << offset;
+            if(x & 0x100) ram[oamptr2] |= 1 << offset;
+            if(bus.read(spraddr) & 0x20) ram[oamptr2] |= 2 << offset;
             oamptr += 4;
             sprcount--;
             offset = (offset + 2) & 6;
@@ -64,12 +66,12 @@ uint32 srcptr = 0x220;
       ram[oamptr + 2] = sprname;
       ram[oamptr + 3] = sprattr;
       ram[oamptr2] &= ~(3 << offset);
-      if(sprx & 0x100)ram[oamptr2] |= 3 << offset;
+      if(sprx & 0x100) ram[oamptr2] |= 3 << offset;
       else ram[oamptr2] |= 2 << offset;
       oamptr += 4;
       sprcount--;
       offset = (offset + 2) & 6;
-      if(!offset)oamptr2++;
+      if(!offset) oamptr2++;
     }
   }
 }
@@ -94,7 +96,7 @@ uint32 ptr = 0;
     C4WFZVal = readw(ptr + 9);
     C4TransfWireFrame();
 
-  //Displace
+    //Displace
     writew(ptr + 1, C4WFXVal + 0x80);
     writew(ptr + 5, C4WFYVal + 0x50);
   }
@@ -107,7 +109,8 @@ uint32 ptr = 0;
   writew(0x605 + 8, 0x40);
 
   ptr = 0xb02;
-uint32 ptr2 = 0;
+  uint32 ptr2 = 0;
+
   for(int32 i = readw(0xb00); i > 0; i--, ptr += 2, ptr2 += 8) {
     C4WFXVal  = readw((read(ptr + 0) << 4) + 1);
     C4WFYVal  = readw((read(ptr + 0) << 4) + 5);
@@ -132,13 +135,14 @@ void Cx4::op00_08() {
 
 //Disintegrate
 void Cx4::op00_0b() {
-uint8  width, height;
-uint32 startx, starty;
-uint32 srcptr;
-uint32 x, y;
-int32  scalex, scaley;
-int32  cx, cy;
-int32  i, j;
+  uint8  width, height;
+  uint32 startx, starty;
+  uint32 srcptr;
+  uint32 x, y;
+  int32  scalex, scaley;
+  int32  cx, cy;
+  int32  i, j;
+
   width  = read(0x1f89);
   height = read(0x1f8c);
   cx     = readw(0x1f80);
@@ -157,31 +161,32 @@ int32  i, j;
   for(y = starty, i = 0;i < height; i++, y += scaley) {
     for(x = startx, j = 0;j < width; j++, x += scalex) {
       if((x >> 8) < width && (y >> 8) < height && (y >> 8) * width + (x >> 8) < 0x2000) {
-      uint8 pixel = (j & 1) ? (ram[srcptr] >> 4) : (ram[srcptr]);
-      int32 index = (y >> 11) * width * 4 + (x >> 11) * 32 + ((y >> 8) & 7) * 2;
-      uint8 mask = 0x80 >> ((x >> 8) & 7);
-        if(pixel & 1)ram[index     ] |= mask;
-        if(pixel & 2)ram[index +  1] |= mask;
-        if(pixel & 4)ram[index + 16] |= mask;
-        if(pixel & 8)ram[index + 17] |= mask;
+        uint8 pixel = (j & 1) ? (ram[srcptr] >> 4) : (ram[srcptr]);
+        int32 index = (y >> 11) * width * 4 + (x >> 11) * 32 + ((y >> 8) & 7) * 2;
+        uint8 mask = 0x80 >> ((x >> 8) & 7);
+
+        if(pixel & 1) ram[index     ] |= mask;
+        if(pixel & 2) ram[index +  1] |= mask;
+        if(pixel & 4) ram[index + 16] |= mask;
+        if(pixel & 8) ram[index + 17] |= mask;
       }
-      if(j & 1)srcptr++;
+      if(j & 1) srcptr++;
     }
   }
 }
 
 //Bitplane Wave
 void Cx4::op00_0c() {
-uint32 destptr = 0;
-uint32 waveptr = read(0x1f83);
-uint16 mask1   = 0xc0c0;
-uint16 mask2   = 0x3f3f;
+  uint32 destptr = 0;
+  uint32 waveptr = read(0x1f83);
+  uint16 mask1   = 0xc0c0;
+  uint16 mask2   = 0x3f3f;
 
   for(int j = 0; j < 0x10; j++) {
     do {
-    int16 height = -((int8)read(waveptr + 0xb00)) - 16;
+      int16 height = -((int8)read(waveptr + 0xb00)) - 16;
       for(int i = 0; i < 40; i++) {
-      uint16 temp = readw(destptr + wave_data[i]) & mask2;
+        uint16 temp = readw(destptr + wave_data[i]) & mask2;
         if(height >= 0) {
           if(height < 8) {
             temp |= mask1 & readw(0xa00 + height * 2);
@@ -199,9 +204,9 @@ uint16 mask2   = 0x3f3f;
     destptr += 16;
 
     do {
-    int16 height = -((int8)read(waveptr + 0xb00)) - 16;
+      int16 height = -((int8)read(waveptr + 0xb00)) - 16;
       for(int i = 0; i < 40; i++) {
-      uint16 temp = readw(destptr + wave_data[i]) & mask2;
+        uint16 temp = readw(destptr + wave_data[i]) & mask2;
         if(height >= 0) {
           if(height < 8) {
             temp |= mask1 & readw(0xa10 + height * 2);
@@ -220,4 +225,4 @@ uint16 mask2   = 0x3f3f;
   }
 }
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/opcodes.cpp

@@ -3,13 +3,13 @@
 //Sprite Functions
 void Cx4::op00() {
   switch(reg[0x4d]) {
-  case 0x00:op00_00();break;
-  case 0x03:op00_03();break;
-  case 0x05:op00_05();break;
-  case 0x07:op00_07();break;
-  case 0x08:op00_08();break;
-  case 0x0b:op00_0b();break;
-  case 0x0c:op00_0c();break;
+    case 0x00: op00_00(); break;
+    case 0x03: op00_03(); break;
+    case 0x05: op00_05(); break;
+    case 0x07: op00_07(); break;
+    case 0x08: op00_08(); break;
+    case 0x0b: op00_0b(); break;
+    case 0x0c: op00_0c(); break;
   }
 }
 
@@ -21,7 +21,7 @@ void Cx4::op01() {
 
 //Propulsion
 void Cx4::op05() {
-int32 temp = 0x10000;
+  int32 temp = 0x10000;
   if(readw(0x1f83)) {
     temp = sar((temp / readw(0x1f83)) * readw(0x1f81), 8);
   }
@@ -33,7 +33,7 @@ void Cx4::op0d() {
   C41FXVal    = readw(0x1f80);
   C41FYVal    = readw(0x1f83);
   C41FDistVal = readw(0x1f86);
-  tanval = sqrt(((double)C41FYVal) * ((double)C41FYVal) + ((double)C41FXVal) * ((double)C41FXVal));
+  double tanval = sqrt(((double)C41FYVal) * ((double)C41FYVal) + ((double)C41FXVal) * ((double)C41FXVal));
   tanval = (double)C41FDistVal / tanval;
   C41FYVal = (int16)(((double)C41FYVal * tanval) * 0.99);
   C41FXVal = (int16)(((double)C41FXVal * tanval) * 0.98);
@@ -103,7 +103,7 @@ void Cx4::op1f() {
   if(!C41FXVal) {
     C41FAngleRes = (C41FYVal > 0) ? 0x080 : 0x180;
   } else {
-    tanval = ((double)C41FYVal) / ((double)C41FXVal);
+    double tanval = ((double)C41FYVal) / ((double)C41FXVal);
     C41FAngleRes = (short)(atan(tanval) / (PI * 2) * 512);
     C41FAngleRes = C41FAngleRes;
     if(C41FXVal < 0) {
@@ -116,12 +116,13 @@ void Cx4::op1f() {
 
 //Trapezoid
 void Cx4::op22() {
-int16 angle1 = readw(0x1f8c) & 0x1ff;
-int16 angle2 = readw(0x1f8f) & 0x1ff;
-int32 tan1 = Tan(angle1);
-int32 tan2 = Tan(angle2);
-int16 y = readw(0x1f83) - readw(0x1f89);
-int16 left, right;
+  int16 angle1 = readw(0x1f8c) & 0x1ff;
+  int16 angle2 = readw(0x1f8f) & 0x1ff;
+  int32 tan1 = Tan(angle1);
+  int32 tan2 = Tan(angle2);
+  int16 y = readw(0x1f83) - readw(0x1f89);
+  int16 left, right;
+
   for(int32 j = 0; j < 225; j++, y++) {
     if(y >= 0) {
       left  = sar((int32)tan1 * y, 16) - readw(0x1f80) + readw(0x1f86);
@@ -223,4 +224,4 @@ void Cx4::op89() {
   str(1, 0xffffff);
 }
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/serialization.cpp

@@ -0,0 +1,39 @@
+#ifdef CX4_CPP
+
+void Cx4::serialize(serializer &s) {
+  s.array(ram);
+  s.array(reg);
+
+  s.integer(r0);
+  s.integer(r1);
+  s.integer(r2);
+  s.integer(r3);
+  s.integer(r4);
+  s.integer(r5);
+  s.integer(r6);
+  s.integer(r7);
+  s.integer(r8);
+  s.integer(r9);
+  s.integer(r10);
+  s.integer(r11);
+  s.integer(r12);
+  s.integer(r13);
+  s.integer(r14);
+  s.integer(r15);
+
+  s.integer(C4WFXVal);
+  s.integer(C4WFYVal);
+  s.integer(C4WFZVal);
+  s.integer(C4WFX2Val);
+  s.integer(C4WFY2Val);
+  s.integer(C4WFDist);
+  s.integer(C4WFScale);
+
+  s.integer(C41FXVal);
+  s.integer(C41FYVal);
+  s.integer(C41FAngleRes);
+  s.integer(C41FDist);
+  s.integer(C41FDistVal);
+}
+
+#endif

src/chip/dsp1/dsp1.cpp

@@ -1,10 +1,34 @@
-#include "../../base.h"
-#define DSP1_CPP
+#include <../base.hpp>
 
+#define DSP1_CPP
+namespace SNES {
+
+DSP1 dsp1;
+
+#include "serialization.cpp"
 #include "dsp1emu.cpp"
 
-void DSP1::init() {}
-void DSP1::enable() {}
+void DSP1::init() {
+}
+
+void DSP1::enable() {
+  switch(cartridge.dsp1_mapper()) {
+    case Cartridge::DSP1LoROM1MB: {
+      bus.map(Bus::MapDirect, 0x20, 0x3f, 0x8000, 0xffff, *this);
+      bus.map(Bus::MapDirect, 0xa0, 0xbf, 0x8000, 0xffff, *this);
+    } break;
+
+    case Cartridge::DSP1LoROM2MB: {
+      bus.map(Bus::MapDirect, 0x60, 0x6f, 0x0000, 0x7fff, *this);
+      bus.map(Bus::MapDirect, 0xe0, 0xef, 0x0000, 0x7fff, *this);
+    } break;
+
+    case Cartridge::DSP1HiROM: {
+      bus.map(Bus::MapDirect, 0x00, 0x1f, 0x6000, 0x7fff, *this);
+      bus.map(Bus::MapDirect, 0x80, 0x9f, 0x6000, 0x7fff, *this);
+    } break;
+  }
+}
 
 void DSP1::power() {
   reset();
@@ -26,7 +50,7 @@ void DSP1::reset() {
  * of expected ranges
  *****/
 bool DSP1::addr_decode(uint16 addr) {
-  switch(cartridge.info.dsp1_mapper) {
+  switch(cartridge.dsp1_mapper()) {
     case Cartridge::DSP1LoROM1MB: {
     //$[20-3f]:[8000-bfff] = DR, $[20-3f]:[c000-ffff] = SR
       return (addr >= 0xc000);
@@ -46,12 +70,14 @@ bool DSP1::addr_decode(uint16 addr) {
   return 0;
 }
 
-uint8 DSP1::read(uint addr) {
+uint8 DSP1::read(unsigned addr) {
   return (addr_decode(addr) == 0) ? dsp1.getDr() : dsp1.getSr();
 }
 
-void DSP1::write(uint addr, uint8 data) {
+void DSP1::write(unsigned addr, uint8 data) {
   if(addr_decode(addr) == 0) {
     dsp1.setDr(data);
   }
 }
+
+};

src/chip/dsp1/dsp1.hpp

@@ -1,18 +1,20 @@
-#include "dsp1emu.h"
+#include "dsp1emu.hpp"
 
 class DSP1 : public Memory {
-private:
-  Dsp1 dsp1;
-  bool addr_decode(uint16 addr);
-
 public:
   void init();
   void enable();
   void power();
   void reset();
 
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
+
+  void serialize(serializer&);
+
+private:
+  Dsp1 dsp1;
+  bool addr_decode(uint16 addr);
 };
 
 extern DSP1 dsp1;

src/chip/dsp1/dsp1emu.cpp

@@ -1622,4 +1622,4 @@ const int16 Dsp1::SinTable[256] = {
 
 //////////////////////////////////////////////////////////////////
 
-#endif //ifdef DSP1_CPP
+#endif

src/chip/dsp1/dsp1emu.hpp

@@ -33,6 +33,8 @@ class Dsp1
       void setDr(uint8 iDr);
       void reset();
 
+      void serialize(serializer&);
+
    private:
       enum FsmMajorState {WAIT_COMMAND, READ_DATA, WRITE_DATA};
       enum MaxDataAccesses {MAX_READS=7, MAX_WRITES=1024};
@@ -72,7 +74,7 @@ class Dsp1
       uint8 mSr;            // status register
       int mSrLowByteAccess;
       uint16 mDr;           // "internal" representation of the data register
-      FsmMajorState mFsmMajorState;     // current major state of the FSM
+      unsigned mFsmMajorState;     // current major state of the FSM
       uint8 mCommand;                  // current command processed by the FSM
       uint8 mDataCounter;                 // #uint16 read/writes counter used by the FSM
       int16 mReadBuffer[MAX_READS];

src/chip/dsp1/serialization.cpp

@@ -0,0 +1,56 @@
+#ifdef DSP1_CPP
+
+void DSP1::serialize(serializer &s) {
+  dsp1.serialize(s);
+}
+
+void Dsp1::serialize(serializer &s) {
+  for(unsigned i = 0; i < 3; i++) {
+    s.array(shared.MatrixA[i]);
+    s.array(shared.MatrixB[i]);
+    s.array(shared.MatrixC[i]);
+  }
+
+  s.integer(shared.CentreX);
+  s.integer(shared.CentreY);
+  s.integer(shared.CentreZ);
+  s.integer(shared.CentreZ_C);
+  s.integer(shared.CentreZ_E);
+  s.integer(shared.VOffset);
+  s.integer(shared.Les);
+  s.integer(shared.C_Les);
+  s.integer(shared.E_Les);
+  s.integer(shared.SinAas);
+  s.integer(shared.CosAas);
+  s.integer(shared.SinAzs);
+  s.integer(shared.CosAzs);
+  s.integer(shared.SinAZS);
+  s.integer(shared.CosAZS);
+  s.integer(shared.SecAZS_C1);
+  s.integer(shared.SecAZS_E1);
+  s.integer(shared.SecAZS_C2);
+  s.integer(shared.SecAZS_E2);
+  s.integer(shared.Nx);
+  s.integer(shared.Ny);
+  s.integer(shared.Nz);
+  s.integer(shared.Gx);
+  s.integer(shared.Gy);
+  s.integer(shared.Gz);
+  s.integer(shared.Hx);
+  s.integer(shared.Hy);
+  s.integer(shared.Vx);
+  s.integer(shared.Vy);
+  s.integer(shared.Vz);
+
+  s.integer(mSr);
+  s.integer(mSrLowByteAccess);
+  s.integer(mDr);
+  s.integer(mFsmMajorState);
+  s.integer(mCommand);
+  s.integer(mDataCounter);
+  s.array(mReadBuffer);
+  s.array(mWriteBuffer);
+  s.integer(mFreeze);
+}
+
+#endif

src/chip/dsp2/dsp2.cpp

@@ -1,10 +1,22 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define DSP2_CPP
+namespace SNES {
 
-#include "dsp2_op.cpp"
+DSP2 dsp2;
 
-void DSP2::init() {}
-void DSP2::enable() {}
+#include "serialization.cpp"
+#include "opcodes.cpp"
+
+void DSP2::init() {
+}
+
+void DSP2::enable() {
+  bus.map(Bus::MapDirect, 0x20, 0x3f, 0x6000, 0x6fff, *this);
+  bus.map(Bus::MapDirect, 0x20, 0x3f, 0x8000, 0xbfff, *this);
+  bus.map(Bus::MapDirect, 0xa0, 0xbf, 0x6000, 0x6fff, *this);
+  bus.map(Bus::MapDirect, 0xa0, 0xbf, 0x8000, 0xbfff, *this);
+}
 
 void DSP2::power() {
   reset();
@@ -29,8 +41,8 @@ void DSP2::reset() {
   status.op0dinlen       = 0;
 }
 
-uint8 DSP2::read(uint addr) {
-uint8 r = 0xff;
+uint8 DSP2::read(unsigned addr) {
+  uint8 r = 0xff;
   if(status.out_count) {
     r = status.output[status.out_index++];
     status.out_index &= 511;
@@ -41,7 +53,7 @@ uint8 r = 0xff;
   return r;
 }
 
-void DSP2::write(uint addr, uint8 data) {
+void DSP2::write(unsigned addr, uint8 data) {
   if(status.waiting_for_command) {
     status.command  = data;
     status.in_index = 0;
@@ -133,3 +145,5 @@ void DSP2::write(uint addr, uint8 data) {
 
 DSP2::DSP2() {}
 DSP2::~DSP2() {}
+};
+

src/chip/dsp2/dsp2.hpp

@@ -1,10 +1,10 @@
 class DSP2 : public Memory {
 public:
   struct {
-    bool   waiting_for_command;
-    uint   command;
-    uint   in_count,  in_index;
-    uint   out_count, out_index;
+    bool waiting_for_command;
+    unsigned command;
+    unsigned in_count,  in_index;
+    unsigned out_count, out_index;
 
     uint8  parameters[512];
     uint8  output[512];
@@ -26,9 +26,10 @@ public:
   void power();
   void reset();
 
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 
+  void serialize(serializer&);
   DSP2();
   ~DSP2();
 

src/chip/dsp2/opcodes.cpp

@@ -174,4 +174,4 @@ uint8  pixelarray[512];
   }
 }
 
-#endif //ifdef DSP2_CPP
+#endif

src/chip/dsp2/serialization.cpp

@@ -0,0 +1,26 @@
+#ifdef DSP2_CPP
+
+void DSP2::serialize(serializer &s) {
+  s.integer(status.waiting_for_command);
+  s.integer(status.command);
+  s.integer(status.in_count);
+  s.integer(status.in_index);
+  s.integer(status.out_count);
+  s.integer(status.out_index);
+
+  s.array(status.parameters);
+  s.array(status.output);
+
+  s.integer(status.op05transparent);
+  s.integer(status.op05haslen);
+  s.integer(status.op05len);
+  s.integer(status.op06haslen);
+  s.integer(status.op06len);
+  s.integer(status.op09word1);
+  s.integer(status.op09word2);
+  s.integer(status.op0dhaslen);
+  s.integer(status.op0doutlen);
+  s.integer(status.op0dinlen);
+}
+
+#endif

src/chip/dsp3/dsp3.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define DSP3_CPP
+namespace SNES {
+
+DSP3 dsp3;
 
 namespace DSP3i {
   #define bool8 uint8
@@ -11,6 +15,8 @@ void DSP3::init() {
 }
 
 void DSP3::enable() {
+  bus.map(Bus::MapDirect, 0x20, 0x3f, 0x8000, 0xffff, *this);
+  bus.map(Bus::MapDirect, 0xa0, 0xbf, 0x8000, 0xffff, *this);
 }
 
 void DSP3::power() {
@@ -21,14 +27,16 @@ void DSP3::reset() {
   DSP3i::DSP3_Reset();
 }
 
-uint8 DSP3::read(uint addr) {
+uint8 DSP3::read(unsigned addr) {
   DSP3i::dsp3_address = addr & 0xffff;
   DSP3i::DSP3GetByte();
   return DSP3i::dsp3_byte;
 }
 
-void DSP3::write(uint addr, uint8 data) {
+void DSP3::write(unsigned addr, uint8 data) {
   DSP3i::dsp3_address = addr & 0xffff;
   DSP3i::dsp3_byte = data;
   DSP3i::DSP3SetByte();
 }
+
+};

src/chip/dsp3/dsp3.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
 };
 
 extern DSP3 dsp3;

src/chip/dsp3/dsp3emu.c

@@ -1143,4 +1143,4 @@ void InitDSP3()
   DSP3_Reset();
 }
 
-#endif //ifdef DSP3_CPP
+#endif

src/chip/dsp4/dsp4.cpp

@@ -1,5 +1,17 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define DSP4_CPP
+namespace SNES {
+
+DSP4 dsp4;
+
+void DSP4::init() {
+}
+
+void DSP4::enable() {
+  bus.map(Bus::MapDirect, 0x30, 0x3f, 0x8000, 0xffff, *this);
+  bus.map(Bus::MapDirect, 0xb0, 0xbf, 0x8000, 0xffff, *this);
+}
 
 namespace DSP4i {
   inline uint16 READ_WORD(uint8 *addr) {
@@ -20,12 +32,6 @@ namespace DSP4i {
   #undef bool8
 };
 
-void DSP4::init() {
-}
-
-void DSP4::enable() {
-}
-
 void DSP4::power() {
   reset();
 }
@@ -34,7 +40,7 @@ void DSP4::reset() {
   DSP4i::InitDSP4();
 }
 
-uint8 DSP4::read(uint addr) {
+uint8 DSP4::read(unsigned addr) {
   addr &= 0xffff;
   if(addr < 0xc000) {
     DSP4i::dsp4_address = addr;
@@ -44,7 +50,7 @@ uint8 DSP4::read(uint addr) {
   return 0x80;
 }
 
-void DSP4::write(uint addr, uint8 data) {
+void DSP4::write(unsigned addr, uint8 data) {
   addr &= 0xffff;
   if(addr < 0xc000) {
     DSP4i::dsp4_address = addr;
@@ -52,3 +58,5 @@ void DSP4::write(uint addr, uint8 data) {
     DSP4i::DSP4SetByte();
   }
 }
+
+};

src/chip/dsp4/dsp4.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
 };
 
 extern DSP4 dsp4;

src/chip/dsp4/dsp4emu.c

@@ -2062,9 +2062,9 @@ void DSP4SetByte()
       // unknown
       case 0x000A:
       {
-        //int16 in1a = DSP4_READ_WORD();
+        int16 in1a = DSP4_READ_WORD();
         int16 in2a = DSP4_READ_WORD();
-        //int16 in3a = DSP4_READ_WORD();
+        int16 in3a = DSP4_READ_WORD();
         int16 out1a, out2a, out3a, out4a;
 
         DSP4_OP0A(in2a, &out2a, &out1a, &out4a, &out3a);
@@ -2147,4 +2147,4 @@ void DSP4GetByte()
   }
 }
 
-#endif //ifdef DSP4_CPP
+#endif

src/chip/obc1/obc1.cpp

@@ -1,89 +1,84 @@
-#include "../../base.h"
+#include <../base.hpp>
 
-void OBC1::init() {}
-void OBC1::enable() {}
+#define OBC1_CPP
+namespace SNES {
+
+OBC1 obc1;
+
+#include "serialization.cpp"
+
+void OBC1::init() {
+}
+
+void OBC1::enable() {
+  bus.map(Bus::MapDirect, 0x00, 0x3f, 0x6000, 0x7fff, *this);
+  bus.map(Bus::MapDirect, 0x80, 0xbf, 0x6000, 0x7fff, *this);
+}
 
 void OBC1::power() {
   reset();
 }
 
 void OBC1::reset() {
-  for(uint i = 0x0000; i <= 0x1fff; i++) ram_write(i, 0xff);
+  for(unsigned i = 0x0000; i <= 0x1fff; i++) ram_write(i, 0xff);
 
   status.baseptr = (ram_read(0x1ff5) & 1) ? 0x1800 : 0x1c00;
   status.address = (ram_read(0x1ff6) & 0x7f);
   status.shift   = (ram_read(0x1ff6) & 3) << 1;
 }
 
-uint8 OBC1::read(uint addr) {
+uint8 OBC1::read(unsigned addr) {
   addr &= 0x1fff;
   if((addr & 0x1ff8) != 0x1ff0) return ram_read(addr);
 
-  switch(addr) {
-  case 0x1ff0:
-    return ram_read(status.baseptr + (status.address << 2) + 0);
-  case 0x1ff1:
-    return ram_read(status.baseptr + (status.address << 2) + 1);
-  case 0x1ff2:
-    return ram_read(status.baseptr + (status.address << 2) + 2);
-  case 0x1ff3:
-    return ram_read(status.baseptr + (status.address << 2) + 3);
-  case 0x1ff4:
-    return ram_read(status.baseptr + (status.address >> 2) + 0x200);
-  case 0x1ff5:
-  case 0x1ff6:
-  case 0x1ff7:
-    return ram_read(addr);
+  switch(addr) { default:  //never used, avoids compiler warning
+    case 0x1ff0: return ram_read(status.baseptr + (status.address << 2) + 0);
+    case 0x1ff1: return ram_read(status.baseptr + (status.address << 2) + 1);
+    case 0x1ff2: return ram_read(status.baseptr + (status.address << 2) + 2);
+    case 0x1ff3: return ram_read(status.baseptr + (status.address << 2) + 3);
+    case 0x1ff4: return ram_read(status.baseptr + (status.address >> 2) + 0x200);
+    case 0x1ff5: case 0x1ff6: case 0x1ff7: return ram_read(addr);
   }
-
-  return 0x00; //never used, avoids compiler warning
 }
 
-void OBC1::write(uint addr, uint8 data) {
+void OBC1::write(unsigned addr, uint8 data) {
   addr &= 0x1fff;
   if((addr & 0x1ff8) != 0x1ff0) return ram_write(addr, data);
 
   switch(addr) {
-  case 0x1ff0:
-    ram_write(status.baseptr + (status.address << 2) + 0, data);
-    break;
-  case 0x1ff1:
-    ram_write(status.baseptr + (status.address << 2) + 1, data);
-    break;
-  case 0x1ff2:
-    ram_write(status.baseptr + (status.address << 2) + 2, data);
-    break;
-  case 0x1ff3:
-    ram_write(status.baseptr + (status.address << 2) + 3, data);
-    break;
-  case 0x1ff4: {
-  uint8 temp;
-    temp = ram_read(status.baseptr + (status.address >> 2) + 0x200);
-    temp = (temp & ~(3 << status.shift)) | ((data & 3) << status.shift);
-    ram_write(status.baseptr + (status.address >> 2) + 0x200, temp);
-  } break;
-  case 0x1ff5:
-    status.baseptr = (data & 1) ? 0x1800 : 0x1c00;
-    ram_write(addr, data);
-    break;
-  case 0x1ff6:
-    status.address = (data & 0x7f);
-    status.shift   = (data & 3) << 1;
-    ram_write(addr, data);
-    break;
-  case 0x1ff7:
-    ram_write(addr, data);
-    break;
+    case 0x1ff0: ram_write(status.baseptr + (status.address << 2) + 0, data); break;
+    case 0x1ff1: ram_write(status.baseptr + (status.address << 2) + 1, data); break;
+    case 0x1ff2: ram_write(status.baseptr + (status.address << 2) + 2, data); break;
+    case 0x1ff3: ram_write(status.baseptr + (status.address << 2) + 3, data); break;
+    case 0x1ff4: {
+      uint8 temp = ram_read(status.baseptr + (status.address >> 2) + 0x200);
+      temp = (temp & ~(3 << status.shift)) | ((data & 3) << status.shift);
+      ram_write(status.baseptr + (status.address >> 2) + 0x200, temp);
+    } break;
+    case 0x1ff5: {
+      status.baseptr = (data & 1) ? 0x1800 : 0x1c00;
+      ram_write(addr, data);
+    } break;
+    case 0x1ff6: {
+      status.address = (data & 0x7f);
+      status.shift   = (data & 3) << 1;
+      ram_write(addr, data);
+    } break;
+    case 0x1ff7: {
+      ram_write(addr, data);
+    } break;
   }
 }
 
-uint8 OBC1::ram_read(uint addr) {
+uint8 OBC1::ram_read(unsigned addr) {
   return memory::cartram.read(addr & 0x1fff);
 }
 
-void OBC1::ram_write(uint addr, uint8 data) {
+void OBC1::ram_write(unsigned addr, uint8 data) {
   memory::cartram.write(addr & 0x1fff, data);
 }
 
 OBC1::OBC1() {}
 OBC1::~OBC1() {}
+
+};

src/chip/obc1/obc1.hpp

@@ -5,15 +5,16 @@ public:
   void power();
   void reset();
 
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 
+  void serialize(serializer&);
   OBC1();
   ~OBC1();
 
 private:
-  uint8 ram_read(uint addr);
-  void ram_write(uint addr, uint8 data);
+  uint8 ram_read(unsigned addr);
+  void ram_write(unsigned addr, uint8 data);
 
   struct {
     uint16 address;

src/chip/obc1/serialization.cpp

@@ -0,0 +1,9 @@
+#ifdef OBC1_CPP
+
+void OBC1::serialize(serializer &s) {
+  s.integer(status.address);
+  s.integer(status.baseptr);
+  s.integer(status.shift);
+}
+
+#endif

src/chip/sa1/bus/bus.cpp

@@ -0,0 +1,243 @@
+#ifdef SA1_CPP
+
+VBRBus vbrbus;
+SA1Bus sa1bus;
+
+namespace memory {
+  static StaticRAM iram(2048);
+                                        //accessed by:
+  static VectorSelectionPage vectorsp;  //S-CPU + SA-1
+  static CPUIRAM cpuiram;               //S-CPU
+  static SA1IRAM sa1iram;               //SA-1
+  static SA1BWRAM sa1bwram;             //SA-1
+  static CC1BWRAM cc1bwram;             //S-CPU
+  static BitmapRAM bitmapram;           //SA-1
+}
+
+//$230c (VDPL), $230d (VDPH) use this bus to read variable-length data.
+//this is used both to avoid VBR-reads from accessing MMIO registers, and
+//to avoid syncing the S-CPU and SA-1*; as both chips are able to access
+//these ports.
+//(* eg, memory::cartram is used directly, as memory::sa1bwram syncs to the S-CPU)
+void VBRBus::init() {
+  map(MapDirect, 0x00, 0xff, 0x0000, 0xffff, memory::memory_unmapped);
+
+  map(MapLinear, 0x00, 0x3f, 0x0000, 0x07ff, memory::iram);
+  map(MapLinear, 0x00, 0x3f, 0x3000, 0x37ff, memory::iram);
+  map(MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::cartram);
+  map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::cartrom);
+  map(MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::cartram);
+  map(MapLinear, 0x80, 0xbf, 0x0000, 0x07ff, memory::iram);
+  map(MapLinear, 0x80, 0xbf, 0x3000, 0x37ff, memory::iram);
+  map(MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::cartram);
+  map(MapLinear, 0x80, 0xbf, 0x8000, 0xffff, memory::cartrom);
+  map(MapLinear, 0xc0, 0xff, 0x0000, 0xffff, memory::cartrom);
+}
+
+void SA1Bus::init() {
+  map(MapDirect, 0x00, 0xff, 0x0000, 0xffff, memory::memory_unmapped);
+  for(unsigned i = 0x2200; i <= 0x23ff; i++) memory::mmio.map(i, sa1);
+
+  map(MapLinear, 0x00, 0x3f, 0x0000, 0x07ff, memory::sa1iram);
+  map(MapDirect, 0x00, 0x3f, 0x2200, 0x23ff, memory::mmio);
+  map(MapLinear, 0x00, 0x3f, 0x3000, 0x37ff, memory::sa1iram);
+  map(MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::sa1bwram);
+  map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::cartrom);
+  map(MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::sa1bwram);
+  map(MapLinear, 0x60, 0x6f, 0x0000, 0xffff, memory::bitmapram);
+  map(MapLinear, 0x80, 0xbf, 0x0000, 0x07ff, memory::sa1iram);
+  map(MapDirect, 0x80, 0xbf, 0x2200, 0x23ff, memory::mmio);
+  map(MapLinear, 0x80, 0xbf, 0x3000, 0x37ff, memory::sa1iram);
+  map(MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::sa1bwram);
+  map(MapLinear, 0x80, 0xbf, 0x8000, 0xffff, memory::cartrom);
+  map(MapLinear, 0xc0, 0xff, 0x0000, 0xffff, memory::cartrom);
+
+  bus.map(MapLinear, 0x00, 0x3f, 0x3000, 0x37ff, memory::cpuiram);
+  bus.map(MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::cc1bwram);
+  bus.map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::cartrom);
+  bus.map(MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::cc1bwram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x3000, 0x37ff, memory::cpuiram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::cc1bwram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x8000, 0xffff, memory::cartrom);
+  bus.map(MapLinear, 0xc0, 0xff, 0x0000, 0xffff, memory::cartrom);
+
+  memory::vectorsp.sync();
+}
+
+//===================
+//VectorSelectionPage
+//===================
+
+//this class maps $00:[ff00-ffff] for the purpose of supporting:
+//$2209.d6 IVSW (S-CPU IRQ vector selection) (0 = cart, 1 = SA-1)
+//$2209.d4 NVSW (S-CPU NMI vector selection) (0 = cart, 1 = SA-1)
+//when set, vector addresses are over-ridden with SA-1 register settings:
+//SIV = S-CPU IRQ vector address override
+//SNV = S-CPU NMI vector address override
+//
+//$00:[ffea-ffeb|ffee-ffef] are special cased on read;
+//all other addresses return original mapped data.
+
+uint8 VectorSelectionPage::read(unsigned addr) {
+  switch(0xff00 | (addr & 0xff)) {
+    case 0xffea: case 0xffeb: {
+      if(sa1.mmio.cpu_nvsw == true) return (sa1.mmio.snv >> ((addr & 1) << 3));
+    } break;
+
+    case 0xffee: case 0xffef: {
+      if(sa1.mmio.cpu_ivsw == true) return (sa1.mmio.siv >> ((addr & 1) << 3));
+    } break;
+  }
+
+  return access->read(addr);
+}
+
+void VectorSelectionPage::write(unsigned addr, uint8 data) {
+  return access->write(addr, data);
+}
+
+//call this whenever bus is remapped.
+//note: S-CPU and SA-1 bus always share $00:[ff00-ffff] as cartridge ROM data;
+//the SA-1 MMC does not allow mapping these independently between processors.
+//this allows this class to be shared for both, caching only ones' access class.
+void VectorSelectionPage::sync() {
+  if(bus.page[0x00ff00 >> 8].access != this) {
+    //bus was re-mapped, hook access routine
+    access = bus.page[0x00ff00 >> 8].access;
+       bus.page[0x00ff00 >> 8].access = this;
+    sa1bus.page[0x00ff00 >> 8].access = this;
+  }
+}
+
+//=======
+//SA1IRAM
+//=======
+
+unsigned SA1IRAM::size() const {
+  return memory::iram.size();
+}
+
+uint8 SA1IRAM::read(unsigned addr) {
+  scheduler.sync_copcpu();
+  return memory::iram.read(addr);
+}
+
+void SA1IRAM::write(unsigned addr, uint8 data) {
+  scheduler.sync_copcpu();
+  memory::iram.write(addr, data);
+}
+
+//=======
+//CPUIRAM
+//=======
+
+unsigned CPUIRAM::size() const {
+  return memory::iram.size();
+}
+
+uint8 CPUIRAM::read(unsigned addr) {
+  scheduler.sync_cpucop();
+  return memory::iram.read(addr);
+}
+
+void CPUIRAM::write(unsigned addr, uint8 data) {
+  scheduler.sync_cpucop();
+  memory::iram.write(addr, data);
+}
+
+//========
+//SA1BWRAM
+//========
+
+unsigned SA1BWRAM::size() const {
+  return memory::cartram.size();
+}
+
+uint8 SA1BWRAM::read(unsigned addr) {
+  scheduler.sync_copcpu();
+  return memory::cartram.read(addr);
+}
+
+void SA1BWRAM::write(unsigned addr, uint8 data) {
+  scheduler.sync_copcpu();
+  memory::cartram.write(addr, data);
+}
+
+//========
+//CC1BWRAM
+//========
+
+unsigned CC1BWRAM::size() const {
+  return memory::cartram.size();
+}
+
+uint8 CC1BWRAM::read(unsigned addr) {
+  scheduler.sync_cpucop();
+  if(dma) return sa1.dma_cc1_read(addr);
+  return memory::cartram.read(addr);
+}
+
+void CC1BWRAM::write(unsigned addr, uint8 data) {
+  scheduler.sync_cpucop();
+  memory::cartram.write(addr, data);
+}
+
+//=========
+//BitmapRAM
+//=========
+
+unsigned BitmapRAM::size() const {
+  return 0x100000;
+}
+
+uint8 BitmapRAM::read(unsigned addr) {
+  scheduler.sync_copcpu();
+
+  if(sa1.mmio.bbf == 0) {
+    //4bpp
+    unsigned shift = addr & 1;
+    addr = (addr >> 1) & (memory::cartram.size() - 1);
+    switch(shift) { default:
+      case 0: return (memory::cartram.read(addr) >> 0) & 15;
+      case 1: return (memory::cartram.read(addr) >> 4) & 15;
+    }
+  } else {
+    //2bpp
+    unsigned shift = addr & 3;
+    addr = (addr >> 2) & (memory::cartram.size() - 1);
+    switch(shift) { default:
+      case 0: return (memory::cartram.read(addr) >> 0) & 3;
+      case 1: return (memory::cartram.read(addr) >> 2) & 3;
+      case 2: return (memory::cartram.read(addr) >> 4) & 3;
+      case 3: return (memory::cartram.read(addr) >> 6) & 3;
+    }
+  }
+}
+
+void BitmapRAM::write(unsigned addr, uint8 data) {
+  scheduler.sync_copcpu();
+
+  if(sa1.mmio.bbf == 0) {
+    //4bpp
+    unsigned shift = addr & 1;
+    addr = (addr >> 1) & (memory::cartram.size() - 1);
+    switch(shift) { default:
+      case 0: data = (memory::cartram.read(addr) & 0xf0) | ((data & 15) << 0); break;
+      case 1: data = (memory::cartram.read(addr) & 0x0f) | ((data & 15) << 4); break;
+    }
+  } else {
+    //2bpp
+    unsigned shift = addr & 3;
+    addr = (addr >> 2) & (memory::cartram.size() - 1);
+    switch(shift) { default:
+      case 0: data = (memory::cartram.read(addr) & 0xfc) | ((data &  3) << 0); break;
+      case 1: data = (memory::cartram.read(addr) & 0xf3) | ((data &  3) << 2); break;
+      case 2: data = (memory::cartram.read(addr) & 0xcf) | ((data &  3) << 4); break;
+      case 3: data = (memory::cartram.read(addr) & 0x3f) | ((data &  3) << 6); break;
+    }
+  }
+
+  memory::cartram.write(addr, data);
+}
+
+#endif

src/chip/sa1/bus/bus.hpp

@@ -0,0 +1,45 @@
+struct VBRBus : Bus {
+  void init();
+};
+
+struct SA1Bus : Bus {
+  void init();
+};
+
+struct VectorSelectionPage : Memory {
+  alwaysinline uint8 read(unsigned);
+  alwaysinline void write(unsigned, uint8);
+  void sync();
+  Memory *access;
+};
+
+struct CPUIRAM : Memory {
+  unsigned size() const;
+  alwaysinline uint8 read(unsigned);
+  alwaysinline void write(unsigned, uint8);
+};
+
+struct SA1IRAM : Memory {
+  unsigned size() const;
+  alwaysinline uint8 read(unsigned);
+  alwaysinline void write(unsigned, uint8);
+};
+
+struct SA1BWRAM : Memory {
+  unsigned size() const;
+  alwaysinline uint8 read(unsigned);
+  alwaysinline void write(unsigned, uint8);
+};
+
+struct CC1BWRAM : Memory {
+  unsigned size() const;
+  alwaysinline uint8 read(unsigned);
+  alwaysinline void write(unsigned, uint8);
+  bool dma;
+};
+
+struct BitmapRAM : Memory {
+  unsigned size() const;
+  alwaysinline uint8 read(unsigned);
+  alwaysinline void write(unsigned, uint8);
+};

src/chip/sa1/dma/dma.cpp

@@ -0,0 +1,139 @@
+#ifdef SA1_CPP
+
+//====================
+//direct data transfer
+//====================
+
+void SA1::dma_normal() {
+  while(mmio.dtc--) {
+    uint8 data = regs.mdr;
+    uint32 dsa = mmio.dsa++;
+    uint32 dda = mmio.dda++;
+
+    //source and destination cannot be the same
+    if(mmio.sd == DMA::SourceBWRAM && mmio.dd == DMA::DestBWRAM) continue;
+    if(mmio.sd == DMA::SourceIRAM  && mmio.dd == DMA::DestIRAM ) continue;
+
+    switch(mmio.sd) {
+      case DMA::SourceROM: {
+        if((dsa & 0x408000) == 0x008000 || (dsa & 0xc00000) == 0xc00000) {
+          data = sa1bus.read(dsa);
+        }
+      } break;
+
+      case DMA::SourceBWRAM: {
+        if((dsa & 0x40e000) == 0x006000 || (dsa & 0xf00000) == 0x400000) {
+          data = sa1bus.read(dsa);
+        }
+      } break;
+
+      case DMA::SourceIRAM: {
+        data = memory::iram.read(dsa & 0x07ff);
+      } break;
+    }
+
+    switch(mmio.dd) {
+      case DMA::DestBWRAM: {
+        if((dda & 0x40e000) == 0x006000 || (dda & 0xf00000) == 0x400000) {
+          sa1bus.write(dda, data);
+        }
+      } break;
+
+      case DMA::DestIRAM: {
+        memory::iram.write(dda & 0x07ff, data);
+      } break;
+    }
+  }
+
+  mmio.dma_irqfl = true;
+  if(mmio.dma_irqen) mmio.dma_irqcl = 0;
+}
+
+//((byte & 6) << 3) + (byte & 1) explanation:
+//transforms a byte index (0-7) into a planar index:
+//result[] = {  0,  1, 16, 17, 32, 33, 48, 49 };
+//works for 2bpp, 4bpp and 8bpp modes
+
+//===========================
+//type-1 character conversion
+//===========================
+
+void SA1::dma_cc1() {
+  memory::cc1bwram.dma = true;
+  mmio.chdma_irqfl = true;
+  if(mmio.chdma_irqen) {
+    mmio.chdma_irqcl = 0;
+    cpu.regs.irq = 1;
+  }
+}
+
+uint8 SA1::dma_cc1_read(unsigned addr) {
+  //16 bytes/char (2bpp); 32 bytes/char (4bpp); 64 bytes/char (8bpp)
+  unsigned charmask = (1 << (6 - mmio.dmacb)) - 1;
+
+  if((addr & charmask) == 0) {
+    //buffer next character to I-RAM
+    unsigned bpp = 2 << (2 - mmio.dmacb);
+    unsigned bpl = (8 << mmio.dmasize) >> mmio.dmacb;
+    unsigned bwmask = memory::cartram.size() - 1;
+    unsigned tile = ((addr - mmio.dsa) & bwmask) >> (6 - mmio.dmacb);
+    unsigned ty = (tile >> mmio.dmasize);
+    unsigned tx = tile & ((1 << mmio.dmasize) - 1);
+    unsigned bwaddr = mmio.dsa + ty * 8 * bpl + tx * bpp;
+
+    for(unsigned y = 0; y < 8; y++) {
+      uint64 data = 0;
+      for(unsigned byte = 0; byte < bpp; byte++) {
+        data |= (uint64)memory::cartram.read((bwaddr + byte) & bwmask) << (byte << 3);
+      }
+      bwaddr += bpl;
+
+      uint8 out[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+      for(unsigned x = 0; x < 8; x++) {
+        out[0] |= (data & 1) << (7 - x); data >>= 1;
+        out[1] |= (data & 1) << (7 - x); data >>= 1;
+        if(mmio.dmacb == 2) continue;
+        out[2] |= (data & 1) << (7 - x); data >>= 1;
+        out[3] |= (data & 1) << (7 - x); data >>= 1;
+        if(mmio.dmacb == 1) continue;
+        out[4] |= (data & 1) << (7 - x); data >>= 1;
+        out[5] |= (data & 1) << (7 - x); data >>= 1;
+        out[6] |= (data & 1) << (7 - x); data >>= 1;
+        out[7] |= (data & 1) << (7 - x); data >>= 1;
+      }
+
+      for(unsigned byte = 0; byte < bpp; byte++) {
+        unsigned p = mmio.dda + (y << 1) + ((byte & 6) << 3) + (byte & 1);
+        memory::iram.write(p & 0x07ff, out[byte]);
+      }
+    }
+  }
+
+  return memory::iram.read((mmio.dda + (addr & charmask)) & 0x07ff);
+}
+
+//===========================
+//type-2 character conversion
+//===========================
+
+void SA1::dma_cc2() {
+  //select register file index (0-7 or 8-15)
+  const uint8 *brf = &mmio.brf[(dma.line & 1) << 3];
+  unsigned bpp = 2 << (2 - mmio.dmacb);
+  unsigned addr = mmio.dda & 0x07ff;
+  addr &= ~((1 << (7 - mmio.dmacb)) - 1);
+  addr += (dma.line & 8) * bpp;
+  addr += (dma.line & 7) * 2;
+
+  for(unsigned byte = 0; byte < bpp; byte++) {
+    uint8 output = 0;
+    for(unsigned bit = 0; bit < 8; bit++) {
+      output |= ((brf[bit] >> byte) & 1) << (7 - bit);
+    }
+    memory::iram.write(addr + ((byte & 6) << 3) + (byte & 1), output);
+  }
+
+  dma.line = (dma.line + 1) & 15;
+}
+
+#endif

src/chip/sa1/dma/dma.hpp

@@ -0,0 +1,11 @@
+struct DMA {
+  enum CDEN { DmaNormal = 0, DmaCharConversion = 1 };
+  enum SD { SourceROM = 0, SourceBWRAM = 1, SourceIRAM = 2 };
+  enum DD { DestIRAM = 0, DestBWRAM = 1 };
+  unsigned line;
+} dma;
+
+void dma_normal();
+void dma_cc1();
+uint8 dma_cc1_read(unsigned addr);
+void dma_cc2();

src/chip/sa1/memory/memory.cpp

@@ -0,0 +1,24 @@
+#ifdef SA1_CPP
+
+//ROM, I-RAM and MMIO registers are accessed at ~10.74MHz (2 clock ticks)
+//BW-RAM is accessed at ~5.37MHz (4 clock ticks)
+//tick() == 2 clock ticks
+//note: bus conflict delays are not emulated at this time
+
+void SA1::op_io() {
+  tick();
+}
+
+uint8 SA1::op_read(unsigned addr) {
+  tick();
+  if(((addr & 0x40e000) == 0x006000) || ((addr & 0xd00000) == 0x400000)) tick();
+  return sa1bus.read(addr);
+}
+
+void SA1::op_write(unsigned addr, uint8 data) {
+  tick();
+  if(((addr & 0x40e000) == 0x006000) || ((addr & 0xd00000) == 0x400000)) tick();
+  sa1bus.write(addr, data);
+}
+
+#endif

src/chip/sa1/memory/memory.hpp

@@ -0,0 +1,5 @@
+alwaysinline void op_io();
+alwaysinline uint8 op_read(unsigned addr);
+alwaysinline void op_write(unsigned addr, uint8 data);
+
+uint8_t vbr_read(unsigned addr);

src/chip/sa1/mmio/mmio.cpp

@@ -0,0 +1,633 @@
+#ifdef SA1_CPP
+
+//BS-X flash carts, when present, are mapped to 0x400000+
+Memory& SA1::mmio_access(unsigned &addr) {
+  if(!memory::bsxflash.data()) return memory::cartrom;
+  if(addr < 0x400000) return memory::cartrom;
+  addr &= 0x3fffff;
+  return bsxflash;
+}
+
+//(CCNT) SA-1 control
+void SA1::mmio_w2200(uint8 data) {
+  if(mmio.sa1_resb && !(data & 0x80)) {
+    //reset SA-1 CPU
+    regs.pc.w = mmio.crv;
+    regs.pc.b = 0x00;
+  }
+
+  mmio.sa1_irq  = (data & 0x80);
+  mmio.sa1_rdyb = (data & 0x40);
+  mmio.sa1_resb = (data & 0x20);
+  mmio.sa1_nmi  = (data & 0x10);
+  mmio.smeg     = (data & 0x0f);
+
+  if(mmio.sa1_irq) {
+    mmio.sa1_irqfl = true;
+    if(mmio.sa1_irqen) mmio.sa1_irqcl = 0;
+  }
+
+  if(mmio.sa1_nmi) {
+    mmio.sa1_nmifl = true;
+    if(mmio.sa1_nmien) mmio.sa1_nmicl = 0;
+  }
+}
+
+//(SIE) S-CPU interrupt enable
+void SA1::mmio_w2201(uint8 data) {
+  if(!mmio.cpu_irqen && (data & 0x80)) {
+    if(mmio.cpu_irqfl) {
+      mmio.cpu_irqcl = 0;
+      cpu.regs.irq = 1;
+    }
+  }
+
+  if(!mmio.chdma_irqen && (data & 0x20)) {
+    if(mmio.chdma_irqfl) {
+      mmio.chdma_irqcl = 0;
+      cpu.regs.irq = 1;
+    }
+  }
+
+  mmio.cpu_irqen   = (data & 0x80);
+  mmio.chdma_irqen = (data & 0x20);
+}
+
+//(SIC) S-CPU interrupt clear
+void SA1::mmio_w2202(uint8 data) {
+  mmio.cpu_irqcl   = (data & 0x80);
+  mmio.chdma_irqcl = (data & 0x20);
+
+  if(mmio.cpu_irqcl  ) mmio.cpu_irqfl   = false;
+  if(mmio.chdma_irqcl) mmio.chdma_irqfl = false;
+
+  if(!mmio.cpu_irqfl && !mmio.chdma_irqfl) cpu.regs.irq = 0;
+}
+
+//(CRV) SA-1 reset vector
+void SA1::mmio_w2203(uint8 data) { mmio.crv = (mmio.crv & 0xff00) | data; }
+void SA1::mmio_w2204(uint8 data) { mmio.crv = (data << 8) | (mmio.crv & 0xff); }
+
+//(CNV) SA-1 NMI vector
+void SA1::mmio_w2205(uint8 data) { mmio.cnv = (mmio.cnv & 0xff00) | data; }
+void SA1::mmio_w2206(uint8 data) { mmio.cnv = (data << 8) | (mmio.cnv & 0xff); }
+
+//(CIV) SA-1 IRQ vector
+void SA1::mmio_w2207(uint8 data) { mmio.civ = (mmio.civ & 0xff00) | data; }
+void SA1::mmio_w2208(uint8 data) { mmio.civ = (data << 8) | (mmio.civ & 0xff); }
+
+//(SCNT) S-CPU control
+void SA1::mmio_w2209(uint8 data) {
+  mmio.cpu_irq  = (data & 0x80);
+  mmio.cpu_ivsw = (data & 0x40);
+  mmio.cpu_nvsw = (data & 0x10);
+  mmio.cmeg     = (data & 0x0f);
+
+  if(mmio.cpu_irq) {
+    mmio.cpu_irqfl = true;
+    if(mmio.cpu_irqen) {
+      mmio.cpu_irqcl = 0;
+      cpu.regs.irq = 1;
+    }
+  }
+}
+
+//(CIE) SA-1 interrupt enable
+void SA1::mmio_w220a(uint8 data) {
+  if(!mmio.sa1_irqen   && (data & 0x80) && mmio.sa1_irqfl  ) mmio.sa1_irqcl   = 0;
+  if(!mmio.timer_irqen && (data & 0x40) && mmio.timer_irqfl) mmio.timer_irqcl = 0;
+  if(!mmio.dma_irqen   && (data & 0x20) && mmio.dma_irqfl  ) mmio.dma_irqcl   = 0;
+  if(!mmio.sa1_nmien   && (data & 0x10) && mmio.sa1_nmifl  ) mmio.sa1_nmicl   = 0;
+
+  mmio.sa1_irqen   = (data & 0x80);
+  mmio.timer_irqen = (data & 0x40);
+  mmio.dma_irqen   = (data & 0x20);
+  mmio.sa1_nmien   = (data & 0x10);
+}
+
+//(CIC) SA-1 interrupt clear
+void SA1::mmio_w220b(uint8 data) {
+  mmio.sa1_irqcl   = (data & 0x80);
+  mmio.timer_irqcl = (data & 0x40);
+  mmio.dma_irqcl   = (data & 0x20);
+  mmio.sa1_nmicl   = (data & 0x10);
+
+  if(mmio.sa1_irqcl)   mmio.sa1_irqfl   = false;
+  if(mmio.timer_irqcl) mmio.timer_irqfl = false;
+  if(mmio.dma_irqcl)   mmio.dma_irqfl   = false;
+  if(mmio.sa1_nmicl)   mmio.sa1_nmifl   = false;
+}
+
+//(SNV) S-CPU NMI vector
+void SA1::mmio_w220c(uint8 data) { mmio.snv = (mmio.snv & 0xff00) | data;      }
+void SA1::mmio_w220d(uint8 data) { mmio.snv = (data << 8) | (mmio.snv & 0xff); }
+
+//(SIV) S-CPU IRQ vector
+void SA1::mmio_w220e(uint8 data) { mmio.siv = (mmio.siv & 0xff00) | data;      }
+void SA1::mmio_w220f(uint8 data) { mmio.siv = (data << 8) | (mmio.siv & 0xff); }
+
+//(TMC) H/V timer control
+void SA1::mmio_w2210(uint8 data) {
+  mmio.hvselb = (data & 0x80);
+  mmio.ven    = (data & 0x02);
+  mmio.hen    = (data & 0x01);
+}
+
+//(CTR) SA-1 timer restart
+void SA1::mmio_w2211(uint8 data) {
+  status.vcounter = 0;
+  status.hcounter = 0;
+}
+
+//(HCNT) H-count
+void SA1::mmio_w2212(uint8 data) { mmio.hcnt = (mmio.hcnt & 0xff00) | (data << 0); }
+void SA1::mmio_w2213(uint8 data) { mmio.hcnt = (mmio.hcnt & 0x00ff) | (data << 8); }
+
+//(VCNT) V-count
+void SA1::mmio_w2214(uint8 data) { mmio.vcnt = (mmio.vcnt & 0xff00) | (data << 0); }
+void SA1::mmio_w2215(uint8 data) { mmio.vcnt = (mmio.vcnt & 0x00ff) | (data << 8); }
+
+//(CXB) Super MMC bank C
+void SA1::mmio_w2220(uint8 data) {
+  mmio.cbmode = (data & 0x80);
+  mmio.cb     = (data & 0x07);
+
+  unsigned addr = mmio.cb << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.cbmode == 0) {
+       bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, memory::cartrom, 0x000000);
+    sa1bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, memory::cartrom, 0x000000);
+  } else {
+       bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, access, addr);
+
+  memory::vectorsp.sync();
+}
+
+//(DXB) Super MMC bank D
+void SA1::mmio_w2221(uint8 data) {
+  mmio.dbmode = (data & 0x80);
+  mmio.db     = (data & 0x07);
+
+  unsigned addr = mmio.db << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.dbmode == 0) {
+       bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, memory::cartrom, 0x100000);
+    sa1bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, memory::cartrom, 0x100000);
+  } else {
+       bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, access, addr);
+}
+
+//(EXB) Super MMC bank E
+void SA1::mmio_w2222(uint8 data) {
+  mmio.ebmode = (data & 0x80);
+  mmio.eb     = (data & 0x07);
+
+  unsigned addr = mmio.eb << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.ebmode == 0) {
+       bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom, 0x200000);
+    sa1bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom, 0x200000);
+  } else {
+       bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, access, addr);
+}
+
+//(FXB) Super MMC bank F
+void SA1::mmio_w2223(uint8 data) {
+  mmio.fbmode = (data & 0x80);
+  mmio.fb     = (data & 0x07);
+
+  unsigned addr = mmio.fb << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.fbmode == 0) {
+       bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, memory::cartrom, 0x300000);
+    sa1bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, memory::cartrom, 0x300000);
+  } else {
+       bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, access, addr);
+}
+
+//(BMAPS) S-CPU BW-RAM address mapping
+void SA1::mmio_w2224(uint8 data) {
+  mmio.sbm = (data & 0x1f);
+
+  bus.map(Bus::MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::cc1bwram, mmio.sbm * 0x2000, 0x2000);
+  bus.map(Bus::MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::cc1bwram, mmio.sbm * 0x2000, 0x2000);
+}
+
+//(BMAP) SA-1 BW-RAM address mapping
+void SA1::mmio_w2225(uint8 data) {
+  mmio.sw46 = (data & 0x80);
+  mmio.cbm  = (data & 0x7f);
+
+  if(mmio.sw46 == 0) {
+    //$[40-43]:[0000-ffff] x  32 projection
+    sa1bus.map(Bus::MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::sa1bwram, (mmio.cbm & 0x1f) * 0x2000, 0x2000);
+    sa1bus.map(Bus::MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::sa1bwram, (mmio.cbm & 0x1f) * 0x2000, 0x2000);
+  } else {
+    //$[60-6f]:[0000-ffff] x 128 projection
+    sa1bus.map(Bus::MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::bitmapram, mmio.cbm * 0x2000, 0x2000);
+    sa1bus.map(Bus::MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::bitmapram, mmio.cbm * 0x2000, 0x2000);
+  }
+}
+
+//(SWBE) S-CPU BW-RAM write enable
+void SA1::mmio_w2226(uint8 data) {
+  mmio.swen = (data & 0x80);
+}
+
+//(CWBE) SA-1 BW-RAM write enable
+void SA1::mmio_w2227(uint8 data) {
+  mmio.cwen = (data & 0x80);
+}
+
+//(BWPA) BW-RAM write-protected area
+void SA1::mmio_w2228(uint8 data) {
+  mmio.bwp = (data & 0x0f);
+}
+
+//(SIWP) S-CPU I-RAM write protection
+void SA1::mmio_w2229(uint8 data) {
+  mmio.siwp = data;
+}
+
+//(CIWP) SA-1 I-RAM write protection
+void SA1::mmio_w222a(uint8 data) {
+  mmio.ciwp = data;
+}
+
+//(DCNT) DMA control
+void SA1::mmio_w2230(uint8 data) {
+  mmio.dmaen = (data & 0x80);
+  mmio.dprio = (data & 0x40);
+  mmio.cden  = (data & 0x20);
+  mmio.cdsel = (data & 0x10);
+  mmio.dd    = (data & 0x04);
+  mmio.sd    = (data & 0x03);
+
+  if(mmio.dmaen == 0) dma.line = 0;
+}
+
+//(CDMA) character conversion DMA parameters
+void SA1::mmio_w2231(uint8 data) {
+  mmio.chdend  = (data & 0x80);
+  mmio.dmasize = (data >> 2) & 7;
+  mmio.dmacb   = (data & 0x03);
+
+  if(mmio.chdend) memory::cc1bwram.dma = false;
+  if(mmio.dmasize > 5) mmio.dmasize = 5;
+  if(mmio.dmacb   > 2) mmio.dmacb   = 2;
+}
+
+//(SDA) DMA source device start address
+void SA1::mmio_w2232(uint8 data) { mmio.dsa = (mmio.dsa & 0xffff00) | (data <<  0); }
+void SA1::mmio_w2233(uint8 data) { mmio.dsa = (mmio.dsa & 0xff00ff) | (data <<  8); }
+void SA1::mmio_w2234(uint8 data) { mmio.dsa = (mmio.dsa & 0x00ffff) | (data << 16); }
+
+//(DDA) DMA destination start address
+void SA1::mmio_w2235(uint8 data) {
+  mmio.dda = (mmio.dda & 0xffff00) | (data <<  0);
+}
+
+void SA1::mmio_w2236(uint8 data) {
+  mmio.dda = (mmio.dda & 0xff00ff) | (data <<  8);
+
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 0 && mmio.dd == DMA::DestIRAM) {
+      dma_normal();
+    } else if(mmio.cden == 1 && mmio.cdsel == 1) {
+      dma_cc1();
+    }
+  }
+}
+
+void SA1::mmio_w2237(uint8 data) {
+  mmio.dda = (mmio.dda & 0x00ffff) | (data << 16);
+
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 0 && mmio.dd == DMA::DestBWRAM) {
+      dma_normal();
+    }
+  }
+}
+
+//(DTC) DMA terminal counter
+void SA1::mmio_w2238(uint8 data) { mmio.dtc = (mmio.dtc & 0xff00) | (data << 0); }
+void SA1::mmio_w2239(uint8 data) { mmio.dtc = (mmio.dtc & 0x00ff) | (data << 8); }
+
+//(BBF) BW-RAM bitmap format
+void SA1::mmio_w223f(uint8 data) {
+  mmio.bbf = (data & 0x80);
+}
+
+//(BRF) bitmap register files
+void SA1::mmio_w2240(uint8 data) { mmio.brf[ 0] = data; }
+void SA1::mmio_w2241(uint8 data) { mmio.brf[ 1] = data; }
+void SA1::mmio_w2242(uint8 data) { mmio.brf[ 2] = data; }
+void SA1::mmio_w2243(uint8 data) { mmio.brf[ 3] = data; }
+void SA1::mmio_w2244(uint8 data) { mmio.brf[ 4] = data; }
+void SA1::mmio_w2245(uint8 data) { mmio.brf[ 5] = data; }
+void SA1::mmio_w2246(uint8 data) { mmio.brf[ 6] = data; }
+void SA1::mmio_w2247(uint8 data) { mmio.brf[ 7] = data;
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 1 && mmio.cdsel == 0) {
+      dma_cc2();
+    }
+  }
+}
+
+void SA1::mmio_w2248(uint8 data) { mmio.brf[ 8] = data; }
+void SA1::mmio_w2249(uint8 data) { mmio.brf[ 9] = data; }
+void SA1::mmio_w224a(uint8 data) { mmio.brf[10] = data; }
+void SA1::mmio_w224b(uint8 data) { mmio.brf[11] = data; }
+void SA1::mmio_w224c(uint8 data) { mmio.brf[12] = data; }
+void SA1::mmio_w224d(uint8 data) { mmio.brf[13] = data; }
+void SA1::mmio_w224e(uint8 data) { mmio.brf[14] = data; }
+void SA1::mmio_w224f(uint8 data) { mmio.brf[15] = data;
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 1 && mmio.cdsel == 0) {
+      dma_cc2();
+    }
+  }
+}
+
+//(MCNT) arithmetic control
+void SA1::mmio_w2250(uint8 data) {
+  mmio.acm = (data & 0x02);
+  mmio.md  = (data & 0x01);
+
+  if(mmio.acm) mmio.mr = 0;
+}
+
+//(MAL) multiplicand / dividend low
+void SA1::mmio_w2251(uint8 data) {
+  mmio.ma = (mmio.ma & 0xff00) | data;
+}
+
+//(MAH) multiplicand / dividend high
+void SA1::mmio_w2252(uint8 data) {
+  mmio.ma = (data << 8) | (mmio.ma & 0x00ff);
+}
+
+//(MBL) multiplier / divisor low
+void SA1::mmio_w2253(uint8 data) {
+  mmio.mb = (mmio.mb & 0xff00) | data;
+}
+
+//(MBH) multiplier / divisor high
+//multiplication / cumulative sum only resets MB
+//division resets both MA and MB
+void SA1::mmio_w2254(uint8 data) {
+  mmio.mb = (data << 8) | (mmio.mb & 0x00ff);
+
+  if(mmio.acm == 0) {
+    if(mmio.md == 0) {
+      //signed multiplication
+      mmio.mr = (int16)mmio.ma * (int16)mmio.mb;
+      mmio.mb = 0;
+    } else {
+      //unsigned division
+      if(mmio.mb == 0) {
+        mmio.mr = 0;
+      } else {
+        int16  quotient  = (int16)mmio.ma / (uint16)mmio.mb;
+        uint16 remainder = (int16)mmio.ma % (uint16)mmio.mb;
+        mmio.mr = (remainder << 16) | quotient;
+      }
+      mmio.ma = 0;
+      mmio.mb = 0;
+    }
+  } else {
+    //sigma (accumulative multiplication)
+    mmio.mr += (int16)mmio.ma * (int16)mmio.mb;
+    mmio.overflow = (mmio.mr >= (1ULL << 40));
+    mmio.mr &= (1ULL << 40) - 1;
+    mmio.mb = 0;
+  }
+}
+
+//(VBD) variable-length bit processing
+void SA1::mmio_w2258(uint8 data) {
+  mmio.hl = (data & 0x80);
+  mmio.vb = (data & 0x0f);
+  if(mmio.vb == 0) mmio.vb = 16;
+
+  if(mmio.hl == 0) {
+    //fixed mode
+    mmio.vbit += mmio.vb;
+    mmio.va += (mmio.vbit >> 3);
+    mmio.vbit &= 7;
+  }
+}
+
+//(VDA) variable-length bit game pak ROM start address
+void SA1::mmio_w2259(uint8 data) { mmio.va = (mmio.va & 0xffff00) | (data <<  0); }
+void SA1::mmio_w225a(uint8 data) { mmio.va = (mmio.va & 0xff00ff) | (data <<  8); }
+void SA1::mmio_w225b(uint8 data) { mmio.va = (mmio.va & 0x00ffff) | (data << 16); mmio.vbit = 0; }
+
+//(SFR) S-CPU flag read
+uint8 SA1::mmio_r2300() {
+  uint8 data;
+  data  = mmio.cpu_irqfl   << 7;
+  data |= mmio.cpu_ivsw    << 6;
+  data |= mmio.chdma_irqfl << 5;
+  data |= mmio.cpu_nvsw    << 4;
+  data |= mmio.cmeg;
+  return data;
+}
+
+//(CFR) SA-1 flag read
+uint8 SA1::mmio_r2301() {
+  uint8 data;
+  data  = mmio.sa1_irqfl   << 7;
+  data |= mmio.timer_irqfl << 6;
+  data |= mmio.dma_irqfl   << 5;
+  data |= mmio.sa1_nmifl   << 4;
+  data |= mmio.smeg;
+  return data;
+}
+
+//(HCR) hcounter read
+uint8 SA1::mmio_r2302() {
+  //latch counters
+  mmio.hcr = status.hcounter >> 2;
+  mmio.vcr = status.vcounter;
+                            return mmio.hcr >> 0; }
+uint8 SA1::mmio_r2303() { return mmio.hcr >> 8; }
+
+//(VCR) vcounter read
+uint8 SA1::mmio_r2304() { return mmio.vcr >> 0; }
+uint8 SA1::mmio_r2305() { return mmio.vcr >> 8; }
+
+//(MR) arithmetic result
+uint8 SA1::mmio_r2306() { return mmio.mr >>  0; }
+uint8 SA1::mmio_r2307() { return mmio.mr >>  8; }
+uint8 SA1::mmio_r2308() { return mmio.mr >> 16; }
+uint8 SA1::mmio_r2309() { return mmio.mr >> 24; }
+uint8 SA1::mmio_r230a() { return mmio.mr >> 32; }
+
+//(OF) arithmetic overflow flag
+uint8 SA1::mmio_r230b() { return mmio.overflow << 7; }
+
+//(VDPL) variable-length data read port low
+uint8 SA1::mmio_r230c() {
+  uint32 data = (vbrbus.read(mmio.va + 0) <<  0)
+              | (vbrbus.read(mmio.va + 1) <<  8)
+              | (vbrbus.read(mmio.va + 2) << 16);
+  data >>= mmio.vbit;
+  return data >> 0;
+}
+
+//(VDPH) variable-length data read port high
+uint8 SA1::mmio_r230d() {
+  uint32 data = (vbrbus.read(mmio.va + 0) <<  0)
+              | (vbrbus.read(mmio.va + 1) <<  8)
+              | (vbrbus.read(mmio.va + 2) << 16);
+  data >>= mmio.vbit;
+
+  if(mmio.hl == 1) {
+    //auto-increment mode
+    mmio.vbit += mmio.vb;
+    mmio.va += (mmio.vbit >> 3);
+    mmio.vbit &= 7;
+  }
+
+  return data >> 8;
+}
+
+//(VC) version code register
+uint8 SA1::mmio_r230e() {
+  return 0x01;  //true value unknown
+}
+
+uint8 SA1::mmio_read(unsigned addr) {
+  (co_active() == scheduler.thread_cpu ? scheduler.sync_cpucop() : scheduler.sync_copcpu());
+  addr &= 0xffff;
+
+  switch(addr) {
+    case 0x2300: return mmio_r2300();
+    case 0x2301: return mmio_r2301();
+    case 0x2302: return mmio_r2302();
+    case 0x2303: return mmio_r2303();
+    case 0x2304: return mmio_r2304();
+    case 0x2305: return mmio_r2305();
+    case 0x2306: return mmio_r2306();
+    case 0x2307: return mmio_r2307();
+    case 0x2308: return mmio_r2308();
+    case 0x2309: return mmio_r2309();
+    case 0x230a: return mmio_r230a();
+    case 0x230b: return mmio_r230b();
+    case 0x230c: return mmio_r230c();
+    case 0x230d: return mmio_r230d();
+    case 0x230e: return mmio_r230e();
+  }
+
+  return 0x00;
+}
+
+void SA1::mmio_write(unsigned addr, uint8 data) {
+  (co_active() == scheduler.thread_cpu ? scheduler.sync_cpucop() : scheduler.sync_copcpu());
+  addr &= 0xffff;
+
+  switch(addr) {
+    case 0x2200: return mmio_w2200(data);
+    case 0x2201: return mmio_w2201(data);
+    case 0x2202: return mmio_w2202(data);
+    case 0x2203: return mmio_w2203(data);
+    case 0x2204: return mmio_w2204(data);
+    case 0x2205: return mmio_w2205(data);
+    case 0x2206: return mmio_w2206(data);
+    case 0x2207: return mmio_w2207(data);
+    case 0x2208: return mmio_w2208(data);
+    case 0x2209: return mmio_w2209(data);
+    case 0x220a: return mmio_w220a(data);
+    case 0x220b: return mmio_w220b(data);
+    case 0x220c: return mmio_w220c(data);
+    case 0x220d: return mmio_w220d(data);
+    case 0x220e: return mmio_w220e(data);
+    case 0x220f: return mmio_w220f(data);
+
+    case 0x2210: return mmio_w2210(data);
+    case 0x2211: return mmio_w2211(data);
+    case 0x2212: return mmio_w2212(data);
+    case 0x2213: return mmio_w2213(data);
+    case 0x2214: return mmio_w2214(data);
+    case 0x2215: return mmio_w2215(data);
+
+    case 0x2220: return mmio_w2220(data);
+    case 0x2221: return mmio_w2221(data);
+    case 0x2222: return mmio_w2222(data);
+    case 0x2223: return mmio_w2223(data);
+    case 0x2224: return mmio_w2224(data);
+    case 0x2225: return mmio_w2225(data);
+    case 0x2226: return mmio_w2226(data);
+    case 0x2227: return mmio_w2227(data);
+    case 0x2228: return mmio_w2228(data);
+    case 0x2229: return mmio_w2229(data);
+    case 0x222a: return mmio_w222a(data);
+
+    case 0x2230: return mmio_w2230(data);
+    case 0x2231: return mmio_w2231(data);
+    case 0x2232: return mmio_w2232(data);
+    case 0x2233: return mmio_w2233(data);
+    case 0x2234: return mmio_w2234(data);
+    case 0x2235: return mmio_w2235(data);
+    case 0x2236: return mmio_w2236(data);
+    case 0x2237: return mmio_w2237(data);
+    case 0x2238: return mmio_w2238(data);
+    case 0x2239: return mmio_w2239(data);
+
+    case 0x223f: return mmio_w223f(data);
+    case 0x2240: return mmio_w2240(data);
+    case 0x2241: return mmio_w2241(data);
+    case 0x2242: return mmio_w2242(data);
+    case 0x2243: return mmio_w2243(data);
+    case 0x2244: return mmio_w2244(data);
+    case 0x2245: return mmio_w2245(data);
+    case 0x2246: return mmio_w2246(data);
+    case 0x2247: return mmio_w2247(data);
+    case 0x2248: return mmio_w2248(data);
+    case 0x2249: return mmio_w2249(data);
+    case 0x224a: return mmio_w224a(data);
+    case 0x224b: return mmio_w224b(data);
+    case 0x224c: return mmio_w224c(data);
+    case 0x224d: return mmio_w224d(data);
+    case 0x224e: return mmio_w224e(data);
+    case 0x224f: return mmio_w224f(data);
+
+    case 0x2250: return mmio_w2250(data);
+    case 0x2251: return mmio_w2251(data);
+    case 0x2252: return mmio_w2252(data);
+    case 0x2253: return mmio_w2253(data);
+    case 0x2254: return mmio_w2254(data);
+
+    case 0x2258: return mmio_w2258(data);
+    case 0x2259: return mmio_w2259(data);
+    case 0x225a: return mmio_w225a(data);
+    case 0x225b: return mmio_w225b(data);
+  }
+}
+
+#endif

src/chip/sa1/mmio/mmio.hpp

@@ -0,0 +1,256 @@
+uint8 mmio_read(unsigned addr);
+void mmio_write(unsigned addr, uint8 data);
+Memory& mmio_access(unsigned &addr);
+
+struct MMIO {
+  //$2200 CCNT
+  bool sa1_irq;
+  bool sa1_rdyb;
+  bool sa1_resb;
+  bool sa1_nmi;
+  uint8 smeg;
+
+  //$2201 SIE
+  bool cpu_irqen;
+  bool chdma_irqen;
+
+  //$2202 SIC
+  bool cpu_irqcl;
+  bool chdma_irqcl;
+
+  //$2203,$2204 CRV
+  uint16 crv;
+
+  //$2205,$2206 CNV
+  uint16 cnv;
+
+  //$2207,$2208 CIV
+  uint16 civ;
+
+  //$2209 SCNT
+  bool cpu_irq;
+  bool cpu_ivsw;
+  bool cpu_nvsw;
+  uint8 cmeg;
+
+  //$220a CIE
+  bool sa1_irqen;
+  bool timer_irqen;
+  bool dma_irqen;
+  bool sa1_nmien;
+
+  //$220b CIC
+  bool sa1_irqcl;
+  bool timer_irqcl;
+  bool dma_irqcl;
+  bool sa1_nmicl;
+
+  //$220c,$220d SNV
+  uint16 snv;
+
+  //$220e,$220f SIV
+  uint16 siv;
+
+  //$2210 TMC
+  bool hvselb;
+  bool ven;
+  bool hen;
+
+  //$2212,$2213
+  uint16 hcnt;
+
+  //$2214,$2215
+  uint16 vcnt;
+
+  //$2220 CXB
+  bool cbmode;
+  uint8 cb;
+
+  //$2221 DXB
+  bool dbmode;
+  uint8 db;
+
+  //$2222 EXB
+  bool ebmode;
+  uint8 eb;
+
+  //$2223 FXB
+  bool fbmode;
+  uint8 fb;
+
+  //$2224 BMAPS
+  uint8 sbm;
+
+  //$2225 BMAP
+  bool sw46;
+  uint8 cbm;
+
+  //$2226 SBWE
+  bool swen;
+
+  //$2227 CBWE
+  bool cwen;
+
+  //$2228 BWPA
+  uint8 bwp;
+
+  //$2229 SIWP
+  uint8 siwp;
+
+  //$222a CIWP
+  uint8 ciwp;
+
+  //$2230 DCNT
+  bool dmaen;
+  bool dprio;
+  bool cden;
+  bool cdsel;
+  bool dd;
+  uint8 sd;
+
+  //$2231 CDMA
+  bool chdend;
+  uint8 dmasize;
+  uint8 dmacb;
+
+  //$2232-$2234 SDA
+  uint32 dsa;
+
+  //$2235-$2237 DDA
+  uint32 dda;
+
+  //$2238,$2239 DTC
+  uint16 dtc;
+
+  //$223f BBF
+  bool bbf;
+
+  //$2240-224f BRF
+  uint8 brf[16];
+
+  //$2250 MCNT
+  bool acm;
+  bool md;
+
+  //$2251,$2252 MA
+  uint16 ma;
+
+  //$2253,$2254 MB
+  uint16 mb;
+
+  //$2258 VBD
+  bool hl;
+  uint8 vb;
+
+  //$2259-$225b VDA
+  uint32 va;
+  uint8 vbit;
+
+  //$2300 SFR
+  bool cpu_irqfl;
+  bool chdma_irqfl;
+
+  //$2301 CFR
+  bool sa1_irqfl;
+  bool timer_irqfl;
+  bool dma_irqfl;
+  bool sa1_nmifl;
+
+  //$2302,$2303 HCR
+  uint16 hcr;
+
+  //$2304,$2305 VCR
+  uint16 vcr;
+
+  //$2306-230a MR
+  uint64 mr;
+
+  //$230b OF
+  bool overflow;
+} mmio;
+
+void mmio_w2200(uint8);  //CCNT
+void mmio_w2201(uint8);  //SIE
+void mmio_w2202(uint8);  //SIC
+void mmio_w2203(uint8);  //CRVL
+void mmio_w2204(uint8);  //CRVH
+void mmio_w2205(uint8);  //CNVL
+void mmio_w2206(uint8);  //CNVH
+void mmio_w2207(uint8);  //CIVL
+void mmio_w2208(uint8);  //CIVH
+void mmio_w2209(uint8);  //SCNT
+void mmio_w220a(uint8);  //CIE
+void mmio_w220b(uint8);  //CIC
+void mmio_w220c(uint8);  //SNVL
+void mmio_w220d(uint8);  //SNVH
+void mmio_w220e(uint8);  //SIVL
+void mmio_w220f(uint8);  //SIVH
+void mmio_w2210(uint8);  //TMC
+void mmio_w2211(uint8);  //CTR
+void mmio_w2212(uint8);  //HCNTL
+void mmio_w2213(uint8);  //HCNTH
+void mmio_w2214(uint8);  //VCNTL
+void mmio_w2215(uint8);  //VCNTH
+void mmio_w2220(uint8);  //CXB
+void mmio_w2221(uint8);  //DXB
+void mmio_w2222(uint8);  //EXB
+void mmio_w2223(uint8);  //FXB
+void mmio_w2224(uint8);  //BMAPS
+void mmio_w2225(uint8);  //BMAP
+void mmio_w2226(uint8);  //SBWE
+void mmio_w2227(uint8);  //CBWE
+void mmio_w2228(uint8);  //BWPA
+void mmio_w2229(uint8);  //SIWP
+void mmio_w222a(uint8);  //CIWP
+void mmio_w2230(uint8);  //DCNT
+void mmio_w2231(uint8);  //CDMA
+void mmio_w2232(uint8);  //SDAL
+void mmio_w2233(uint8);  //SDAH
+void mmio_w2234(uint8);  //SDAB
+void mmio_w2235(uint8);  //DDAL
+void mmio_w2236(uint8);  //DDAH
+void mmio_w2237(uint8);  //DDAB
+void mmio_w2238(uint8);  //DTCL
+void mmio_w2239(uint8);  //DTCH
+void mmio_w223f(uint8);  //BBF
+void mmio_w2240(uint8);  //BRF0
+void mmio_w2241(uint8);  //BRF1
+void mmio_w2242(uint8);  //BRF2
+void mmio_w2243(uint8);  //BRF3
+void mmio_w2244(uint8);  //BRF4
+void mmio_w2245(uint8);  //BRF5
+void mmio_w2246(uint8);  //BRF6
+void mmio_w2247(uint8);  //BRF7
+void mmio_w2248(uint8);  //BRF8
+void mmio_w2249(uint8);  //BRF9
+void mmio_w224a(uint8);  //BRFA
+void mmio_w224b(uint8);  //BRFB
+void mmio_w224c(uint8);  //BRFC
+void mmio_w224d(uint8);  //BRFD
+void mmio_w224e(uint8);  //BRFE
+void mmio_w224f(uint8);  //BRFF
+void mmio_w2250(uint8);  //MCNT
+void mmio_w2251(uint8);  //MAL
+void mmio_w2252(uint8);  //MAH
+void mmio_w2253(uint8);  //MBL
+void mmio_w2254(uint8);  //MBH
+void mmio_w2258(uint8);  //VBD
+void mmio_w2259(uint8);  //VDAL
+void mmio_w225a(uint8);  //VDAH
+void mmio_w225b(uint8);  //VDAB
+
+uint8 mmio_r2300();  //SFR
+uint8 mmio_r2301();  //CFR
+uint8 mmio_r2302();  //HCRL
+uint8 mmio_r2303();  //HCRH
+uint8 mmio_r2304();  //VCRL
+uint8 mmio_r2305();  //VCRH
+uint8 mmio_r2306();  //MR [00-07]
+uint8 mmio_r2307();  //MR [08-15]
+uint8 mmio_r2308();  //MR [16-23]
+uint8 mmio_r2309();  //MR [24-31]
+uint8 mmio_r230a();  //MR [32-40]
+uint8 mmio_r230b();  //OF
+uint8 mmio_r230c();  //VDPL
+uint8 mmio_r230d();  //VDPH
+uint8 mmio_r230e();  //VC

src/chip/sa1/sa1.cpp

@@ -0,0 +1,321 @@
+#include <../base.hpp>
+
+#define SA1_CPP
+namespace SNES {
+
+SA1 sa1;
+
+#include "bus/bus.cpp"
+#include "dma/dma.cpp"
+#include "memory/memory.cpp"
+#include "mmio/mmio.cpp"
+
+void SA1::enter() {
+  while(true) {
+    while(mmio.sa1_rdyb || mmio.sa1_resb) {
+      //SA-1 co-processor is asleep
+      tick();
+      scheduler.sync_copcpu();
+    }
+
+    if(status.interrupt_pending) {
+      status.interrupt_pending = false;
+      interrupt(status.interrupt_vector);
+    }
+
+    (this->*opcode_table[op_readpc()])();
+  }
+}
+
+void SA1::last_cycle() {
+  if(mmio.sa1_nmi && !mmio.sa1_nmicl) {
+    status.interrupt_pending = true;
+    status.interrupt_vector  = mmio.cnv;
+    mmio.sa1_nmifl = true;
+    mmio.sa1_nmicl = 1;
+    regs.wai = false;
+  } else if(!regs.p.i) {
+    if(mmio.timer_irqen && !mmio.timer_irqcl) {
+      status.interrupt_pending = true;
+      status.interrupt_vector  = mmio.civ;
+      mmio.timer_irqfl = true;
+      regs.wai = false;
+    } else if(mmio.dma_irqen && !mmio.dma_irqcl) {
+      status.interrupt_pending = true;
+      status.interrupt_vector  = mmio.civ;
+      mmio.dma_irqfl = true;
+      regs.wai = false;
+    } else if(mmio.sa1_irq && !mmio.sa1_irqcl) {
+      status.interrupt_pending = true;
+      status.interrupt_vector  = mmio.civ;
+      mmio.sa1_irqfl = true;
+      regs.wai = false;
+    }
+  }
+}
+
+void SA1::interrupt(uint16 vector) {
+  op_read(regs.pc.d);
+  op_io();
+  if(!regs.e) op_writestack(regs.pc.b);
+  op_writestack(regs.pc.h);
+  op_writestack(regs.pc.l);
+  op_writestack(regs.e ? (regs.p & ~0x10) : regs.p);
+  regs.pc.w = vector;
+  regs.pc.b = 0x00;
+  regs.p.i  = 1;
+  regs.p.d  = 0;
+}
+
+bool SA1::interrupt_pending() {
+  return status.interrupt_pending;
+}
+
+void SA1::tick() {
+  scheduler.addclocks_cop(2);
+  if(++status.tick_counter == 0) scheduler.sync_copcpu();
+
+  //adjust counters:
+  //note that internally, status counters are in clocks;
+  //whereas MMIO register counters are in dots (4 clocks = 1 dot)
+  if(mmio.hvselb == 0) {
+    //HV timer
+    status.hcounter += 2;
+    if(status.hcounter >= 1364) {
+      status.hcounter = 0;
+      if(++status.vcounter >= status.scanlines) status.vcounter = 0;
+    }
+  } else {
+    //linear timer
+    status.hcounter += 2;
+    status.vcounter += (status.hcounter >> 11);
+    status.hcounter &= 0x07ff;
+    status.vcounter &= 0x01ff;
+  }
+
+  //test counters for timer IRQ
+  switch((mmio.ven << 1) + (mmio.hen << 0)) {
+    case 0: break;
+    case 1: if(status.hcounter == (mmio.hcnt << 2)) trigger_irq(); break;
+    case 2: if(status.vcounter == mmio.vcnt && status.hcounter == 0) trigger_irq(); break;
+    case 3: if(status.vcounter == mmio.hcnt && status.hcounter == (mmio.hcnt << 2)) trigger_irq(); break;
+  }
+}
+
+void SA1::trigger_irq() {
+  mmio.timer_irqfl = true;
+  if(mmio.timer_irqen) mmio.timer_irqcl = 0;
+}
+
+void SA1::init() {
+}
+
+void SA1::enable() {
+}
+
+void SA1::power() {
+  regs.a = regs.x = regs.y = 0x0000;
+  regs.s = 0x01ff;
+
+  reset();
+}
+
+void SA1::reset() {
+  memory::vectorsp.access = 0;
+  memory::cc1bwram.dma = false;
+  for(unsigned addr = 0; addr < memory::iram.size(); addr++) {
+    memory::iram.write(addr, 0x00);
+  }
+  vbrbus.init();
+  sa1bus.init();
+
+  regs.pc.d = 0x000000;
+  regs.x.h  = 0x00;
+  regs.y.h  = 0x00;
+  regs.s.h  = 0x01;
+  regs.d    = 0x0000;
+  regs.db   = 0x00;
+  regs.p    = 0x34;
+  regs.e    = 1;
+  regs.mdr  = 0x00;
+  regs.wai  = false;
+  update_table();
+
+  status.tick_counter = 0;
+
+  status.interrupt_pending = false;
+  status.interrupt_vector  = 0x0000;
+
+  status.scanlines = (system.region() == System::NTSC ? 262 : 312);
+  status.vcounter  = 0;
+  status.hcounter  = 0;
+
+  dma.line = 0;
+
+  //$2200 CCNT
+  mmio.sa1_irq  = false;
+  mmio.sa1_rdyb = false;
+  mmio.sa1_resb = true;
+  mmio.sa1_nmi  = false;
+  mmio.smeg     = 0;
+
+  //$2201 SIE
+  mmio.cpu_irqen   = false;
+  mmio.chdma_irqen = false;
+
+  //$2202 SIC
+  mmio.cpu_irqcl   = false;
+  mmio.chdma_irqcl = false;
+
+  //$2203,$2204 CRV
+  mmio.crv = 0x0000;
+
+  //$2205,$2206 CNV
+  mmio.cnv = 0x0000;
+
+  //$2207,$2208 CIV
+  mmio.civ = 0x0000;
+
+  //$2209 SCNT
+  mmio.cpu_irq  = false;
+  mmio.cpu_ivsw = false;
+  mmio.cpu_nvsw = false;
+  mmio.cmeg     = 0;
+
+  //$220a CIE
+  mmio.sa1_irqen   = false;
+  mmio.timer_irqen = false;
+  mmio.dma_irqen   = false;
+  mmio.sa1_nmien   = false;
+
+  //$220b CIC
+  mmio.sa1_irqcl   = false;
+  mmio.timer_irqcl = false;
+  mmio.dma_irqcl   = false;
+  mmio.sa1_nmicl   = false;
+
+  //$220c,$220d SNV
+  mmio.snv = 0x0000;
+
+  //$220e,$220f SIV
+  mmio.siv = 0x0000;
+
+  //$2210
+  mmio.hvselb = false;
+  mmio.ven    = false;
+  mmio.hen    = false;
+
+  //$2212,$2213 HCNT
+  mmio.hcnt = 0x0000;
+
+  //$2214,$2215 VCNT
+  mmio.vcnt = 0x0000;
+
+  //$2220-2223 CXB, DXB, EXB, FXB
+  mmio.cbmode = 0;
+  mmio.dbmode = 0;
+  mmio.ebmode = 0;
+  mmio.fbmode = 0;
+
+  mmio.cb = 0x00;
+  mmio.db = 0x01;
+  mmio.eb = 0x02;
+  mmio.fb = 0x03;
+
+  //$2224 BMAPS
+  mmio.sbm = 0x00;
+
+  //$2225 BMAP
+  mmio.sw46 = false;
+  mmio.cbm  = 0x00;
+
+  //$2226 SWBE
+  mmio.swen = false;
+
+  //$2227 CWBE
+  mmio.cwen = false;
+
+  //$2228 BWPA
+  mmio.bwp = 0x0f;
+
+  //$2229 SIWP
+  mmio.siwp = 0x00;
+
+  //$222a CIWP
+  mmio.ciwp = 0x00;
+
+  //$2230 DCNT
+  mmio.dmaen = false;
+  mmio.dprio = false;
+  mmio.cden  = false;
+  mmio.cdsel = false;
+  mmio.dd    = 0;
+  mmio.sd    = 0;
+
+  //$2231 CDMA
+  mmio.chdend  = false;
+  mmio.dmasize = 0;
+  mmio.dmacb   = 0;
+
+  //$2232-$2234 SDA
+  mmio.dsa = 0x000000;
+
+  //$2235-$2237 DDA
+  mmio.dda = 0x000000;
+
+  //$2238,$2239 DTC
+  mmio.dtc = 0x0000;
+
+  //$223f BBF
+  mmio.bbf = 0;
+
+  //$2240-$224f BRF
+  for(unsigned i = 0; i < 16; i++) {
+    mmio.brf[i] = 0x00;
+  }
+
+  //$2250 MCNT
+  mmio.acm = 0;
+  mmio.md  = 0;
+
+  //$2251,$2252 MA
+  mmio.ma = 0x0000;
+
+  //$2253,$2254 MB
+  mmio.mb = 0x0000;
+
+  //$2258 VBD
+  mmio.hl = false;
+  mmio.vb = 16;
+
+  //$2259-$225b
+  mmio.va   = 0x000000;
+  mmio.vbit = 0;
+
+  //$2300 SFR
+  mmio.cpu_irqfl   = false;
+  mmio.chdma_irqfl = false;
+
+  //$2301 CFR
+  mmio.sa1_irqfl   = false;
+  mmio.timer_irqfl = false;
+  mmio.dma_irqfl   = false;
+  mmio.sa1_nmifl   = false;
+
+  //$2302,$2303 HCR
+  mmio.hcr = 0x0000;
+
+  //$2304,$2305 VCR
+  mmio.vcr = 0x0000;
+
+  //$2306-$230a MR
+  mmio.mr = 0;
+
+  //$230b
+  mmio.overflow = false;
+}
+
+SA1::SA1() {
+}
+
+};

src/chip/sa1/sa1.hpp

@@ -0,0 +1,37 @@
+#include "bus/bus.hpp"
+
+class SA1 : public CPUcore, public MMIO {
+public:
+  #include "dma/dma.hpp"
+  #include "memory/memory.hpp"
+  #include "mmio/mmio.hpp"
+
+  struct Status {
+    uint8 tick_counter;
+
+    bool interrupt_pending;
+    uint16 interrupt_vector;
+
+    uint16 scanlines;
+    uint16 vcounter;
+    uint16 hcounter;
+  } status;
+
+  void enter();
+  void interrupt(uint16 vector);
+  void tick();
+
+  alwaysinline void trigger_irq();
+  alwaysinline void last_cycle();
+  alwaysinline bool interrupt_pending();
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  SA1();
+};
+
+extern SA1 sa1;
+extern SA1Bus sa1bus;

src/chip/sdd1/sdd1.cpp

@@ -1,12 +1,27 @@
-#include "../../base.h"
-#define SDD1_CPP
+#include <../base.hpp>
 
+#define SDD1_CPP
+namespace SNES {
+
+SDD1 sdd1;
+
+#include "serialization.cpp"
 #include "sdd1emu.cpp"
 
 void SDD1::init() {}
 
 void SDD1::enable() {
-  for(int i = 0x4800; i <= 0x4807; i++) memory::mmio.map(i, *this);
+  //hook S-CPU DMA MMIO registers to gather information for struct dma[];
+  //buffer address and transfer size information for use in SDD1::read()
+  for(unsigned i = 0x4300; i <= 0x437f; i++) {
+    cpu_mmio[i & 0x7f] = memory::mmio.mmio[i - 0x2000];
+    memory::mmio.map(i, *this);
+  }
+
+  //hook S-DD1 MMIO registers
+  for(unsigned i = 0x4800; i <= 0x4807; i++) {
+    memory::mmio.map(i, *this);
+  }
 }
 
 void SDD1::power() {
@@ -14,97 +29,133 @@ void SDD1::power() {
 }
 
 void SDD1::reset() {
-  sdd1.dma_active = false;
+  sdd1_enable = 0x00;
+  xfer_enable = 0x00;
 
-  regs.r4800 = 0x00;
-  regs.r4801 = 0x00;
+  mmc[0] = 0 << 20;
+  mmc[1] = 1 << 20;
+  mmc[2] = 2 << 20;
+  mmc[3] = 3 << 20;
 
-  regs.r4804 = 0x00;
-  regs.r4805 = 0x01;
-  regs.r4806 = 0x02;
-  regs.r4807 = 0x03;
+  for(unsigned i = 0; i < 8; i++) {
+    dma[i].addr = 0;
+    dma[i].size = 0;
+  }
 
-  bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, memory::cartrom, (regs.r4804 & 7) << 20);
-  bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, memory::cartrom, (regs.r4805 & 7) << 20);
-  bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, memory::cartrom, (regs.r4806 & 7) << 20);
-  bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, memory::cartrom, (regs.r4807 & 7) << 20);
+  buffer.ready = false;
+
+  bus.map(Bus::MapDirect, 0xc0, 0xff, 0x0000, 0xffff, *this);
 }
 
-uint8 SDD1::mmio_read(uint addr) {
-  switch(addr & 0xffff) {
-    case 0x4804: return regs.r4804;
-    case 0x4805: return regs.r4805;
-    case 0x4806: return regs.r4806;
-    case 0x4807: return regs.r4807;
+uint8 SDD1::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+
+  if((addr & 0x4380) == 0x4300) {
+    return cpu_mmio[addr & 0x7f]->mmio_read(addr);
+  }
+
+  switch(addr) {
+    case 0x4804: return mmc[0] >> 20;
+    case 0x4805: return mmc[1] >> 20;
+    case 0x4806: return mmc[2] >> 20;
+    case 0x4807: return mmc[3] >> 20;
   }
 
   return cpu.regs.mdr;
 }
 
-void SDD1::mmio_write(uint addr, uint8 data) {
-  switch(addr & 0xffff) {
-    case 0x4800: {
-      regs.r4800 = data;
-    } break;
+void SDD1::mmio_write(unsigned addr, uint8 data) {
+  addr &= 0xffff;
 
-    case 0x4801: {
-      regs.r4801 = data;
-    } break;
+  if((addr & 0x4380) == 0x4300) {
+    unsigned channel = (addr >> 4) & 7;
+    switch(addr & 15) {
+      case 2: dma[channel].addr = (dma[channel].addr & 0xffff00) + (data <<  0); break;
+      case 3: dma[channel].addr = (dma[channel].addr & 0xff00ff) + (data <<  8); break;
+      case 4: dma[channel].addr = (dma[channel].addr & 0x00ffff) + (data << 16); break;
 
-    case 0x4804: {
-      if(regs.r4804 != data) {
-        regs.r4804 = data;
-        bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4804 & 7) << 20);
-      }
-    } break;
+      case 5: dma[channel].size = (dma[channel].size &   0xff00) + (data <<  0); break;
+      case 6: dma[channel].size = (dma[channel].size &   0x00ff) + (data <<  8); break;
+    }
+    return cpu_mmio[addr & 0x7f]->mmio_write(addr, data);
+  }
 
-    case 0x4805: {
-      if(regs.r4805 != data) {
-        regs.r4805 = data;
-        bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4805 & 7) << 20);
-      }
-    } break;
+  switch(addr) {
+    case 0x4800: sdd1_enable = data; break;
+    case 0x4801: xfer_enable = data; break;
 
-    case 0x4806: {
-      if(regs.r4806 != data) {
-        regs.r4806 = data;
-        bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4806 & 7) << 20);
-      }
-    } break;
-
-    case 0x4807: {
-      if(regs.r4807 != data) {
-        regs.r4807 = data;
-        bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4807 & 7) << 20);
-      }
-    } break;
+    case 0x4804: mmc[0] = data << 20; break;
+    case 0x4805: mmc[1] = data << 20; break;
+    case 0x4806: mmc[2] = data << 20; break;
+    case 0x4807: mmc[3] = data << 20; break;
   }
 }
 
-void SDD1::dma_begin(uint8 channel, uint32 addr, uint16 length) {
-  if(regs.r4800 & (1 << channel) && regs.r4801 & (1 << channel)) {
-    regs.r4801 &= ~(1 << channel);
-    sdd1.dma_active   = true;
-    sdd1.buffer_index = 0;
-    sdd1.buffer_size  = length;
-    sdd1emu.decompress(addr, (length) ? length : 65536, sdd1.buffer);
-  }
+//SDD1::read() is mapped to $[c0-ff]:[0000-ffff]
+//the design is meant to be as close to the hardware design as possible, thus this code
+//avoids adding S-DD1 hooks inside S-CPU::DMA emulation.
+//
+//the real S-DD1 cannot see $420b (DMA enable) writes, as they are not placed on the bus.
+//however, $43x0-$43xf writes (DMAx channel settings) most likely do appear on the bus.
+//the S-DD1 also requires fixed addresses for transfers, which wouldn't be necessary if
+//it could see $420b writes (eg it would know when the transfer should begin.)
+//
+//the hardware needs a way to distinguish program code after $4801 writes from DMA
+//decompression that follows soon after.
+//
+//the only plausible design for hardware would be for the S-DD1 to spy on DMAx settings,
+//and begin spooling decompression on writes to $4801 that activate a channel. after that,
+//it feeds decompressed data only when the ROM read address matches the DMA channel address.
+//
+//the actual S-DD1 transfer can occur on any channel, but it is most likely limited to
+//one transfer per $420b write (for spooling purposes). however, this is not known for certain.
+uint8 SDD1::read(unsigned addr) {
+  if(sdd1_enable & xfer_enable) {
+    //at least one channel has S-DD1 decompression enabled ...
+    for(unsigned i = 0; i < 8; i++) {
+      if(sdd1_enable & xfer_enable & (1 << i)) {
+        //S-DD1 always uses fixed transfer mode, so address will not change during transfer
+        if(addr == dma[i].addr) {
+          if(!buffer.ready) {
+            //first byte read for channel performs full decompression.
+            //this really should stream byte-by-byte, but it's not necessary since the size is known
+            buffer.offset = 0;
+            buffer.size = dma[i].size ? dma[i].size : 65536;
+
+            //sdd1emu calls this function; it needs to access uncompressed data;
+            //so temporarily disable decompression mode for decompress() call.
+            uint8 temp = sdd1_enable;
+            sdd1_enable = false;
+            sdd1emu.decompress(addr, buffer.size, buffer.data);
+            sdd1_enable = temp;
+
+            buffer.ready = true;
+          }
+
+          //fetch a decompressed byte; once buffer is depleted, disable channel and invalidate buffer
+          uint8 data = buffer.data[(uint16)buffer.offset++];
+          if(buffer.offset >= buffer.size) {
+            buffer.ready = false;
+            xfer_enable &= ~(1 << i);
+          }
+
+          return data;
+        }  //address matched
+      }  //channel enabled
+    }  //channel loop
+  }  //S-DD1 decompressor enabled
+
+  //S-DD1 decompression mode inactive; return ROM data
+  return memory::cartrom.read(mmc[(addr >> 20) & 3] + (addr & 0x0fffff));
 }
 
-bool SDD1::dma_active() {
-  return sdd1.dma_active;
+void SDD1::write(unsigned addr, uint8 data) {
 }
 
-uint8 SDD1::dma_read() {
-  if(--sdd1.buffer_size == 0) sdd1.dma_active = false;
-
-//sdd1.buffer[] is 65536 bytes, and sdd1.buffer_index
-//is of type uint16, so no buffer overflow is possible
-  return sdd1.buffer[sdd1.buffer_index++];
+SDD1::SDD1() {
 }
 
-SDD1::SDD1() {}
+SDD1::~SDD1() {
+}
+
+};

src/chip/sdd1/sdd1.h

@@ -1,39 +0,0 @@
-#include "sdd1emu.h"
-
-class SDD1 : public MMIO {
-public:
-  void init();
-  void enable();
-  void power();
-  void reset();
-
-  uint8 mmio_read (uint addr);
-  void  mmio_write(uint addr, uint8 data);
-
-  void  dma_begin(uint8 channel, uint32 addr, uint16 length);
-  bool  dma_active();
-  uint8 dma_read();
-
-  SDD1();
-
-private:
-  SDD1emu sdd1emu;
-
-  struct {
-    uint8  buffer[65536]; //pointer to decompressed S-DD1 data, max DMA length is 65536
-    uint16 buffer_index;  //DMA read index into S-DD1 decompression buffer
-    uint16 buffer_size;
-    bool   dma_active;
-  } sdd1;
-
-  struct {
-    uint8 r4800;
-    uint8 r4801;
-    uint8 r4804;
-    uint8 r4805;
-    uint8 r4806;
-    uint8 r4807;
-  } regs;
-};
-
-extern SDD1 sdd1;

src/chip/sdd1/sdd1.hpp

@@ -0,0 +1,41 @@
+#include "sdd1emu.hpp"
+
+class SDD1 : public MMIO, public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
+
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
+
+  void serialize(serializer&);
+  SDD1();
+  ~SDD1();
+
+private:
+  MMIO *cpu_mmio[0x80];  //bus spying hooks to glean information for struct dma[]
+
+  uint8 sdd1_enable;     //channel bit-mask
+  uint8 xfer_enable;     //channel bit-mask
+  unsigned mmc[4];       //memory map controller ROM indices
+
+  struct {
+    unsigned addr;       //$43x2-$43x4 -- DMA transfer address
+    uint16 size;         //$43x5-$43x6 -- DMA transfer size
+  } dma[8];
+
+  SDD1emu sdd1emu;
+  struct {
+    uint8 data[65536];   //pointer to decompressed S-DD1 data
+    uint16 offset;       //read index into S-DD1 decompression buffer
+    unsigned size;       //length of data buffer; reads decrement counter, set ready to false at 0
+    bool ready;          //true when data[] is valid; false to invoke sdd1emu.decompress()
+  } buffer;
+};
+
+extern SDD1 sdd1;

src/chip/sdd1/sdd1emu.cpp

@@ -30,7 +30,8 @@ understood.
 
 ************************************************************************/
 
-#define SDD1_read(__addr) (bus.read(__addr))
+typedef uint8 bool8;
+#define SDD1_read(__addr) (sdd1.read(__addr))
 
 ////////////////////////////////////////////////////
 
@@ -448,4 +449,4 @@ SDD1emu::SDD1emu() :
 
 ///////////////////////////////////////////////////////////
 
-#endif //ifdef SDD1_CPP
+#endif

src/chip/sdd1/sdd1emu.hpp

@@ -28,7 +28,7 @@ understood.
 
 ************************************************************************/
 
-typedef uint8_t bool8;
+#define bool8 uint8
 
 class SDD1_IM {  //Input Manager
 
@@ -160,3 +160,5 @@ class SDD1emu {
   SDD1_OL OL;
 
 };
+
+#undef bool8

src/chip/sdd1/serialization.cpp

@@ -0,0 +1,19 @@
+#ifdef SDD1_CPP
+
+void SDD1::serialize(serializer &s) {
+  s.integer(sdd1_enable);
+  s.integer(xfer_enable);
+  s.array(mmc);
+
+  for(unsigned n = 0; n < 8; n++) {
+    s.integer(dma[n].addr);
+    s.integer(dma[n].size);
+  }
+
+  s.array(buffer.data);
+  s.integer(buffer.offset);
+  s.integer(buffer.size);
+  s.integer(buffer.ready);
+}
+
+#endif

src/chip/spc7110/decomp.hpp

@@ -4,6 +4,7 @@ public:
   void init(unsigned mode, unsigned offset, unsigned index);
   void reset();
 
+  void serialize(serializer&);
   SPC7110Decomp();
   ~SPC7110Decomp();
 

src/chip/spc7110/serialization.cpp

@@ -0,0 +1,81 @@
+#ifdef SPC7110_CPP
+
+void SPC7110Decomp::serialize(serializer &s) {
+  s.integer(decomp_mode);
+  s.integer(decomp_offset);
+
+  s.array(decomp_buffer, decomp_buffer_size);
+  s.integer(decomp_buffer_rdoffset);
+  s.integer(decomp_buffer_wroffset);
+  s.integer(decomp_buffer_length);
+
+  for(unsigned n = 0; n < 32; n++) {
+    s.integer(context[n].index);
+    s.integer(context[n].invert);
+  }
+}
+
+void SPC7110::serialize(serializer &s) {
+  s.integer(r4801);
+  s.integer(r4802);
+  s.integer(r4803);
+  s.integer(r4804);
+  s.integer(r4805);
+  s.integer(r4806);
+  s.integer(r4807);
+  s.integer(r4808);
+  s.integer(r4809);
+  s.integer(r480a);
+  s.integer(r480b);
+  s.integer(r480c);
+  decomp.serialize(s);
+
+  s.integer(r4811);
+  s.integer(r4812);
+  s.integer(r4813);
+  s.integer(r4814);
+  s.integer(r4815);
+  s.integer(r4816);
+  s.integer(r4817);
+  s.integer(r4818);
+  s.integer(r481x);
+  s.integer(r4814_latch);
+  s.integer(r4815_latch);
+
+  s.integer(r4820);
+  s.integer(r4821);
+  s.integer(r4822);
+  s.integer(r4823);
+  s.integer(r4824);
+  s.integer(r4825);
+  s.integer(r4826);
+  s.integer(r4827);
+  s.integer(r4828);
+  s.integer(r4829);
+  s.integer(r482a);
+  s.integer(r482b);
+  s.integer(r482c);
+  s.integer(r482d);
+  s.integer(r482e);
+  s.integer(r482f);
+
+  s.integer(r4830);
+  s.integer(r4831);
+  s.integer(r4832);
+  s.integer(r4833);
+  s.integer(r4834);
+
+  s.integer(dx_offset);
+  s.integer(ex_offset);
+  s.integer(fx_offset);
+
+  s.integer(r4840);
+  s.integer(r4841);
+  s.integer(r4842);
+
+  s.integer(rtc_state);
+  s.integer(rtc_mode);
+  s.integer(rtc_index);
+}
+
+#endif

src/chip/spc7110/spc7110.cpp

@@ -1,6 +1,11 @@
-#include "../../base.h"
-#define SPC7110_CPP
+#include <../base.hpp>
 
+#define SPC7110_CPP
+namespace SNES {
+
+SPC7110 spc7110;
+
+#include "serialization.cpp"
 #include "decomp.cpp"
 
 const unsigned SPC7110::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
@@ -8,7 +13,7 @@ const unsigned SPC7110::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 3
 void SPC7110::init() {}
 
 void SPC7110::enable() {
-  uint16_t limit = (cartridge.info.spc7110rtc ? 0x4842 : 0x483f);
+  uint16_t limit = (cartridge.has_spc7110rtc() ? 0x4842 : 0x483f);
   for(uint16_t i = 0x4800; i <= limit; i++) memory::mmio.map(i, *this);
 }
 
@@ -72,7 +77,7 @@ void SPC7110::reset() {
   r4841 = 0x00;
   r4842 = 0x00;
 
-  if(cartridge.info.spc7110rtc) {
+  if(cartridge.has_spc7110rtc()) {
     rtc_state = RTCS_Inactive;
     rtc_mode  = RTCM_Linear;
     rtc_index = 0;
@@ -92,18 +97,30 @@ void SPC7110::set_data_pointer(unsigned addr) { r4811 = addr; r4812 = addr >> 8;
 void SPC7110::set_data_adjust(unsigned addr)  { r4814 = addr; r4815 = addr >> 8; }
 
 void SPC7110::update_time(int offset) {
-  time_t rtc_time;
-  rtc_time  = memory::cartrtc.read(16);
-  rtc_time |= memory::cartrtc.read(17) << 8;
-  rtc_time |= memory::cartrtc.read(18) << 16;
-  rtc_time |= memory::cartrtc.read(19) << 24;
+  time_t rtc_time
+  = (memory::cartrtc.read(16) <<  0)
+  | (memory::cartrtc.read(17) <<  8)
+  | (memory::cartrtc.read(18) << 16)
+  | (memory::cartrtc.read(19) << 24);
+  time_t current_time = time(0) - offset;
+
+  //sizeof(time_t) is platform-dependent; though memory::cartrtc needs to be platform-agnostic.
+  //yet platforms with 32-bit signed time_t will overflow every ~68 years. handle this by
+  //accounting for overflow at the cost of 1-bit precision (to catch underflow). this will allow
+  //memory::cartrtc timestamp to remain valid for up to ~34 years from the last update, even if
+  //time_t overflows. calculation should be valid regardless of number representation, time_t size,
+  //or whether time_t is signed or unsigned.
+  time_t diff
+  = (current_time >= rtc_time)
+  ? (current_time - rtc_time)
+  : (std::numeric_limits<time_t>::max() - rtc_time + current_time + 1);  //compensate for overflow
+  if(diff > std::numeric_limits<time_t>::max() / 2) diff = 0;            //compensate for underflow
 
   bool update = true;
-  if(memory::cartrtc.read(13) & 1) update = false; //do not update if CR0 timer disable flag is set
-  if(memory::cartrtc.read(15) & 3) update = false; //do not update if CR2 timer disable flags are set
+  if(memory::cartrtc.read(13) & 1) update = false;  //do not update if CR0 timer disable flag is set
+  if(memory::cartrtc.read(15) & 3) update = false;  //do not update if CR2 timer disable flags are set
 
-  time_t current_time = time(0) - offset;
-  if(update && current_time > rtc_time) {
+  if(diff > 0 && update == true) {
     unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
     unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
     unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
@@ -114,9 +131,9 @@ void SPC7110::update_time(int offset) {
 
     day--;
     month--;
-    year += (year >= 90) ? 1900 : 2000; //range = 1990-2089
+    year += (year >= 90) ? 1900 : 2000;  //range = 1990-2089
 
-    second += (unsigned)(current_time - rtc_time);
+    second += diff;
     while(second >= 60) {
       second -= 60;
 
@@ -168,13 +185,13 @@ void SPC7110::update_time(int offset) {
     memory::cartrtc.write(12, weekday % 7);
   }
 
-  memory::cartrtc.write(16, current_time);
-  memory::cartrtc.write(17, current_time >> 8);
+  memory::cartrtc.write(16, current_time >>  0);
+  memory::cartrtc.write(17, current_time >>  8);
   memory::cartrtc.write(18, current_time >> 16);
   memory::cartrtc.write(19, current_time >> 24);
 }
 
-uint8 SPC7110::mmio_read(uint addr) {
+uint8 SPC7110::mmio_read(unsigned addr) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -215,7 +232,7 @@ uint8 SPC7110::mmio_read(uint addr) {
 
       unsigned addr = data_pointer();
       unsigned adjust = data_adjust();
-      if(r4818 & 8) adjust = (int16)adjust; //16-bit sign extend
+      if(r4818 & 8) adjust = (int16)adjust;  //16-bit sign extend
 
       unsigned adjustaddr = addr;
       if(r4818 & 2) {
@@ -226,7 +243,7 @@ uint8 SPC7110::mmio_read(uint addr) {
       uint8 data = memory::cartrom.read(datarom_addr(adjustaddr));
       if(!(r4818 & 2)) {
         unsigned increment = (r4818 & 1) ? data_increment() : 1;
-        if(r4818 & 4) increment = (int16)increment; //16-bit sign extend
+        if(r4818 & 4) increment = (int16)increment;  //16-bit sign extend
 
         if((r4818 & 16) == 0) {
           set_data_pointer(addr + increment);
@@ -250,7 +267,7 @@ uint8 SPC7110::mmio_read(uint addr) {
 
       unsigned addr = data_pointer();
       unsigned adjust = data_adjust();
-      if(r4818 & 8) adjust = (int16)adjust; //16-bit sign extend
+      if(r4818 & 8) adjust = (int16)adjust;  //16-bit sign extend
 
       uint8 data = memory::cartrom.read(datarom_addr(addr + adjust));
       if((r4818 & 0x60) == 0x60) {
@@ -322,7 +339,7 @@ uint8 SPC7110::mmio_read(uint addr) {
   return cpu.regs.mdr;
 }
 
-void SPC7110::mmio_write(uint addr, uint8 data) {
+void SPC7110::mmio_write(unsigned addr, uint8 data) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -373,11 +390,11 @@ void SPC7110::mmio_write(uint addr, uint8 data) {
 
       if((r4818 & 0x60) == 0x20) {
         unsigned increment = data_adjust() & 0xff;
-        if(r4818 & 8) increment = (int8)increment; //8-bit sign extend
+        if(r4818 & 8) increment = (int8)increment;  //8-bit sign extend
         set_data_pointer(data_pointer() + increment);
       } else if((r4818 & 0x60) == 0x40) {
         unsigned increment = data_adjust();
-        if(r4818 & 8) increment = (int16)increment; //16-bit sign extend
+        if(r4818 & 8) increment = (int16)increment;  //16-bit sign extend
         set_data_pointer(data_pointer() + increment);
       }
     } break;
@@ -390,11 +407,11 @@ void SPC7110::mmio_write(uint addr, uint8 data) {
 
       if((r4818 & 0x60) == 0x20) {
         unsigned increment = data_adjust() & 0xff;
-        if(r4818 & 8) increment = (int8)increment; //8-bit sign extend
+        if(r4818 & 8) increment = (int8)increment;  //8-bit sign extend
         set_data_pointer(data_pointer() + increment);
       } else if((r4818 & 0x60) == 0x40) {
         unsigned increment = data_adjust();
-        if(r4818 & 8) increment = (int16)increment; //16-bit sign extend
+        if(r4818 & 8) increment = (int16)increment;  //16-bit sign extend
         set_data_pointer(data_pointer() + increment);
       }
     } break;
@@ -518,17 +535,17 @@ void SPC7110::mmio_write(uint addr, uint8 data) {
 
     case 0x4831: {
       r4831 = data;
-      dx_offset = datarom_addr((data & 7) * 0x100000);
+      dx_offset = datarom_addr(data * 0x100000);
     } break;
 
     case 0x4832: {
       r4832 = data;
-      ex_offset = datarom_addr((data & 7) * 0x100000);
+      ex_offset = datarom_addr(data * 0x100000);
     } break;
 
     case 0x4833: {
       r4833 = data;
-      fx_offset = datarom_addr((data & 7) * 0x100000);
+      fx_offset = datarom_addr(data * 0x100000);
     } break;
 
     case 0x4834: r4834 = data; break;
@@ -615,7 +632,7 @@ void SPC7110::mmio_write(uint addr, uint8 data) {
   }
 }
 
-uint8 SPC7110::read(uint addr) {
+uint8 SPC7110::read(unsigned addr) {
   //$[00-0f|80-8f]:[8000-ffff], $[c0-cf]:[0000-ffff] mapped directly to memory::cartrom
 
   if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
@@ -646,7 +663,7 @@ uint8 SPC7110::read(uint addr) {
   return cpu.regs.mdr;
 }
 
-void SPC7110::write(uint addr, uint8 data) {
+void SPC7110::write(unsigned addr, uint8 data) {
   if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
     //$[00|30]:[6000-7fff]
     if(r4830 & 0x80) memory::cartram.write(addr & 0x1fff, data);
@@ -656,3 +673,5 @@ void SPC7110::write(uint addr, uint8 data) {
 
 SPC7110::SPC7110() {
 }
+
+};

src/chip/spc7110/spc7110.h

@@ -1,133 +0,0 @@
-/*****
- * SPC7110 emulator - version 0.03 (2008-08-10)
- * Copyright (c) 2008, byuu and neviksti
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * The software is provided "as is" and the author disclaims all warranties
- * with regard to this software including all implied warranties of
- * merchantibility and fitness, in no event shall the author be liable for
- * any special, direct, indirect, or consequential damages or any damages
- * whatsoever resulting from loss of use, data or profits, whether in an
- * action of contract, negligence or other tortious action, arising out of
- * or in connection with the use or performance of this software.
- *****/
-
-#include "decomp.h"
-
-class SPC7110 : public MMIO, public Memory {
-public:
-  void init();
-  void enable();
-  void power();
-  void reset();
-
-  unsigned datarom_addr(unsigned addr);
-
-  unsigned data_pointer();
-  unsigned data_adjust();
-  unsigned data_increment();
-  void set_data_pointer(unsigned addr);
-  void set_data_adjust(unsigned addr);
-
-  void update_time(int offset = 0);
-  time_t create_time();
-
-  uint8 mmio_read (uint addr);
-  void  mmio_write(uint addr, uint8 data);
-
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
-
-  //spc7110decomp
-  void decomp_init();
-  uint8 decomp_read();
-
-  SPC7110();
-
-private:
-  //==================
-  //decompression unit
-  //==================
-  uint8 r4801; //compression table low
-  uint8 r4802; //compression table high
-  uint8 r4803; //compression table bank
-  uint8 r4804; //compression table index
-  uint8 r4805; //decompression buffer index low
-  uint8 r4806; //decompression buffer index high
-  uint8 r4807; //???
-  uint8 r4808; //???
-  uint8 r4809; //compression length low
-  uint8 r480a; //compression length high
-  uint8 r480b; //decompression control register
-  uint8 r480c; //decompression status
-
-  SPC7110Decomp decomp;
-
-  //==============
-  //data port unit
-  //==============
-  uint8 r4811; //data pointer low
-  uint8 r4812; //data pointer high
-  uint8 r4813; //data pointer bank
-  uint8 r4814; //data adjust low
-  uint8 r4815; //data adjust high
-  uint8 r4816; //data increment low
-  uint8 r4817; //data increment high
-  uint8 r4818; //data port control register
-
-  uint8 r481x;
-
-  bool r4814_latch;
-  bool r4815_latch;
-
-  //=========
-  //math unit
-  //=========
-  uint8 r4820; //16-bit multiplicand B0, 32-bit dividend B0
-  uint8 r4821; //16-bit multiplicand B1, 32-bit dividend B1
-  uint8 r4822; //32-bit dividend B2
-  uint8 r4823; //32-bit dividend B3
-  uint8 r4824; //16-bit multiplier B0
-  uint8 r4825; //16-bit multiplier B1
-  uint8 r4826; //16-bit divisor B0
-  uint8 r4827; //16-bit divisor B1
-  uint8 r4828; //32-bit product B0, 32-bit quotient B0
-  uint8 r4829; //32-bit product B1, 32-bit quotient B1
-  uint8 r482a; //32-bit product B2, 32-bit quotient B2
-  uint8 r482b; //32-bit product B3, 32-bit quotient B3
-  uint8 r482c; //16-bit remainder B0
-  uint8 r482d; //16-bit remainder B1
-  uint8 r482e; //math control register
-  uint8 r482f; //math status
-
-  //===================
-  //memory mapping unit
-  //===================
-  uint8 r4830; //SRAM write enable
-  uint8 r4831; //$[d0-df]:[0000-ffff] mapping
-  uint8 r4832; //$[e0-ef]:[0000-ffff] mapping
-  uint8 r4833; //$[f0-ff]:[0000-ffff] mapping
-  uint8 r4834; //???
-
-  unsigned dx_offset;
-  unsigned ex_offset;
-  unsigned fx_offset;
-
-  //====================
-  //real-time clock unit
-  //====================
-  uint8 r4840; //RTC latch
-  uint8 r4841; //RTC index/data port
-  uint8 r4842; //RTC status
-
-  enum RTC_State { RTCS_Inactive, RTCS_ModeSelect, RTCS_IndexSelect, RTCS_Write } rtc_state;
-  enum RTC_Mode  { RTCM_Linear = 0x03, RTCM_Indexed = 0x0c } rtc_mode;
-  unsigned rtc_index;
-
-  static const unsigned months[12];
-};
-
-extern SPC7110 spc7110;

src/chip/spc7110/spc7110.hpp

@@ -0,0 +1,136 @@
+/*****
+ * SPC7110 emulator - version 0.03 (2008-08-10)
+ * Copyright (c) 2008, byuu and neviksti
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * The software is provided "as is" and the author disclaims all warranties
+ * with regard to this software including all implied warranties of
+ * merchantibility and fitness, in no event shall the author be liable for
+ * any special, direct, indirect, or consequential damages or any damages
+ * whatsoever resulting from loss of use, data or profits, whether in an
+ * action of contract, negligence or other tortious action, arising out of
+ * or in connection with the use or performance of this software.
+ *****/
+
+#include "decomp.hpp"
+
+class SPC7110 : public MMIO, public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  unsigned datarom_addr(unsigned addr);
+
+  unsigned data_pointer();
+  unsigned data_adjust();
+  unsigned data_increment();
+  void set_data_pointer(unsigned addr);
+  void set_data_adjust(unsigned addr);
+
+  void update_time(int offset = 0);
+  time_t create_time();
+
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
+
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
+
+  //spc7110decomp
+  void decomp_init();
+  uint8 decomp_read();
+
+  void serialize(serializer&);
+  SPC7110();
+
+private:
+  //==================
+  //decompression unit
+  //==================
+  uint8 r4801;  //compression table low
+  uint8 r4802;  //compression table high
+  uint8 r4803;  //compression table bank
+  uint8 r4804;  //compression table index
+  uint8 r4805;  //decompression buffer index low
+  uint8 r4806;  //decompression buffer index high
+  uint8 r4807;  //???
+  uint8 r4808;  //???
+  uint8 r4809;  //compression length low
+  uint8 r480a;  //compression length high
+  uint8 r480b;  //decompression control register
+  uint8 r480c;  //decompression status
+
+  SPC7110Decomp decomp;
+
+  //==============
+  //data port unit
+  //==============
+  uint8 r4811;  //data pointer low
+  uint8 r4812;  //data pointer high
+  uint8 r4813;  //data pointer bank
+  uint8 r4814;  //data adjust low
+  uint8 r4815;  //data adjust high
+  uint8 r4816;  //data increment low
+  uint8 r4817;  //data increment high
+  uint8 r4818;  //data port control register
+
+  uint8 r481x;
+
+  bool r4814_latch;
+  bool r4815_latch;
+
+  //=========
+  //math unit
+  //=========
+  uint8 r4820;  //16-bit multiplicand B0, 32-bit dividend B0
+  uint8 r4821;  //16-bit multiplicand B1, 32-bit dividend B1
+  uint8 r4822;  //32-bit dividend B2
+  uint8 r4823;  //32-bit dividend B3
+  uint8 r4824;  //16-bit multiplier B0
+  uint8 r4825;  //16-bit multiplier B1
+  uint8 r4826;  //16-bit divisor B0
+  uint8 r4827;  //16-bit divisor B1
+  uint8 r4828;  //32-bit product B0, 32-bit quotient B0
+  uint8 r4829;  //32-bit product B1, 32-bit quotient B1
+  uint8 r482a;  //32-bit product B2, 32-bit quotient B2
+  uint8 r482b;  //32-bit product B3, 32-bit quotient B3
+  uint8 r482c;  //16-bit remainder B0
+  uint8 r482d;  //16-bit remainder B1
+  uint8 r482e;  //math control register
+  uint8 r482f;  //math status
+
+  //===================
+  //memory mapping unit
+  //===================
+  uint8 r4830;  //SRAM write enable
+  uint8 r4831;  //$[d0-df]:[0000-ffff] mapping
+  uint8 r4832;  //$[e0-ef]:[0000-ffff] mapping
+  uint8 r4833;  //$[f0-ff]:[0000-ffff] mapping
+  uint8 r4834;  //???
+
+  unsigned dx_offset;
+  unsigned ex_offset;
+  unsigned fx_offset;
+
+  //====================
+  //real-time clock unit
+  //====================
+  uint8 r4840;  //RTC latch
+  uint8 r4841;  //RTC index/data port
+  uint8 r4842;  //RTC status
+
+  enum RTC_State { RTCS_Inactive, RTCS_ModeSelect, RTCS_IndexSelect, RTCS_Write };
+  enum RTC_Mode  { RTCM_Linear = 0x03, RTCM_Indexed = 0x0c };
+  unsigned rtc_state;
+  unsigned rtc_mode;
+  unsigned rtc_index;
+
+  static const unsigned months[12];
+};
+
+extern SPC7110 spc7110;

src/chip/srtc/serialization.cpp

@@ -0,0 +1,8 @@
+#ifdef SRTC_CPP
+
+void SRTC::serialize(serializer &s) {
+  s.integer(rtc_mode);
+  s.integer(rtc_index);
+}
+
+#endif

src/chip/srtc/srtc.cpp

@@ -1,4 +1,11 @@
-#include "../../base.h"
+#include <../base.hpp>
+
+#define SRTC_CPP
+namespace SNES {
+
+SRTC srtc;
+
+#include "serialization.cpp"
 
 const unsigned SRTC::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
 
@@ -15,20 +22,32 @@ void SRTC::power() {
 }
 
 void SRTC::reset() {
-  rtc_mode = RTCM_Read;
+  rtc_mode = RtcRead;
   rtc_index = -1;
   update_time();
 }
 
 void SRTC::update_time() {
-  time_t rtc_time;
-  rtc_time  = memory::cartrtc.read(16);
-  rtc_time |= memory::cartrtc.read(17) << 8;
-  rtc_time |= memory::cartrtc.read(18) << 16;
-  rtc_time |= memory::cartrtc.read(19) << 24;
-
+  time_t rtc_time
+  = (memory::cartrtc.read(16) <<  0)
+  | (memory::cartrtc.read(17) <<  8)
+  | (memory::cartrtc.read(18) << 16)
+  | (memory::cartrtc.read(19) << 24);
   time_t current_time = time(0);
-  if(current_time > rtc_time) {
+
+  //sizeof(time_t) is platform-dependent; though memory::cartrtc needs to be platform-agnostic.
+  //yet platforms with 32-bit signed time_t will overflow every ~68 years. handle this by
+  //accounting for overflow at the cost of 1-bit precision (to catch underflow). this will allow
+  //memory::cartrtc timestamp to remain valid for up to ~34 years from the last update, even if
+  //time_t overflows. calculation should be valid regardless of number representation, time_t size,
+  //or whether time_t is signed or unsigned.
+  time_t diff
+  = (current_time >= rtc_time)
+  ? (current_time - rtc_time)
+  : (std::numeric_limits<time_t>::max() - rtc_time + current_time + 1);  //compensate for overflow
+  if(diff > std::numeric_limits<time_t>::max() / 2) diff = 0;            //compensate for underflow
+
+  if(diff > 0) {
     unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
     unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
     unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
@@ -41,8 +60,7 @@ void SRTC::update_time() {
     month--;
     year += 1000;
 
-    second += (unsigned)(current_time - rtc_time);
-
+    second += diff;
     while(second >= 60) {
       second -= 60;
 
@@ -94,8 +112,8 @@ void SRTC::update_time() {
     memory::cartrtc.write(12, weekday % 7);
   }
 
-  memory::cartrtc.write(16, current_time);
-  memory::cartrtc.write(17, current_time >> 8);
+  memory::cartrtc.write(16, current_time >>  0);
+  memory::cartrtc.write(17, current_time >>  8);
   memory::cartrtc.write(18, current_time >> 16);
   memory::cartrtc.write(19, current_time >> 24);
 }
@@ -104,8 +122,8 @@ void SRTC::update_time() {
 //eg 0 = Sunday, 1 = Monday, ... 6 = Saturday
 //usage: weekday(2008, 1, 1) returns weekday of January 1st, 2008
 unsigned SRTC::weekday(unsigned year, unsigned month, unsigned day) {
-  unsigned y = 1900, m = 1; //epoch is 1900-01-01
-  unsigned sum = 0; //number of days passed since epoch
+  unsigned y = 1900, m = 1;  //epoch is 1900-01-01
+  unsigned sum = 0;          //number of days passed since epoch
 
   year = max(1900, year);
   month = max(1, min(12, month));
@@ -136,14 +154,14 @@ unsigned SRTC::weekday(unsigned year, unsigned month, unsigned day) {
   }
 
   sum += day - 1;
-  return (sum + 1) % 7; //1900-01-01 was a Monday
+  return (sum + 1) % 7;  //1900-01-01 was a Monday
 }
 
-uint8 SRTC::mmio_read(uint addr) {
+uint8 SRTC::mmio_read(unsigned addr) {
   addr &= 0xffff;
 
   if(addr == 0x2800) {
-    if(rtc_mode != RTCM_Read) return 0x00;
+    if(rtc_mode != RtcRead) return 0x00;
 
     if(rtc_index < 0) {
       update_time();
@@ -160,26 +178,26 @@ uint8 SRTC::mmio_read(uint addr) {
   return cpu.regs.mdr;
 }
 
-void SRTC::mmio_write(uint addr, uint8 data) {
+void SRTC::mmio_write(unsigned addr, uint8 data) {
   addr &= 0xffff;
 
   if(addr == 0x2801) {
-    data &= 0x0f; //only the low four bits are used
+    data &= 0x0f;  //only the low four bits are used
 
     if(data == 0x0d) {
-      rtc_mode = RTCM_Read;
+      rtc_mode = RtcRead;
       rtc_index = -1;
       return;
     }
 
     if(data == 0x0e) {
-      rtc_mode = RTCM_Command;
+      rtc_mode = RtcCommand;
       return;
     }
 
-    if(data == 0x0f) return; //unknown behavior
+    if(data == 0x0f) return;  //unknown behavior
 
-    if(rtc_mode == RTCM_Write) {
+    if(rtc_mode == RtcWrite) {
       if(rtc_index >= 0 && rtc_index < 12) {
         memory::cartrtc.write(rtc_index++, data);
 
@@ -193,17 +211,17 @@ void SRTC::mmio_write(uint addr, uint8 data) {
           memory::cartrtc.write(rtc_index++, weekday(year, month, day));
         }
       }
-    } else if(rtc_mode == RTCM_Command) {
+    } else if(rtc_mode == RtcCommand) {
       if(data == 0) {
-        rtc_mode = RTCM_Write;
+        rtc_mode = RtcWrite;
         rtc_index = 0;
       } else if(data == 4) {
-        rtc_mode = RTCM_Ready;
+        rtc_mode = RtcReady;
         rtc_index = -1;
         for(unsigned i = 0; i < 13; i++) memory::cartrtc.write(i, 0);
       } else {
         //unknown behavior
-        rtc_mode = RTCM_Ready;
+        rtc_mode = RtcReady;
       }
     }
   }
@@ -211,3 +229,5 @@ void SRTC::mmio_write(uint addr, uint8 data) {
 
 SRTC::SRTC() {
 }
+
+};

src/chip/srtc/srtc.hpp

@@ -1,22 +1,24 @@
 class SRTC : public MMIO {
 public:
-  void update_time();
-  unsigned weekday(unsigned year, unsigned month, unsigned day);
-
   void init();
   void enable();
   void power();
   void reset();
 
-  uint8 mmio_read (uint addr);
-  void  mmio_write(uint addr, uint8 data);
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
 
+  void serialize(serializer&);
   SRTC();
 
 private:
   static const unsigned months[12];
-  enum RTC_Mode { RTCM_Ready, RTCM_Command, RTCM_Read, RTCM_Write } rtc_mode;
+  enum RtcMode { RtcReady, RtcCommand, RtcRead, RtcWrite };
+  unsigned rtc_mode;
   signed rtc_index;
+
+  void update_time();
+  unsigned weekday(unsigned year, unsigned month, unsigned day);
 };
 
 extern SRTC srtc;

src/chip/st010/serialization.cpp

@@ -0,0 +1,7 @@
+#ifdef ST010_CPP
+
+void ST010::serialize(serializer &s) {
+  s.array(ram);
+}
+
+#endif

src/chip/st010/st010.cpp

@@ -1,9 +1,22 @@
-#include "../../base.h"
-#define ST010_CPP
+#include <../base.hpp>
 
-#include "st010_data.h"
+#define ST010_CPP
+namespace SNES {
+
+ST010 st010;
+
+#include "st010_data.hpp"
+#include "serialization.cpp"
 #include "st010_op.cpp"
 
+void ST010::init() {
+}
+
+void ST010::enable() {
+  bus.map(Bus::MapDirect, 0x68, 0x6f, 0x0000, 0x0fff, *this);
+  bus.map(Bus::MapDirect, 0xe8, 0xef, 0x0000, 0x0fff, *this);
+}
+
 int16 ST010::sin(int16 theta) {
   return sin_table[(theta >> 8) & 0xff];
 }
@@ -33,25 +46,19 @@ void ST010::writeb(uint16 addr, uint8 data) {
 }
 
 void ST010::writew(uint16 addr, uint16 data) {
-  writeb(addr + 0, data);
+  writeb(addr + 0, data >> 0);
   writeb(addr + 1, data >> 8);
 }
 
 void ST010::writed(uint16 addr, uint32 data) {
-  writeb(addr + 0, data);
-  writeb(addr + 1, data >> 8);
+  writeb(addr + 0, data >>  0);
+  writeb(addr + 1, data >>  8);
   writeb(addr + 2, data >> 16);
   writeb(addr + 3, data >> 24);
 }
 
 //
 
-void ST010::init() {
-}
-
-void ST010::enable() {
-}
-
 void ST010::power() {
   reset();
 }
@@ -62,11 +69,11 @@ void ST010::reset() {
 
 //
 
-uint8 ST010::read(uint addr) {
+uint8 ST010::read(unsigned addr) {
   return readb(addr);
 }
 
-void ST010::write(uint addr, uint8 data) {
+void ST010::write(unsigned addr, uint8 data) {
   writeb(addr, data);
 
   if((addr & 0xfff) == 0x0021 && (data & 0x80)) {
@@ -84,3 +91,5 @@ void ST010::write(uint addr, uint8 data) {
     ram[0x0021] &= ~0x80;
   }
 }
+
+};

src/chip/st010/st010.hpp

@@ -5,8 +5,10 @@ public:
   void power();
   void reset();
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
+
+  void serialize(serializer&);
 
 private:
   uint8 ram[0x1000];
@@ -14,11 +16,11 @@ private:
   static const int16 mode7_scale[176];
   static const uint8 arctan[32][32];
 
-//interfaces to sin table
+  //interfaces to sin table
   int16 sin(int16 theta);
   int16 cos(int16 theta);
 
-//interfaces to ram buffer
+  //interfaces to ram buffer
   uint8  readb (uint16 addr);
   uint16 readw (uint16 addr);
   uint32 readd (uint16 addr);
@@ -26,7 +28,7 @@ private:
   void   writew(uint16 addr, uint16 data);
   void   writed(uint16 addr, uint32 data);
 
-//opcodes
+  //opcodes
   void op_01();
   void op_02();
   void op_03();

src/chip/st010/st010_op.cpp

@@ -35,26 +35,26 @@ void ST010::op_01(int16 x0, int16 y0, int16 &x1, int16 &y1, int16 &quadrant, int
 //
 
 void ST010::op_01() {
-int16 x0 = readw(0x0000);
-int16 y0 = readw(0x0002);
-int16 x1, y1, quadrant, theta;
+  int16 x0 = readw(0x0000);
+  int16 y0 = readw(0x0002);
+  int16 x1, y1, quadrant, theta;
 
   op_01(x0, y0, x1, y1, quadrant, theta);
 
   writew(0x0000, x1);
   writew(0x0002, y1);
   writew(0x0004, quadrant);
-//writew(0x0006, y0); //Overload's docs note this write occurs, SNES9x disagrees
+//writew(0x0006, y0);  //Overload's docs note this write occurs, SNES9x disagrees
   writew(0x0010, theta);
 }
 
 void ST010::op_02() {
-int16 positions = readw(0x0024);
-uint16 *places  = (uint16*)(ram + 0x0040);
-uint16 *drivers = (uint16*)(ram + 0x0080);
+  int16 positions = readw(0x0024);
+  uint16 *places  = (uint16*)(ram + 0x0040);
+  uint16 *drivers = (uint16*)(ram + 0x0080);
 
-bool sorted;
-uint16 temp;
+  bool sorted;
+  uint16 temp;
   if(positions > 1) {
     do {
       sorted = true;
@@ -77,10 +77,10 @@ uint16 temp;
 }
 
 void ST010::op_03() {
-int16 x0 = readw(0x0000);
-int16 y0 = readw(0x0002);
-int16 multiplier = readw(0x0004);
-int32 x1, y1;
+  int16 x0 = readw(0x0000);
+  int16 y0 = readw(0x0002);
+  int16 multiplier = readw(0x0004);
+  int32 x1, y1;
 
   x1 = x0 * multiplier << 1;
   y1 = y0 * multiplier << 1;
@@ -90,121 +90,121 @@ int32 x1, y1;
 }
 
 void ST010::op_04() {
-int16 x = readw(0x0000);
-int16 y = readw(0x0002);
-int16 square;
-//calculate the vector length of (x,y)
+  int16 x = readw(0x0000);
+  int16 y = readw(0x0002);
+  int16 square;
+  //calculate the vector length of (x,y)
   square = (int16)sqrt((double)(y * y + x * x));
 
   writew(0x0010, square);
 }
 
 void ST010::op_05() {
-int32 dx, dy;
-int16 a1, b1, c1;
-uint16 o1;
-bool wrap = false;
+  int32 dx, dy;
+  int16 a1, b1, c1;
+  uint16 o1;
+  bool wrap = false;
 
-//target (x,y) coordinates
-int16 ypos_max = readw(0x00c0);
-int16 xpos_max = readw(0x00c2);
+  //target (x,y) coordinates
+  int16 ypos_max = readw(0x00c0);
+  int16 xpos_max = readw(0x00c2);
 
-//current coordinates and direction
-int32 ypos = readd(0x00c4);
-int32 xpos = readd(0x00c8);
-uint16 rot = readw(0x00cc);
+  //current coordinates and direction
+  int32 ypos = readd(0x00c4);
+  int32 xpos = readd(0x00c8);
+  uint16 rot = readw(0x00cc);
 
-//physics
-uint16 speed = readw(0x00d4);
-uint16 accel = readw(0x00d6);
-uint16 speed_max = readw(0x00d8);
+  //physics
+  uint16 speed = readw(0x00d4);
+  uint16 accel = readw(0x00d6);
+  uint16 speed_max = readw(0x00d8);
 
-//special condition acknowledgement
-int16 system = readw(0x00da);
-int16 flags = readw(0x00dc);
+  //special condition acknowledgement
+  int16 system = readw(0x00da);
+  int16 flags = readw(0x00dc);
 
-//new target coordinates
-int16 ypos_new = readw(0x00de);
-int16 xpos_new = readw(0x00e0);
+  //new target coordinates
+  int16 ypos_new = readw(0x00de);
+  int16 xpos_new = readw(0x00e0);
 
-//mask upper bit
+  //mask upper bit
   xpos_new &= 0x7fff;
 
-//get the current distance
+  //get the current distance
   dx = xpos_max - (xpos >> 16);
   dy = ypos_max - (ypos >> 16);
 
-//quirk: clear and move in9
+  //quirk: clear and move in9
   writew(0x00d2, 0xffff);
   writew(0x00da, 0x0000);
 
-//grab the target angle
+  //grab the target angle
   op_01(dy, dx, a1, b1, c1, (int16&)o1);
 
-//check for wrapping
+  //check for wrapping
   if(abs(o1 - rot) > 0x8000) {
     o1 += 0x8000;
     rot += 0x8000;
     wrap = true;
   }
 
-uint16 old_speed = speed;
+  uint16 old_speed = speed;
 
-//special case
+  //special case
   if(abs(o1 - rot) == 0x8000) {
     speed = 0x100;
   }
 
-//slow down for sharp curves
+  //slow down for sharp curves
   else if(abs(o1 - rot) >= 0x1000) {
   uint32 slow = abs(o1 - rot);
-    slow >>= 4; //scaling
+    slow >>= 4;  //scaling
     speed -= slow;
   }
 
-//otherwise accelerate
+  //otherwise accelerate
   else {
     speed += accel;
     if(speed > speed_max) {
-      speed = speed_max; //clip speed
+      speed = speed_max;  //clip speed
     }
   }
 
-//prevent negative/positive overflow
+  //prevent negative/positive overflow
   if(abs(old_speed - speed) > 0x8000) {
     if(old_speed < speed) { speed = 0; }
     else speed = 0xff00;
   }
 
-//adjust direction by so many degrees
-//be careful of negative adjustments
+  //adjust direction by so many degrees
+  //be careful of negative adjustments
   if((o1 > rot && (o1 - rot) > 0x80) || (o1 < rot && (rot - o1) >= 0x80)) {
     if(o1 < rot) { rot -= 0x280; }
     else if(o1 > rot) { rot += 0x280; }
   }
 
-//turn of wrapping
+  //turn off wrapping
   if(wrap) { rot -= 0x8000; }
 
-//now check the distances (store for later)
+  //now check the distances (store for later)
   dx = (xpos_max << 16) - xpos;
   dy = (ypos_max << 16) - ypos;
   dx >>= 16;
   dy >>= 16;
 
-//if we're in so many units of the target, signal it
+  //if we're in so many units of the target, signal it
   if((system && (dy <= 6 && dy >= -8) && (dx <= 126 && dx >= -128)) || (!system && (dx <= 6 && dx >= -8) && (dy <= 126 && dy >= -128))) {
-  //announce our new destination and flag it
+    //announce our new destination and flag it
     xpos_max = xpos_new & 0x7fff;
     ypos_max = ypos_new;
     flags |= 0x08;
   }
 
-//update position
+  //update position
   xpos -= (cos(rot) * 0x400 >> 15) * (speed >> 8) << 1;
   ypos -= (sin(rot) * 0x400 >> 15) * (speed >> 8) << 1;
 
-//quirk: mask upper byte
+  //quirk: mask upper byte
   xpos &= 0x1fffffff;
   ypos &= 0x1fffffff;
 
@@ -218,9 +218,9 @@ uint16 old_speed = speed;
 }
 
 void ST010::op_06() {
-int16 multiplicand = readw(0x0000);
-int16 multiplier = readw(0x0002);
-int32 product;
+  int16 multiplicand = readw(0x0000);
+  int16 multiplier = readw(0x0002);
+  int32 product;
 
   product = multiplicand * multiplier << 1;
 
@@ -228,9 +228,9 @@ int32 product;
 }
 
 void ST010::op_07() {
-int16 theta = readw(0x0000);
+  int16 theta = readw(0x0000);
 
-int16 data;
+  int16 data;
   for(int i = 0, offset = 0; i < 176; i++) {
     data = mode7_scale[i] * cos(theta) >> 15;
     writew(0x00f0 + offset, data);
@@ -246,10 +246,10 @@ int16 data;
 }
 
 void ST010::op_08() {
-int16 x0 = readw(0x0000);
-int16 y0 = readw(0x0002);
-int16 theta = readw(0x0004);
-int16 x1, y1;
+  int16 x0 = readw(0x0000);
+  int16 y0 = readw(0x0002);
+  int16 theta = readw(0x0004);
+  int16 x1, y1;
 
   x1 = (y0 * sin(theta) >> 15) + (x0 * cos(theta) >> 15);
   y1 = (y0 * cos(theta) >> 15) - (x0 * sin(theta) >> 15);
@@ -258,4 +258,4 @@ int16 x1, y1;
   writew(0x0012, y1);
 }
 
-#endif //ifdef ST010_CPP
+#endif

src/chip/st011/st011.cpp

@@ -0,0 +1,20 @@
+#include <../base.hpp>
+
+#define ST011_CPP
+namespace SNES {
+
+ST011 st011;
+
+void ST011::init() {
+}
+
+void ST011::enable() {
+}
+
+void ST011::power() {
+}
+
+void ST011::reset() {
+}
+
+};

src/chip/st011/st011.hpp

@@ -0,0 +1,9 @@
+class ST011 {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+};
+
+extern ST011 st011;

src/chip/st018/st018.cpp

@@ -0,0 +1,124 @@
+#include <../base.hpp>
+
+#define ST018_CPP
+namespace SNES {
+
+ST018 st018;
+
+uint8 ST018::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+  if(addr == 0x3800) return regs.r3800;
+  if(addr == 0x3804) return regs.r3804;
+  return cpu.regs.mdr;
+}
+
+void ST018::mmio_write(unsigned addr, uint8 data) {
+  addr &= 0xffff;
+
+  if(addr == 0x3802) {
+    switch(regs.mode) {
+      case Waiting: {
+        switch(data) {
+          case 0x01: regs.r3800 = regs.r3800_01; break;
+          case 0xaa: op_board_upload(); break;
+          case 0xb2: op_b2(); break;
+          case 0xb3: op_b3(); break;
+          case 0xb4: op_b4(); break;
+          case 0xb5: op_b5(); break;
+          case 0xf1: op_query_chip(); break;
+          case 0xf2: op_query_chip(); break;
+          default: fprintf(stdout, "* ST018 w3802::%.2x\n", data); break;
+        }
+      } return;
+
+      case BoardUpload: {
+        op_board_upload(data);
+      } return;
+    }
+  }
+
+  if(addr == 0x3804) {
+    regs.w3804 <<= 8;
+    regs.w3804  |= data;
+    regs.w3804  &= 0xffffff;
+    return;
+  }
+}
+
+void ST018::init() {
+}
+
+void ST018::enable() {
+  for(unsigned i = 0x3800; i <= 0x38ff; i++) memory::mmio.map(i, *this);
+}
+
+void ST018::power() {
+  reset();
+}
+
+void ST018::reset() {
+  regs.mode = Waiting;
+  regs.r3800 = 0x00;
+  regs.r3804 = 0x85;
+  regs.w3804 = 0;
+  for(unsigned i = 0; i < 97; i++) board[i] = 0;
+}
+
+//=============
+//ST018 opcodes
+//=============
+
+void ST018::op_board_upload() {
+  regs.mode = BoardUpload;
+  regs.counter = 0;
+  regs.r3800 = 0xe0;
+}
+
+void ST018::op_board_upload(uint8 data) {
+  board[regs.counter] = data;
+  regs.r3800 = 96 - regs.counter;
+  regs.counter++;
+  if(regs.counter >= 97) {
+    regs.mode = Waiting;
+    #if 0
+    for(unsigned y = 0; y < 9; y++) {
+      for(unsigned x = 0; x < 9; x++) {
+        fprintf(stdout, "%.2x ", board[y * 9 + x]);
+      }
+      fprintf(stdout, "\n");
+    }
+    for(unsigned n = 0; n < 16; n++) fprintf(stdout, "%.2x ", board[81 + n]);
+    fprintf(stdout, "\n\n");
+    #endif
+  }
+}
+
+void ST018::op_b2() {
+  fprintf(stdout, "* ST018 w3802::b2\n");
+  regs.r3800 = 0xe0;
+  regs.r3800_01 = 0;  //unknown
+}
+
+void ST018::op_b3() {
+  fprintf(stdout, "* ST018 w3802::b3\n");
+  regs.r3800 = 0xe0;
+  regs.r3800_01 = 1;  //0 = player lost?
+}
+
+void ST018::op_b4() {
+  fprintf(stdout, "* ST018 w3802::b4\n");
+  regs.r3800 = 0xe0;
+  regs.r3800_01 = 1;  //0 = player won?
+}
+
+void ST018::op_b5() {
+  fprintf(stdout, "* ST018 w3802::b5\n");
+  regs.r3800 = 0xe0;
+  regs.r3800_01 = 0;  //1 = move will result in checkmate?
+}
+
+void ST018::op_query_chip() {
+  regs.r3800 = 0x00;
+}
+
+};

src/chip/st018/st018.hpp

@@ -0,0 +1,51 @@
+class ST018 : public MMIO {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
+
+  enum mode_t { Waiting, BoardUpload };
+  struct regs_t {
+    mode_t mode;
+
+    uint8 r3800;
+    uint8 r3800_01;
+    uint8 r3804;
+
+    unsigned w3804;
+    unsigned counter;
+  } regs;
+
+  enum PieceID {
+    Pawn   = 0x00,  //foot soldier
+    Lance  = 0x04,  //incense chariot
+    Knight = 0x08,  //cassia horse
+    Silver = 0x0c,  //silver general
+    Gold   = 0x10,  //gold general
+    Rook   = 0x14,  //flying chariot
+    Bishop = 0x18,  //angle mover
+    King   = 0x1c,  //king
+  };
+
+  enum PieceFlag {
+    PlayerA = 0x20,
+    PlayerB = 0x40,
+  };
+
+  uint8 board[9 * 9 + 16];
+
+private:
+  void op_board_upload();
+  void op_board_upload(uint8 data);
+  void op_b2();
+  void op_b3();
+  void op_b4();
+  void op_b5();
+  void op_query_chip();
+};
+
+extern ST018 st018;

src/chip/superfx/bus/bus.cpp

@@ -0,0 +1,106 @@
+#ifdef SUPERFX_CPP
+
+SuperFXBus superfxbus;
+
+namespace memory {
+  static SuperFXGSUROM gsurom;
+  static SuperFXGSURAM gsuram;
+  static SuperFXCPUROM fxrom;
+  static SuperFXCPURAM fxram;
+};
+
+void SuperFXBus::init() {
+  map(MapDirect, 0x00, 0xff, 0x0000, 0xffff, memory::memory_unmapped);
+
+  map(MapLinear, 0x00, 0x3f, 0x0000, 0x7fff, memory::gsurom);
+  map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::gsurom);
+  map(MapLinear, 0x40, 0x5f, 0x0000, 0xffff, memory::gsurom);
+  map(MapLinear, 0x60, 0x7f, 0x0000, 0xffff, memory::gsuram);
+
+  bus.map(MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::fxram, 0x0000, 0x2000);
+  bus.map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::fxrom);
+  bus.map(MapLinear, 0x40, 0x5f, 0x0000, 0xffff, memory::fxrom);
+  bus.map(MapLinear, 0x60, 0x7d, 0x0000, 0xffff, memory::fxram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::fxram, 0x0000, 0x2000);
+  bus.map(MapLinear, 0x80, 0xbf, 0x8000, 0xffff, memory::fxrom);
+  bus.map(MapLinear, 0xc0, 0xdf, 0x0000, 0xffff, memory::fxrom);
+  bus.map(MapLinear, 0xe0, 0xff, 0x0000, 0xffff, memory::fxram);
+}
+
+//ROM / RAM access from the SuperFX CPU
+
+unsigned SuperFXGSUROM::size() const {
+  return memory::cartrom.size();
+}
+
+uint8 SuperFXGSUROM::read(unsigned addr) {
+  while(!superfx.regs.scmr.ron) {
+    superfx.add_clocks(6);
+    scheduler.sync_copcpu();
+  }
+  return memory::cartrom.read(addr);
+}
+
+void SuperFXGSUROM::write(unsigned addr, uint8 data) {
+  while(!superfx.regs.scmr.ron) {
+    superfx.add_clocks(6);
+    scheduler.sync_copcpu();
+  }
+  memory::cartrom.write(addr, data);
+}
+
+unsigned SuperFXGSURAM::size() const {
+  return memory::cartram.size();
+}
+
+uint8 SuperFXGSURAM::read(unsigned addr) {
+  while(!superfx.regs.scmr.ran) {
+    superfx.add_clocks(6);
+    scheduler.sync_copcpu();
+  }
+  return memory::cartram.read(addr);
+}
+
+void SuperFXGSURAM::write(unsigned addr, uint8 data) {
+  while(!superfx.regs.scmr.ran) {
+    superfx.add_clocks(6);
+    scheduler.sync_copcpu();
+  }
+  memory::cartram.write(addr, data);
+}
+
+//ROM / RAM access from the S-CPU
+
+unsigned SuperFXCPUROM::size() const {
+  return memory::cartrom.size();
+}
+
+uint8 SuperFXCPUROM::read(unsigned addr) {
+  if(superfx.regs.sfr.g && superfx.regs.scmr.ron) {
+    static const uint8_t data[16] = {
+      0x00, 0x01, 0x00, 0x01, 0x04, 0x01, 0x00, 0x01,
+      0x00, 0x01, 0x08, 0x01, 0x00, 0x01, 0x0c, 0x01,
+    };
+    return data[addr & 15];
+  }
+  return memory::cartrom.read(addr);
+}
+
+void SuperFXCPUROM::write(unsigned addr, uint8 data) {
+  memory::cartrom.write(addr, data);
+}
+
+unsigned SuperFXCPURAM::size() const {
+  return memory::cartram.size();
+}
+
+uint8 SuperFXCPURAM::read(unsigned addr) {
+  if(superfx.regs.sfr.g && superfx.regs.scmr.ran) return cpu.regs.mdr;
+  return memory::cartram.read(addr);
+}
+
+void SuperFXCPURAM::write(unsigned addr, uint8 data) {
+  memory::cartram.write(addr, data);
+}
+
+#endif

src/chip/superfx/bus/bus.hpp

@@ -0,0 +1,27 @@
+struct SuperFXBus : Bus {
+  void init();
+};
+
+struct SuperFXGSUROM : Memory {
+  unsigned size() const;
+  uint8 read(unsigned);
+  void write(unsigned, uint8);
+};
+
+struct SuperFXGSURAM : Memory {
+  unsigned size() const;
+  uint8 read(unsigned);
+  void write(unsigned, uint8);
+};
+
+struct SuperFXCPUROM : Memory {
+  unsigned size() const;
+  uint8 read(unsigned);
+  void write(unsigned, uint8);
+};
+
+struct SuperFXCPURAM : Memory {
+  unsigned size() const;
+  uint8 read(unsigned);
+  void write(unsigned, uint8);
+};

src/chip/superfx/core/core.cpp

@@ -0,0 +1,107 @@
+#ifdef SUPERFX_CPP
+
+#include "opcodes.cpp"
+#include "opcode_table.cpp"
+
+uint8 SuperFX::color(uint8 source) {
+  if(regs.por.highnibble) return (regs.colr & 0xf0) | (source >> 4);
+  if(regs.por.freezehigh) return (regs.colr & 0xf0) | (source & 0x0f);
+  return source;
+}
+
+void SuperFX::plot(uint8 x, uint8 y) {
+  uint8 color = regs.colr;
+
+  if(regs.por.dither && regs.scmr.md != 3) {
+    if((x ^ y) & 1) color >>= 4;
+    color &= 0x0f;
+  }
+
+  if(!regs.por.transparent) {
+    if(regs.scmr.md == 3) {
+      if(regs.por.freezehigh) {
+        if((color & 0x0f) == 0) return;
+      } else {
+        if(color == 0) return;
+      }
+    } else {
+      if((color & 0x0f) == 0) return;
+    }
+  }
+
+  uint16 offset = (y << 5) + (x >> 3);
+  if(offset != pixelcache[0].offset) {
+    pixelcache_flush(pixelcache[1]);
+    pixelcache[1] = pixelcache[0];
+    pixelcache[0].bitpend = 0x00;
+    pixelcache[0].offset = offset;
+  }
+
+  x = (x & 7) ^ 7;
+  pixelcache[0].data[x] = color;
+  pixelcache[0].bitpend |= 1 << x;
+  if(pixelcache[0].bitpend == 0xff) {
+    pixelcache_flush(pixelcache[1]);
+    pixelcache[1] = pixelcache[0];
+    pixelcache[0].bitpend = 0x00;
+  }
+}
+
+uint8 SuperFX::rpix(uint8 x, uint8 y) {
+  pixelcache_flush(pixelcache[1]);
+  pixelcache_flush(pixelcache[0]);
+
+  unsigned cn;  //character number
+  switch(regs.por.obj ? 3 : regs.scmr.ht) {
+    case 0: cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 3); break;
+    case 1: cn = ((x & 0xf8) << 1) + ((x & 0xf8) >> 1) + ((y & 0xf8) >> 3); break;
+    case 2: cn = ((x & 0xf8) << 1) + ((x & 0xf8) << 0) + ((y & 0xf8) >> 3); break;
+    case 3: cn = ((y & 0x80) << 2) + ((x & 0x80) << 1) + ((y & 0x78) << 1) + ((x & 0x78) >> 3); break;
+  }
+  unsigned bpp = 2 << (regs.scmr.md - (regs.scmr.md >> 1));  // = [regs.scmr.md]{ 2, 4, 4, 8 };
+  unsigned addr = 0x700000 + (cn * (bpp << 3)) + (regs.scbr << 10) + ((y & 0x07) * 2);
+  uint8 data = 0x00;
+  x = (x & 7) ^ 7;
+
+  for(unsigned n = 0; n < bpp; n++) {
+    unsigned byte = ((n >> 1) << 4) + (n & 1);  // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
+    add_clocks(memory_access_speed);
+    data |= ((superfxbus.read(addr + byte) >> x) & 1) << n;
+  }
+
+  return data;
+}
+
+void SuperFX::pixelcache_flush(pixelcache_t &cache) {
+  if(cache.bitpend == 0x00) return;
+
+  uint8 x = cache.offset << 3;
+  uint8 y = cache.offset >> 5;
+
+  unsigned cn;  //character number
+  switch(regs.por.obj ? 3 : regs.scmr.ht) {
+    case 0: cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 3); break;
+    case 1: cn = ((x & 0xf8) << 1) + ((x & 0xf8) >> 1) + ((y & 0xf8) >> 3); break;
+    case 2: cn = ((x & 0xf8) << 1) + ((x & 0xf8) << 0) + ((y & 0xf8) >> 3); break;
+    case 3: cn = ((y & 0x80) << 2) + ((x & 0x80) << 1) + ((y & 0x78) << 1) + ((x & 0x78) >> 3); break;
+  }
+  unsigned bpp = 2 << (regs.scmr.md - (regs.scmr.md >> 1));  // = [regs.scmr.md]{ 2, 4, 4, 8 };
+  unsigned addr = 0x700000 + (cn * (bpp << 3)) + (regs.scbr << 10) + ((y & 0x07) * 2);
+
+  for(unsigned n = 0; n < bpp; n++) {
+    unsigned byte = ((n >> 1) << 4) + (n & 1);  // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
+    uint8 data = 0x00;
+    for(unsigned x = 0; x < 8; x++) data |= ((cache.data[x] >> n) & 1) << x;
+    if(cache.bitpend != 0xff) {
+      add_clocks(memory_access_speed);
+      data &= cache.bitpend;
+      data |= superfxbus.read(addr + byte) & ~cache.bitpend;
+    }
+    add_clocks(memory_access_speed);
+    superfxbus.write(addr + byte, data);
+  }
+
+  cache.bitpend = 0x00;
+}
+
+#endif

src/chip/superfx/core/core.hpp

@@ -0,0 +1,92 @@
+#include "registers.hpp"
+
+uint8 color(uint8 source);
+void plot(uint8 x, uint8 y);
+uint8 rpix(uint8 x, uint8 y);
+void pixelcache_flush(pixelcache_t &cache);
+
+void (SuperFX::*opcode_table[1024])();
+void initialize_opcode_table();
+
+//opcodes.cpp
+template<int> void op_adc_i();
+template<int> void op_adc_r();
+template<int> void op_add_i();
+template<int> void op_add_r();
+void op_alt1();
+void op_alt2();
+void op_alt3();
+template<int> void op_and_i();
+template<int> void op_and_r();
+void op_asr();
+void op_bge();
+void op_bcc();
+void op_bcs();
+void op_beq();
+template<int> void op_bic_i();
+template<int> void op_bic_r();
+void op_blt();
+void op_bmi();
+void op_bne();
+void op_bpl();
+void op_bra();
+void op_bvc();
+void op_bvs();
+void op_cache();
+void op_cmode();
+template<int> void op_cmp_r();
+void op_color();
+template<int> void op_dec_r();
+void op_div2();
+void op_fmult();
+template<int> void op_from_r();
+void op_getb();
+void op_getbl();
+void op_getbh();
+void op_getbs();
+void op_getc();
+void op_hib();
+template<int> void op_ibt_r();
+template<int> void op_inc_r();
+template<int> void op_iwt_r();
+template<int> void op_jmp_r();
+template<int> void op_ldb_ir();
+template<int> void op_ldw_ir();
+template<int> void op_link();
+template<int> void op_ljmp_r();
+template<int> void op_lm_r();
+template<int> void op_lms_r();
+void op_lmult();
+void op_lob();
+void op_loop();
+void op_lsr();
+void op_merge();
+template<int> void op_mult_i();
+template<int> void op_mult_r();
+void op_nop();
+void op_not();
+template<int> void op_or_i();
+template<int> void op_or_r();
+void op_plot();
+void op_ramb();
+void op_rol();
+void op_romb();
+void op_ror();
+void op_rpix();
+template<int> void op_sbc_r();
+void op_sbk();
+void op_sex();
+template<int> void op_sm_r();
+template<int> void op_sms_r();
+template<int> void op_stb_ir();
+void op_stop();
+template<int> void op_stw_ir();
+template<int> void op_sub_i();
+template<int> void op_sub_r();
+void op_swap();
+template<int> void op_to_r();
+template<int> void op_umult_i();
+template<int> void op_umult_r();
+template<int> void op_with_r();
+template<int> void op_xor_i();
+template<int> void op_xor_r();

src/chip/superfx/core/opcode_table.cpp

@@ -0,0 +1,270 @@
+#ifdef SUPERFX_CPP
+
+void SuperFX::initialize_opcode_table() {
+  #define op4(id, name) \
+    op(id+ 0, name< 1>) op(id+ 1, name< 2>) op(id+ 2, name< 3>) op(id+ 3, name< 4>)
+
+  #define op6(id, name) \
+    op(id+ 0, name< 8>) op(id+ 1, name< 9>) op(id+ 2, name<10>) op(id+ 3, name<11>) \
+    op(id+ 4, name<12>) op(id+ 5, name<13>)
+
+  #define op12(id, name) \
+    op(id+ 0, name< 0>) op(id+ 1, name< 1>) op(id+ 2, name< 2>) op(id+ 3, name< 3>) \
+    op(id+ 4, name< 4>) op(id+ 5, name< 5>) op(id+ 6, name< 6>) op(id+ 7, name< 7>) \
+    op(id+ 8, name< 8>) op(id+ 9, name< 9>) op(id+10, name<10>) op(id+11, name<11>)
+
+  #define op15l(id, name) \
+    op(id+ 0, name< 0>) op(id+ 1, name< 1>) op(id+ 2, name< 2>) op(id+ 3, name< 3>) \
+    op(id+ 4, name< 4>) op(id+ 5, name< 5>) op(id+ 6, name< 6>) op(id+ 7, name< 7>) \
+    op(id+ 8, name< 8>) op(id+ 9, name< 9>) op(id+10, name<10>) op(id+11, name<11>) \
+    op(id+12, name<12>) op(id+13, name<13>) op(id+14, name<14>)
+
+  #define op15h(id, name) \
+    op(id+ 0, name< 1>) op(id+ 1, name< 2>) op(id+ 2, name< 3>) op(id+ 3, name< 4>) \
+    op(id+ 4, name< 5>) op(id+ 5, name< 6>) op(id+ 6, name< 7>) op(id+ 7, name< 8>) \
+    op(id+ 8, name< 9>) op(id+ 9, name<10>) op(id+10, name<11>) op(id+11, name<12>) \
+    op(id+12, name<13>) op(id+13, name<14>) op(id+14, name<15>)
+
+  #define op16(id, name) \
+    op(id+ 0, name< 0>) op(id+ 1, name< 1>) op(id+ 2, name< 2>) op(id+ 3, name< 3>) \
+    op(id+ 4, name< 4>) op(id+ 5, name< 5>) op(id+ 6, name< 6>) op(id+ 7, name< 7>) \
+    op(id+ 8, name< 8>) op(id+ 9, name< 9>) op(id+10, name<10>) op(id+11, name<11>) \
+    op(id+12, name<12>) op(id+13, name<13>) op(id+14, name<14>) op(id+15, name<15>)
+
+  //======
+  // ALT0
+  //======
+
+  #define op(id, name) opcode_table[  0 + id] = &SuperFX::op_##name;
+  op   (0x00, stop)
+  op   (0x01, nop)
+  op   (0x02, cache)
+  op   (0x03, lsr)
+  op   (0x04, rol)
+  op   (0x05, bra)
+  op   (0x06, blt)
+  op   (0x07, bge)
+  op   (0x08, bne)
+  op   (0x09, beq)
+  op   (0x0a, bpl)
+  op   (0x0b, bmi)
+  op   (0x0c, bcc)
+  op   (0x0d, bcs)
+  op   (0x0e, bvc)
+  op   (0x0f, bvs)
+  op16 (0x10, to_r)
+  op16 (0x20, with_r)
+  op12 (0x30, stw_ir)
+  op   (0x3c, loop)
+  op   (0x3d, alt1)
+  op   (0x3e, alt2)
+  op   (0x3f, alt3)
+  op12 (0x40, ldw_ir)
+  op   (0x4c, plot)
+  op   (0x4d, swap)
+  op   (0x4e, color)
+  op   (0x4f, not)
+  op16 (0x50, add_r)
+  op16 (0x60, sub_r)
+  op   (0x70, merge)
+  op15h(0x71, and_r)
+  op16 (0x80, mult_r)
+  op   (0x90, sbk)
+  op4  (0x91, link)
+  op   (0x95, sex)
+  op   (0x96, asr)
+  op   (0x97, ror)
+  op6  (0x98, jmp_r)
+  op   (0x9e, lob)
+  op   (0x9f, fmult)
+  op16 (0xa0, ibt_r)
+  op16 (0xb0, from_r)
+  op   (0xc0, hib)
+  op15h(0xc1, or_r)
+  op15l(0xd0, inc_r)
+  op   (0xdf, getc)
+  op15l(0xe0, dec_r)
+  op   (0xef, getb)
+  op16 (0xf0, iwt_r)
+  #undef op
+
+  //======
+  // ALT1
+  //======
+
+  #define op(id, name) opcode_table[256 + id] = &SuperFX::op_##name;
+  op   (0x00, stop)
+  op   (0x01, nop)
+  op   (0x02, cache)
+  op   (0x03, lsr)
+  op   (0x04, rol)
+  op   (0x05, bra)
+  op   (0x06, blt)
+  op   (0x07, bge)
+  op   (0x08, bne)
+  op   (0x09, beq)
+  op   (0x0a, bpl)
+  op   (0x0b, bmi)
+  op   (0x0c, bcc)
+  op   (0x0d, bcs)
+  op   (0x0e, bvc)
+  op   (0x0f, bvs)
+  op16 (0x10, to_r)
+  op16 (0x20, with_r)
+  op12 (0x30, stb_ir)
+  op   (0x3c, loop)
+  op   (0x3d, alt1)
+  op   (0x3e, alt2)
+  op   (0x3f, alt3)
+  op12 (0x40, ldb_ir)
+  op   (0x4c, rpix)
+  op   (0x4d, swap)
+  op   (0x4e, cmode)
+  op   (0x4f, not)
+  op16 (0x50, adc_r)
+  op16 (0x60, sbc_r)
+  op   (0x70, merge)
+  op15h(0x71, bic_r)
+  op16 (0x80, umult_r)
+  op   (0x90, sbk)
+  op4  (0x91, link)
+  op   (0x95, sex)
+  op   (0x96, div2)
+  op   (0x97, ror)
+  op6  (0x98, ljmp_r)
+  op   (0x9e, lob)
+  op   (0x9f, lmult)
+  op16 (0xa0, lms_r)
+  op16 (0xb0, from_r)
+  op   (0xc0, hib)
+  op15h(0xc1, xor_r)
+  op15l(0xd0, inc_r)
+  op   (0xdf, getc)
+  op15l(0xe0, dec_r)
+  op   (0xef, getbh)
+  op16 (0xf0, lm_r)
+  #undef op
+
+  //======
+  // ALT2
+  //======
+
+  #define op(id, name) opcode_table[512 + id] = &SuperFX::op_##name;
+  op   (0x00, stop)
+  op   (0x01, nop)
+  op   (0x02, cache)
+  op   (0x03, lsr)
+  op   (0x04, rol)
+  op   (0x05, bra)
+  op   (0x06, blt)
+  op   (0x07, bge)
+  op   (0x08, bne)
+  op   (0x09, beq)
+  op   (0x0a, bpl)
+  op   (0x0b, bmi)
+  op   (0x0c, bcc)
+  op   (0x0d, bcs)
+  op   (0x0e, bvc)
+  op   (0x0f, bvs)
+  op16 (0x10, to_r)
+  op16 (0x20, with_r)
+  op12 (0x30, stw_ir)
+  op   (0x3c, loop)
+  op   (0x3d, alt1)
+  op   (0x3e, alt2)
+  op   (0x3f, alt3)
+  op12 (0x40, ldw_ir)
+  op   (0x4c, plot)
+  op   (0x4d, swap)
+  op   (0x4e, color)
+  op   (0x4f, not)
+  op16 (0x50, add_i)
+  op16 (0x60, sub_i)
+  op   (0x70, merge)
+  op15h(0x71, and_i)
+  op16 (0x80, mult_i)
+  op   (0x90, sbk)
+  op4  (0x91, link)
+  op   (0x95, sex)
+  op   (0x96, asr)
+  op   (0x97, ror)
+  op6  (0x98, jmp_r)
+  op   (0x9e, lob)
+  op   (0x9f, fmult)
+  op16 (0xa0, sms_r)
+  op16 (0xb0, from_r)
+  op   (0xc0, hib)
+  op15h(0xc1, or_i)
+  op15l(0xd0, inc_r)
+  op   (0xdf, ramb)
+  op15l(0xe0, dec_r)
+  op   (0xef, getbl)
+  op16 (0xf0, sm_r)
+  #undef op
+
+  //======
+  // ALT3
+  //======
+
+  #define op(id, name) opcode_table[768 + id] = &SuperFX::op_##name;
+  op   (0x00, stop)
+  op   (0x01, nop)
+  op   (0x02, cache)
+  op   (0x03, lsr)
+  op   (0x04, rol)
+  op   (0x05, bra)
+  op   (0x06, blt)
+  op   (0x07, bge)
+  op   (0x08, bne)
+  op   (0x09, beq)
+  op   (0x0a, bpl)
+  op   (0x0b, bmi)
+  op   (0x0c, bcc)
+  op   (0x0d, bcs)
+  op   (0x0e, bvc)
+  op   (0x0f, bvs)
+  op16 (0x10, to_r)
+  op16 (0x20, with_r)
+  op12 (0x30, stb_ir)
+  op   (0x3c, loop)
+  op   (0x3d, alt1)
+  op   (0x3e, alt2)
+  op   (0x3f, alt3)
+  op12 (0x40, ldb_ir)
+  op   (0x4c, rpix)
+  op   (0x4d, swap)
+  op   (0x4e, cmode)
+  op   (0x4f, not)
+  op16 (0x50, adc_i)
+  op16 (0x60, cmp_r)
+  op   (0x70, merge)
+  op15h(0x71, bic_i)
+  op16 (0x80, umult_i)
+  op   (0x90, sbk)
+  op4  (0x91, link)
+  op   (0x95, sex)
+  op   (0x96, div2)
+  op   (0x97, ror)
+  op6  (0x98, ljmp_r)
+  op   (0x9e, lob)
+  op   (0x9f, lmult)
+  op16 (0xa0, lms_r)
+  op16 (0xb0, from_r)
+  op   (0xc0, hib)
+  op15h(0xc1, xor_i)
+  op15l(0xd0, inc_r)
+  op   (0xdf, romb)
+  op15l(0xe0, dec_r)
+  op   (0xef, getbs)
+  op16 (0xf0, lm_r)
+  #undef op
+
+  #undef op4
+  #undef op6
+  #undef op12
+  #undef op15l
+  #undef op15h
+  #undef op16
+}
+
+#endif

src/chip/superfx/core/opcodes.cpp

@@ -0,0 +1,661 @@
+#ifdef SUPERFX_CPP
+
+//$00 stop
+void SuperFX::op_stop() {
+  if(regs.cfgr.irq == 0) {
+    regs.sfr.irq = 1;
+    cpu.regs.irq = 1;
+  }
+
+  regs.sfr.g = 0;
+  regs.pipeline = 0x01;
+  regs.reset();
+}
+
+//$01 nop
+void SuperFX::op_nop() {
+  regs.reset();
+}
+
+//$02 cache
+void SuperFX::op_cache() {
+  if(regs.cbr != (regs.r[15] & 0xfff0)) {
+    regs.cbr = regs.r[15] & 0xfff0;
+    cache_flush();
+  }
+  regs.reset();
+}
+
+//$03 lsr
+void SuperFX::op_lsr() {
+  regs.sfr.cy = (regs.sr() & 1);
+  regs.dr() = regs.sr() >> 1;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$04 rol
+void SuperFX::op_rol() {
+  bool carry = (regs.sr() & 0x8000);
+  regs.dr() = (regs.sr() << 1) | regs.sfr.cy;
+  regs.sfr.s  = (regs.dr() & 0x8000);
+  regs.sfr.cy = carry;
+  regs.sfr.z  = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$05 bra e
+void SuperFX::op_bra() {
+  regs.r[15] += (int8)pipe();
+}
+
+//$06 blt e
+void SuperFX::op_blt() {
+  int e = (int8)pipe();
+  if((regs.sfr.s ^ regs.sfr.ov) == 0) regs.r[15] += e;
+}
+
+//$07 bge e
+void SuperFX::op_bge() {
+  int e = (int8)pipe();
+  if((regs.sfr.s ^ regs.sfr.ov) == 1) regs.r[15] += e;
+}
+
+//$08 bne e
+void SuperFX::op_bne() {
+  int e = (int8)pipe();
+  if(regs.sfr.z == 0) regs.r[15] += e;
+}
+
+//$09 beq e
+void SuperFX::op_beq() {
+  int e = (int8)pipe();
+  if(regs.sfr.z == 1) regs.r[15] += e;
+}
+
+//$0a bpl e
+void SuperFX::op_bpl() {
+  int e = (int8)pipe();
+  if(regs.sfr.s == 0) regs.r[15] += e;
+}
+
+//$0b bmi e
+void SuperFX::op_bmi() {
+  int e = (int8)pipe();
+  if(regs.sfr.s == 1) regs.r[15] += e;
+}
+
+//$0c bcc e
+void SuperFX::op_bcc() {
+  int e = (int8)pipe();
+  if(regs.sfr.cy == 0) regs.r[15] += e;
+}
+
+//$0d bcs e
+void SuperFX::op_bcs() {
+  int e = (int8)pipe();
+  if(regs.sfr.cy == 1) regs.r[15] += e;
+}
+
+//$0e bvc e
+void SuperFX::op_bvc() {
+  int e = (int8)pipe();
+  if(regs.sfr.ov == 0) regs.r[15] += e;
+}
+
+//$0f bvs e
+void SuperFX::op_bvs() {
+  int e = (int8)pipe();
+  if(regs.sfr.ov == 1) regs.r[15] += e;
+}
+
+//$10-1f(b0): to rN
+//$10-1f(b1): move rN
+template<int n> void SuperFX::op_to_r() {
+  if(regs.sfr.b == 0) {
+    regs.dreg = &regs.r[n];
+  } else {
+    regs.r[n] = regs.sr();
+    regs.reset();
+  }
+}
+
+//$20-2f: with rN
+template<int n> void SuperFX::op_with_r() {
+  regs.sreg = &regs.r[n];
+  regs.dreg = &regs.r[n];
+  regs.sfr.b = 1;
+}
+
+//$30-3b(alt0): stw (rN)
+template<int n> void SuperFX::op_stw_ir() {
+  regs.ramaddr = regs.r[n];
+  rambuffer_write(regs.ramaddr ^ 0, regs.sr() >> 0);
+  rambuffer_write(regs.ramaddr ^ 1, regs.sr() >> 8);
+  regs.reset();
+}
+
+//$30-3b(alt1): stb (rN)
+template<int n> void SuperFX::op_stb_ir() {
+  regs.ramaddr = regs.r[n];
+  rambuffer_write(regs.ramaddr, regs.sr());
+  regs.reset();
+}
+
+//$3c loop
+void SuperFX::op_loop() {
+  regs.r[12]--;
+  regs.sfr.s = (regs.r[12] & 0x8000);
+  regs.sfr.z = (regs.r[12] == 0);
+  if(!regs.sfr.z) regs.r[15] = regs.r[13];
+  regs.reset();
+}
+
+//$3d alt1
+void SuperFX::op_alt1() {
+  regs.sfr.b = 0;
+  regs.sfr.alt1 = 1;
+}
+
+//$3e alt2
+void SuperFX::op_alt2() {
+  regs.sfr.b = 0;
+  regs.sfr.alt2 = 1;
+}
+
+//$3f alt3
+void SuperFX::op_alt3() {
+  regs.sfr.b = 0;
+  regs.sfr.alt1 = 1;
+  regs.sfr.alt2 = 1;
+}
+
+//$40-4b(alt0): ldw (rN)
+template<int n> void SuperFX::op_ldw_ir() {
+  regs.ramaddr = regs.r[n];
+  uint16_t data;
+  data  = rambuffer_read(regs.ramaddr ^ 0) << 0;
+  data |= rambuffer_read(regs.ramaddr ^ 1) << 8;
+  regs.dr() = data;
+  regs.reset();
+}
+
+//$40-4b(alt1): ldb (rN)
+template<int n> void SuperFX::op_ldb_ir() {
+  regs.ramaddr = regs.r[n];
+  regs.dr() = rambuffer_read(regs.ramaddr);
+  regs.reset();
+}
+
+//$4c(alt0): plot
+void SuperFX::op_plot() {
+  plot(regs.r[1], regs.r[2]);
+  regs.r[1]++;
+  regs.reset();
+}
+
+//$4c(alt1): rpix
+void SuperFX::op_rpix() {
+  regs.dr() = rpix(regs.r[1], regs.r[2]);
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$4d: swap
+void SuperFX::op_swap() {
+  regs.dr() = (regs.sr() >> 8) | (regs.sr() << 8);
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$4e(alt0): color
+void SuperFX::op_color() {
+  regs.colr = color(regs.sr());
+  regs.reset();
+}
+
+//$4e(alt1): cmode
+void SuperFX::op_cmode() {
+  regs.por = regs.sr();
+  regs.reset();
+}
+
+//$4f: not
+void SuperFX::op_not() {
+  regs.dr() = ~regs.sr();
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$50-5f(alt0): add rN
+template<int n> void SuperFX::op_add_r() {
+  int r = regs.sr() + regs.r[n];
+  regs.sfr.ov = ~(regs.sr() ^ regs.r[n]) & (regs.r[n] ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0x10000);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$50-5f(alt1): adc rN
+template<int n> void SuperFX::op_adc_r() {
+  int r = regs.sr() + regs.r[n] + regs.sfr.cy;
+  regs.sfr.ov = ~(regs.sr() ^ regs.r[n]) & (regs.r[n] ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0x10000);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$50-5f(alt2): add #N
+template<int n> void SuperFX::op_add_i() {
+  int r = regs.sr() + n;
+  regs.sfr.ov = ~(regs.sr() ^ n) & (n ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0x10000);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$50-5f(alt3): adc #N
+template<int n> void SuperFX::op_adc_i() {
+  int r = regs.sr() + n + regs.sfr.cy;
+  regs.sfr.ov = ~(regs.sr() ^ n) & (n ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0x10000);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$60-6f(alt0): sub rN
+template<int n> void SuperFX::op_sub_r() {
+  int r = regs.sr() - regs.r[n];
+  regs.sfr.ov = (regs.sr() ^ regs.r[n]) & (regs.sr() ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$60-6f(alt1): sbc rN
+template<int n> void SuperFX::op_sbc_r() {
+  int r = regs.sr() - regs.r[n] - !regs.sfr.cy;
+  regs.sfr.ov = (regs.sr() ^ regs.r[n]) & (regs.sr() ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$60-6f(alt2): sub #N
+template<int n> void SuperFX::op_sub_i() {
+  int r = regs.sr() - n;
+  regs.sfr.ov = (regs.sr() ^ n) & (regs.sr() ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$60-6f(alt3): cmp rN
+template<int n> void SuperFX::op_cmp_r() {
+  int r = regs.sr() - regs.r[n];
+  regs.sfr.ov = (regs.sr() ^ regs.r[n]) & (regs.sr() ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.reset();
+}
+
+//$70: merge
+void SuperFX::op_merge() {
+  regs.dr() = (regs.r[7] & 0xff00) | (regs.r[8] >> 8);
+  regs.sfr.ov = (regs.dr() & 0xc0c0);
+  regs.sfr.s  = (regs.dr() & 0x8080);
+  regs.sfr.cy = (regs.dr() & 0xe0e0);
+  regs.sfr.z  = (regs.dr() & 0xf0f0);
+  regs.reset();
+}
+
+//$71-7f(alt0): and rN
+template<int n> void SuperFX::op_and_r() {
+  regs.dr() = regs.sr() & regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$71-7f(alt1): bic rN
+template<int n> void SuperFX::op_bic_r() {
+  regs.dr() = regs.sr() & ~regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$71-7f(alt2): and #N
+template<int n> void SuperFX::op_and_i() {
+  regs.dr() = regs.sr() & n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$71-7f(alt3): bic #N
+template<int n> void SuperFX::op_bic_i() {
+  regs.dr() = regs.sr() & ~n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$80-8f(alt0): mult rN
+template<int n> void SuperFX::op_mult_r() {
+  regs.dr() = (int8)regs.sr() * (int8)regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+  if(!regs.cfgr.ms0) add_clocks(2);
+}
+
+//$80-8f(alt1): umult rN
+template<int n> void SuperFX::op_umult_r() {
+  regs.dr() = (uint8)regs.sr() * (uint8)regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+  if(!regs.cfgr.ms0) add_clocks(2);
+}
+
+//$80-8f(alt2): mult #N
+template<int n> void SuperFX::op_mult_i() {
+  regs.dr() = (int8)regs.sr() * (int8)n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+  if(!regs.cfgr.ms0) add_clocks(2);
+}
+
+//$80-8f(alt3): umult #N
+template<int n> void SuperFX::op_umult_i() {
+  regs.dr() = (uint8)regs.sr() * (uint8)n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+  if(!regs.cfgr.ms0) add_clocks(2);
+}
+
+//$90: sbk
+void SuperFX::op_sbk() {
+  rambuffer_write(regs.ramaddr ^ 0, regs.sr() >> 0);
+  rambuffer_write(regs.ramaddr ^ 1, regs.sr() >> 8);
+  regs.reset();
+}
+
+//$91-94: link #N
+template<int n> void SuperFX::op_link() {
+  regs.r[11] = regs.r[15] + n;
+  regs.reset();
+}
+
+//$95: sex
+void SuperFX::op_sex() {
+  regs.dr() = (int8)regs.sr();
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$96(alt0): asr
+void SuperFX::op_asr() {
+  regs.sfr.cy = (regs.sr() & 1);
+  regs.dr() = (int16_t)regs.sr() >> 1;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$96(alt1): div2
+void SuperFX::op_div2() {
+  regs.sfr.cy = (regs.sr() & 1);
+  regs.dr() = ((int16_t)regs.sr() >> 1) + ((regs.sr() + 1) >> 16);
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$97: ror
+void SuperFX::op_ror() {
+  bool carry = (regs.sr() & 1);
+  regs.dr() = (regs.sfr.cy << 15) | (regs.sr() >> 1);
+  regs.sfr.s  = (regs.dr() & 0x8000);
+  regs.sfr.cy = carry;
+  regs.sfr.z  = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$98-9d(alt0): jmp rN
+template<int n> void SuperFX::op_jmp_r() {
+  regs.r[15] = regs.r[n];
+  regs.reset();
+}
+
+//$98-9d(alt1): ljmp rN
+template<int n> void SuperFX::op_ljmp_r() {
+  regs.pbr = regs.r[n] & 0x7f;
+  regs.r[15] = regs.sr();
+  regs.cbr = regs.r[15] & 0xfff0;
+  cache_flush();
+  regs.reset();
+}
+
+//$9e: lob
+void SuperFX::op_lob() {
+  regs.dr() = regs.sr() & 0xff;
+  regs.sfr.s = (regs.dr() & 0x80);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$9f(alt0): fmult
+void SuperFX::op_fmult() {
+  uint32_t result = (int16_t)regs.sr() * (int16_t)regs.r[6];
+  regs.dr() = result >> 16;
+  regs.sfr.s  = (regs.dr() & 0x8000);
+  regs.sfr.cy = (result & 0x8000);
+  regs.sfr.z  = (regs.dr() == 0);
+  regs.reset();
+  add_clocks(4 + (regs.cfgr.ms0 << 2));
+}
+
+//$9f(alt1): lmult
+void SuperFX::op_lmult() {
+  uint32_t result = (int16_t)regs.sr() * (int16_t)regs.r[6];
+  regs.r[4] = result;
+  regs.dr() = result >> 16;
+  regs.sfr.s  = (regs.dr() & 0x8000);
+  regs.sfr.cy = (result & 0x8000);
+  regs.sfr.z  = (regs.dr() == 0);
+  regs.reset();
+  add_clocks(4 + (regs.cfgr.ms0 << 2));
+}
+
+//$a0-af(alt0): ibt rN,#pp
+template<int n> void SuperFX::op_ibt_r() {
+  regs.r[n] = (int8)pipe();
+  regs.reset();
+}
+
+//$a0-af(alt1): lms rN,(yy)
+template<int n> void SuperFX::op_lms_r() {
+  regs.ramaddr = pipe() << 1;
+  uint16_t data;
+  data  = rambuffer_read(regs.ramaddr ^ 0) << 0;
+  data |= rambuffer_read(regs.ramaddr ^ 1) << 8;
+  regs.r[n] = data;
+  regs.reset();
+}
+
+//$a0-af(alt2): sms (yy),rN
+template<int n> void SuperFX::op_sms_r() {
+  regs.ramaddr = pipe() << 1;
+  rambuffer_write(regs.ramaddr ^ 0, regs.r[n] >> 0);
+  rambuffer_write(regs.ramaddr ^ 1, regs.r[n] >> 8);
+  regs.reset();
+}
+
+//$b0-bf(b0): from rN
+//$b0-bf(b1): moves rN
+template<int n> void SuperFX::op_from_r() {
+  if(regs.sfr.b == 0) {
+    regs.sreg = &regs.r[n];
+  } else {
+    regs.dr() = regs.r[n];
+    regs.sfr.ov = (regs.dr() & 0x80);
+    regs.sfr.s  = (regs.dr() & 0x8000);
+    regs.sfr.z  = (regs.dr() == 0);
+    regs.reset();
+  }
+}
+
+//$c0: hib
+void SuperFX::op_hib() {
+  regs.dr() = regs.sr() >> 8;
+  regs.sfr.s = (regs.dr() & 0x80);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$c1-cf(alt0): or rN
+template<int n> void SuperFX::op_or_r() {
+  regs.dr() = regs.sr() | regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$c1-cf(alt1): xor rN
+template<int n> void SuperFX::op_xor_r() {
+  regs.dr() = regs.sr() ^ regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$c1-cf(alt2): or #N
+template<int n> void SuperFX::op_or_i() {
+  regs.dr() = regs.sr() | n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$c1-cf(alt3): xor #N
+template<int n> void SuperFX::op_xor_i() {
+  regs.dr() = regs.sr() ^ n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$d0-de: inc rN
+template<int n> void SuperFX::op_inc_r() {
+  regs.r[n]++;
+  regs.sfr.s = (regs.r[n] & 0x8000);
+  regs.sfr.z = (regs.r[n] == 0);
+  regs.reset();
+}
+
+//$df(alt0): getc
+void SuperFX::op_getc() {
+  regs.colr = color(rombuffer_read());
+  regs.reset();
+}
+
+//$df(alt2): ramb
+void SuperFX::op_ramb() {
+  rambuffer_sync();
+  regs.rambr = regs.sr();
+  regs.reset();
+}
+
+//$df(alt3): romb
+void SuperFX::op_romb() {
+  rombuffer_sync();
+  regs.rombr = regs.sr() & 0x7f;
+  regs.reset();
+}
+
+//$e0-ee: dec rN
+template<int n> void SuperFX::op_dec_r() {
+  regs.r[n]--;
+  regs.sfr.s = (regs.r[n] & 0x8000);
+  regs.sfr.z = (regs.r[n] == 0);
+  regs.reset();
+}
+
+//$ef(alt0): getb
+void SuperFX::op_getb() {
+  regs.dr() = rombuffer_read();
+  regs.reset();
+}
+
+//$ef(alt1): getbh
+void SuperFX::op_getbh() {
+  regs.dr() = (rombuffer_read() << 8) | (regs.sr() & 0x00ff);
+  regs.reset();
+}
+
+//$ef(alt2): getbl
+void SuperFX::op_getbl() {
+  regs.dr() = (regs.sr() & 0xff00) | (rombuffer_read() << 0);
+  regs.reset();
+}
+
+//$ef(alt3): getbs
+void SuperFX::op_getbs() {
+  regs.dr() = (int8)rombuffer_read();
+  regs.reset();
+}
+
+//$f0-ff(alt0): iwt rN,#xx
+template<int n> void SuperFX::op_iwt_r() {
+  uint16_t data;
+  data  = pipe() << 0;
+  data |= pipe() << 8;
+  regs.r[n] = data;
+  regs.reset();
+}
+
+//$f0-ff(alt1): lm rN,(xx)
+template<int n> void SuperFX::op_lm_r() {
+  regs.ramaddr  = pipe() << 0;
+  regs.ramaddr |= pipe() << 8;
+  uint16_t data;
+  data  = rambuffer_read(regs.ramaddr ^ 0) << 0;
+  data |= rambuffer_read(regs.ramaddr ^ 1) << 8;
+  regs.r[n] = data;
+  regs.reset();
+}
+
+//$f0-ff(alt2): sm (xx),rN
+template<int n> void SuperFX::op_sm_r() {
+  regs.ramaddr  = pipe() << 0;
+  regs.ramaddr |= pipe() << 8;
+  rambuffer_write(regs.ramaddr ^ 0, regs.r[n] >> 0);
+  rambuffer_write(regs.ramaddr ^ 1, regs.r[n] >> 8);
+  regs.reset();
+}
+
+#endif

src/chip/superfx/core/registers.hpp

@@ -0,0 +1,175 @@
+//accepts a callback binding so r14 writes can trigger ROM buffering transparently
+struct reg16_t : noncopyable {
+  uint16 data;
+  function<void (uint16)> on_modify;
+
+  inline operator unsigned() const { return data; }
+  inline uint16 assign(uint16 i) {
+    if(on_modify) on_modify(i);
+    else data = i;
+    return data;
+  }
+
+  inline unsigned operator++() { return assign(data + 1); }
+  inline unsigned operator--() { return assign(data - 1); }
+  inline unsigned operator++(int) { unsigned r = data; assign(data + 1); return r; }
+  inline unsigned operator--(int) { unsigned r = data; assign(data - 1); return r; }
+  inline unsigned operator   = (unsigned i) { return assign(i); }
+  inline unsigned operator  |= (unsigned i) { return assign(data | i); }
+  inline unsigned operator  ^= (unsigned i) { return assign(data ^ i); }
+  inline unsigned operator  &= (unsigned i) { return assign(data & i); }
+  inline unsigned operator <<= (unsigned i) { return assign(data << i); }
+  inline unsigned operator >>= (unsigned i) { return assign(data >> i); }
+  inline unsigned operator  += (unsigned i) { return assign(data + i); }
+  inline unsigned operator  -= (unsigned i) { return assign(data - i); }
+  inline unsigned operator  *= (unsigned i) { return assign(data * i); }
+  inline unsigned operator  /= (unsigned i) { return assign(data / i); }
+  inline unsigned operator  %= (unsigned i) { return assign(data % i); }
+
+  inline unsigned operator   = (const reg16_t& i) { return assign(i); }
+
+  reg16_t() : data(0) {}
+};
+
+struct sfr_t {
+  bool irq;   //interrupt flag
+  bool b;     //WITH flag
+  bool ih;    //immediate higher 8-bit flag
+  bool il;    //immediate lower 8-bit flag
+  bool alt2;  //ALT2 mode
+  bool alt1;  //ALT2 instruction mode
+  bool r;     //ROM r14 read flag
+  bool g;     //GO flag
+  bool ov;    //overflow flag
+  bool s;     //sign flag
+  bool cy;    //carry flag
+  bool z;     //zero flag
+
+  operator unsigned() const {
+    return (irq << 15) | (b << 12) | (ih << 11) | (il << 10) | (alt2 << 9) | (alt1 << 8)
+         | (r << 6) | (g << 5) | (ov << 4) | (s << 3) | (cy << 2) | (z << 1);
+  }
+
+  sfr_t& operator=(uint16_t data) {
+    irq  = data & 0x8000;
+    b    = data & 0x1000;
+    ih   = data & 0x0800;
+    il   = data & 0x0400;
+    alt2 = data & 0x0200;
+    alt1 = data & 0x0100;
+    r    = data & 0x0040;
+    g    = data & 0x0020;
+    ov   = data & 0x0010;
+    s    = data & 0x0008;
+    cy   = data & 0x0004;
+    z    = data & 0x0002;
+    return *this;
+  }
+};
+
+struct scmr_t {
+  unsigned ht;
+  bool ron;
+  bool ran;
+  unsigned md;
+
+  operator unsigned() const {
+    return ((ht >> 1) << 5) | (ron << 4) | (ran << 3) | ((ht & 1) << 2) | (md);
+  }
+
+  scmr_t& operator=(uint8 data) {
+    ht  = (bool)(data & 0x20) << 1;
+    ht |= (bool)(data & 0x04) << 0;
+    ron = data & 0x10;
+    ran = data & 0x08;
+    md  = data & 0x03;
+    return *this;
+  }
+};
+
+struct por_t {
+  bool obj;
+  bool freezehigh;
+  bool highnibble;
+  bool dither;
+  bool transparent;
+
+  operator unsigned() const {
+    return (obj << 4) | (freezehigh << 3) | (highnibble << 2) | (dither << 1) | (transparent);
+  }
+
+  por_t& operator=(uint8 data) {
+    obj         = data & 0x10;
+    freezehigh  = data & 0x08;
+    highnibble  = data & 0x04;
+    dither      = data & 0x02;
+    transparent = data & 0x01;
+    return *this;
+  }
+};
+
+struct cfgr_t {
+  bool irq;
+  bool ms0;
+
+  operator unsigned() const {
+    return (irq << 7) | (ms0 << 5);
+  }
+
+  cfgr_t& operator=(uint8 data) {
+    irq = data & 0x80;
+    ms0 = data & 0x20;
+    return *this;
+  }
+};
+
+struct regs_t {
+  uint8 pipeline;
+  uint16 ramaddr;
+
+  reg16_t r[16];    //general purpose registers
+  sfr_t sfr;        //status flag register
+  uint8 pbr;        //program bank register
+  uint8 rombr;      //game pack ROM bank register
+  bool rambr;       //game pack RAM bank register
+  uint16 cbr;       //cache base register
+  uint8 scbr;       //screen base register
+  scmr_t scmr;      //screen mode register
+  uint8 colr;       //color register
+  por_t por;        //plot option register
+  bool bramr;       //back-up RAM register
+  uint8 vcr;        //version code register
+  cfgr_t cfgr;      //config register
+  bool clsr;        //clock select register
+
+  unsigned romcl;   //clock ticks until romdr is valid
+  uint8 romdr;      //ROM buffer data register
+
+  unsigned ramcl;   //clock ticks until ramdr is valid
+  uint16 ramar;     //RAM buffer address register
+  uint8 ramdr;      //RAM buffer data register
+
+  reg16_t *sreg, *dreg;
+  reg16_t& sr() { return *sreg; }  //source register (from)
+  reg16_t& dr() { return *dreg; }  //destination register (to)
+
+  void reset() {
+    sfr.b    = 0;
+    sfr.alt1 = 0;
+    sfr.alt2 = 0;
+
+    sreg = &r[0];
+    dreg = &r[0];
+  }
+} regs;
+
+struct cache_t {
+  uint8 buffer[512];
+  bool valid[32];
+} cache;
+
+struct pixelcache_t {
+  uint16 offset;
+  uint8 bitpend;
+  uint8 data[8];
+} pixelcache[2];

src/chip/superfx/disasm/disasm.cpp

@@ -0,0 +1,275 @@
+void SuperFX::disassemble_opcode(char *output) {
+  *output = 0;
+
+  if(!regs.sfr.alt2) {
+    if(!regs.sfr.alt1) {
+      disassemble_alt0(output);
+    } else {
+      disassemble_alt1(output);
+    }
+  } else {
+    if(!regs.sfr.alt1) {
+      disassemble_alt2(output);
+    } else {
+      disassemble_alt3(output);
+    }
+  }
+
+  unsigned length = strlen(output);
+  while(length++ < 20) strcat(output, " ");
+}
+
+#define case4(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3
+#define case6(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5
+#define case12(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
+  case id+ 8: case id+ 9: case id+10: case id+11
+#define case15(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
+  case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14
+#define case16(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
+  case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14: case id+15
+
+#define op0 regs.pipeline
+#define op1 superfxbus.read((regs.pbr << 16) + regs.r[15] + 0)
+#define op2 superfxbus.read((regs.pbr << 16) + regs.r[15] + 1)
+
+void SuperFX::disassemble_alt0(char *output) {
+  char t[256] = "";
+  switch(op0) {
+    case  (0x00): sprintf(t, "stop"); break;
+    case  (0x01): sprintf(t, "nop"); break;
+    case  (0x02): sprintf(t, "cache"); break;
+    case  (0x03): sprintf(t, "lsr"); break;
+    case  (0x04): sprintf(t, "rol"); break;
+    case  (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
+    case  (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
+    case  (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
+    case  (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
+    case  (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
+    case  (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
+    case  (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
+    case  (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
+    case  (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
+    case  (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
+    case  (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
+    case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
+    case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
+    case12(0x30): sprintf(t, "stw (r%u)", op0 & 15); break;
+    case  (0x3c): sprintf(t, "loop"); break;
+    case  (0x3d): sprintf(t, "alt1"); break;
+    case  (0x3e): sprintf(t, "alt2"); break;
+    case  (0x3f): sprintf(t, "alt3"); break;
+    case12(0x40): sprintf(t, "ldw (r%u)", op0 & 15); break;
+    case  (0x4c): sprintf(t, "plot"); break;
+    case  (0x4d): sprintf(t, "swap"); break;
+    case  (0x4e): sprintf(t, "color"); break;
+    case  (0x4f): sprintf(t, "not"); break;
+    case16(0x50): sprintf(t, "add r%u", op0 & 15); break;
+    case16(0x60): sprintf(t, "sub r%u", op0 & 15); break;
+    case  (0x70): sprintf(t, "merge"); break;
+    case15(0x71): sprintf(t, "and r%u", op0 & 15); break;
+    case16(0x80): sprintf(t, "mult r%u", op0 & 15); break;
+    case  (0x90): sprintf(t, "sbk"); break;
+    case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
+    case  (0x95): sprintf(t, "sex"); break;
+    case  (0x96): sprintf(t, "asr"); break;
+    case  (0x97): sprintf(t, "ror"); break;
+    case6 (0x98): sprintf(t, "jmp r%u", op0 & 15); break;
+    case  (0x9e): sprintf(t, "lob"); break;
+    case  (0x9f): sprintf(t, "fmult"); break;
+    case16(0xa0): sprintf(t, "ibt r%u,#$%.2x", op0 & 15, op1); break;
+    case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
+    case  (0xc0): sprintf(t, "hib");
+    case15(0xc1): sprintf(t, "or r%u", op0 & 15); break;
+    case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
+    case  (0xdf): sprintf(t, "getc"); break;
+    case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
+    case  (0xef): sprintf(t, "getb"); break;
+    case16(0xf0): sprintf(t, "iwt r%u,#$%.2x%.2x", op0 & 15, op2, op1); break;
+  }
+  strcat(output, t);
+}
+
+void SuperFX::disassemble_alt1(char *output) {
+  char t[256] = "";
+  switch(op0) {
+    case  (0x00): sprintf(t, "stop"); break;
+    case  (0x01): sprintf(t, "nop"); break;
+    case  (0x02): sprintf(t, "cache"); break;
+    case  (0x03): sprintf(t, "lsr"); break;
+    case  (0x04): sprintf(t, "rol"); break;
+    case  (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
+    case  (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
+    case  (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
+    case  (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
+    case  (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
+    case  (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
+    case  (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
+    case  (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
+    case  (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
+    case  (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
+    case  (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
+    case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
+    case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
+    case12(0x30): sprintf(t, "stb (r%u)", op0 & 15); break;
+    case  (0x3c): sprintf(t, "loop"); break;
+    case  (0x3d): sprintf(t, "alt1"); break;
+    case  (0x3e): sprintf(t, "alt2"); break;
+    case  (0x3f): sprintf(t, "alt3"); break;
+    case12(0x40): sprintf(t, "ldb (r%u)", op0 & 15); break;
+    case  (0x4c): sprintf(t, "rpix"); break;
+    case  (0x4d): sprintf(t, "swap"); break;
+    case  (0x4e): sprintf(t, "cmode"); break;
+    case  (0x4f): sprintf(t, "not"); break;
+    case16(0x50): sprintf(t, "adc r%u", op0 & 15); break;
+    case16(0x60): sprintf(t, "sbc r%u", op0 & 15); break;
+    case  (0x70): sprintf(t, "merge"); break;
+    case15(0x71): sprintf(t, "bic r%u", op0 & 15); break;
+    case16(0x80): sprintf(t, "umult r%u", op0 & 15); break;
+    case  (0x90): sprintf(t, "sbk"); break;
+    case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
+    case  (0x95): sprintf(t, "sex"); break;
+    case  (0x96): sprintf(t, "div2"); break;
+    case  (0x97): sprintf(t, "ror"); break;
+    case6 (0x98): sprintf(t, "ljmp r%u", op0 & 15); break;
+    case  (0x9e): sprintf(t, "lob"); break;
+    case  (0x9f): sprintf(t, "lmult"); break;
+    case16(0xa0): sprintf(t, "lms r%u,(#$%.4x)", op0 & 15, op1 << 1); break;
+    case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
+    case  (0xc0): sprintf(t, "hib"); break;
+    case15(0xc1): sprintf(t, "xor r%u", op0 & 15); break;
+    case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
+    case  (0xdf): sprintf(t, "getc"); break;
+    case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
+    case  (0xef): sprintf(t, "getbh"); break;
+    case16(0xf0): sprintf(t, "lm r%u", op0 & 15); break;
+  }
+  strcat(output, t);
+}
+
+void SuperFX::disassemble_alt2(char *output) {
+  char t[256] = "";
+  switch(op0) {
+    case  (0x00): sprintf(t, "stop"); break;
+    case  (0x01): sprintf(t, "nop"); break;
+    case  (0x02): sprintf(t, "cache"); break;
+    case  (0x03): sprintf(t, "lsr"); break;
+    case  (0x04): sprintf(t, "rol"); break;
+    case  (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
+    case  (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
+    case  (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
+    case  (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
+    case  (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
+    case  (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
+    case  (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
+    case  (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
+    case  (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
+    case  (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
+    case  (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
+    case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
+    case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
+    case12(0x30): sprintf(t, "stw (r%u)", op0 & 15); break;
+    case  (0x3c): sprintf(t, "loop"); break;
+    case  (0x3d): sprintf(t, "alt1"); break;
+    case  (0x3e): sprintf(t, "alt2"); break;
+    case  (0x3f): sprintf(t, "alt3"); break;
+    case12(0x40): sprintf(t, "ldw (r%u)", op0 & 15); break;
+    case  (0x4c): sprintf(t, "plot"); break;
+    case  (0x4d): sprintf(t, "swap"); break;
+    case  (0x4e): sprintf(t, "color"); break;
+    case  (0x4f): sprintf(t, "not"); break;
+    case16(0x50): sprintf(t, "add #%u", op0 & 15); break;
+    case16(0x60): sprintf(t, "sub #%u", op0 & 15); break;
+    case  (0x70): sprintf(t, "merge"); break;
+    case15(0x71): sprintf(t, "and #%u", op0 & 15); break;
+    case16(0x80): sprintf(t, "mult #%u", op0 & 15); break;
+    case  (0x90): sprintf(t, "sbk"); break;
+    case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
+    case  (0x95): sprintf(t, "sex"); break;
+    case  (0x96): sprintf(t, "asr"); break;
+    case  (0x97): sprintf(t, "ror"); break;
+    case6 (0x98): sprintf(t, "jmp r%u", op0 & 15); break;
+    case  (0x9e): sprintf(t, "lob"); break;
+    case  (0x9f): sprintf(t, "fmult"); break;
+    case16(0xa0): sprintf(t, "sms r%u,(#$%.4x)", op0 & 15, op1 << 1); break;
+    case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
+    case  (0xc0): sprintf(t, "hib"); break;
+    case15(0xc1): sprintf(t, "or #%u", op0 & 15); break;
+    case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
+    case  (0xdf): sprintf(t, "ramb"); break;
+    case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
+    case  (0xef): sprintf(t, "getbl"); break;
+    case16(0xf0): sprintf(t, "sm r%u", op0 & 15); break;
+  }
+  strcat(output, t);
+}
+
+void SuperFX::disassemble_alt3(char *output) {
+  char t[256] = "";
+  switch(op0) {
+    case  (0x00): sprintf(t, "stop"); break;
+    case  (0x01): sprintf(t, "nop"); break;
+    case  (0x02): sprintf(t, "cache"); break;
+    case  (0x03): sprintf(t, "lsr"); break;
+    case  (0x04): sprintf(t, "rol"); break;
+    case  (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
+    case  (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
+    case  (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
+    case  (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
+    case  (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
+    case  (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
+    case  (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
+    case  (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
+    case  (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
+    case  (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
+    case  (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
+    case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
+    case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
+    case12(0x30): sprintf(t, "stb (r%u)", op0 & 15); break;
+    case  (0x3c): sprintf(t, "loop"); break;
+    case  (0x3d): sprintf(t, "alt1"); break;
+    case  (0x3e): sprintf(t, "alt2"); break;
+    case  (0x3f): sprintf(t, "alt3"); break;
+    case12(0x40): sprintf(t, "ldb (r%u)", op0 & 15); break;
+    case  (0x4c): sprintf(t, "rpix"); break;
+    case  (0x4d): sprintf(t, "swap"); break;
+    case  (0x4e): sprintf(t, "cmode"); break;
+    case  (0x4f): sprintf(t, "not"); break;
+    case16(0x50): sprintf(t, "adc #%u", op0 & 15); break;
+    case16(0x60): sprintf(t, "cmp r%u", op0 & 15); break;
+    case  (0x70): sprintf(t, "merge"); break;
+    case15(0x71): sprintf(t, "bic #%u", op0 & 15); break;
+    case16(0x80): sprintf(t, "umult #%u", op0 & 15); break;
+    case  (0x90): sprintf(t, "sbk"); break;
+    case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
+    case  (0x95): sprintf(t, "sex"); break;
+    case  (0x96): sprintf(t, "div2"); break;
+    case  (0x97): sprintf(t, "ror"); break;
+    case6 (0x98): sprintf(t, "ljmp r%u", op0 & 15); break;
+    case  (0x9e): sprintf(t, "lob"); break;
+    case  (0x9f): sprintf(t, "lmult"); break;
+    case16(0xa0): sprintf(t, "lms r%u", op0 & 15); break;
+    case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
+    case  (0xc0): sprintf(t, "hib"); break;
+    case15(0xc1): sprintf(t, "xor #%u", op0 & 15); break;
+    case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
+    case  (0xdf): sprintf(t, "romb"); break;
+    case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
+    case  (0xef): sprintf(t, "getbs"); break;
+    case16(0xf0): sprintf(t, "lm r%u", op0 & 15); break;
+  }
+  strcat(output, t);
+}
+
+#undef case4
+#undef case6
+#undef case12
+#undef case15
+#undef case16
+#undef op0
+#undef op1
+#undef op2

src/chip/superfx/disasm/disasm.hpp

@@ -0,0 +1,5 @@
+void disassemble_opcode(char *output);
+void disassemble_alt0(char *output);
+void disassemble_alt1(char *output);
+void disassemble_alt2(char *output);
+void disassemble_alt3(char *output);