Update to bsnes v047 release.

The most notable feature for this release is the addition of SuperFX support. This enables an additional eight commercial games, and two unreleased betas, to run with full support. Most notably of these would be Super Mario World 2: Yoshi's Island and Starfox. Though timing is not quite perfect just yet, there should be no known issues with any titles at the time of this release. That means there should only be two official, commercially-released titles that are not compatible with bsnes at this time: Quick-move Shogi Match with Nidan Rank-holder Morita 1 and 2 (using the ST011 and ST018 co-processors, respectively.)
SuperFX support was the work of many people. GIGO was a great help by providing the source code to his SuperFX emulator (for reference; the implementation in bsnes is my own design), _Demo_ was very helpful in getting Starfox to work properly, and Jonas Quinn provided roughly a half-dozen very important bug fixes that affected nearly every SuperFX game. Without them, this release would not be possible. So please do thank them if you appreciate SuperFX support in bsnes.
Please note that SuperFX emulation is very demanding. I hate to have to repeat this, but once again: bsnes is a reference emulator. It exists to better understand the SNES hardware. It is written in such a manner as to be friendly to other developers (both emulator authors and game programmers), and the findings are meant to help improve other emulators. As far as I know, bsnes is the first emulator to fully support all SuperFX caching mechanisms (instruction cache, both pixel caches, ROM and RAM buffering caches, ...); as well as many other obscure features, such as full support for ROM / RAM access toggling between the SNES and SuperFX CPUs, and multiplier overhead timing. By emulating these, I was able to discover what additional components are needed to emulate Dirt Racer and Power Slide, two titles that no emulator has yet been able to run (they aren't very good games, you weren't missing much.) It should be possible to backport these fixes to faster emulators now.
That said, with a Core 2 Duo E8400 @ 3GHz, on average I get ~100fps in Super Mario World 2, ~95fps in Starfox and ~85fps in Doom. Compare this to ~165fps in Zelda 3, a game that does not use the SuperFX chip. My binary releases also target 32-bit x86 architecture. For those capable of building 64-bit binaries, especially Linux users, that should provide an additional ~10% speedup. Be sure to profile the application if you build it yourself.
Lastly on the SuperFX front, note that Starfox 2 is fully playable, but that most images floating around have corrupted headers. I do not attempt to repair bad headers, so these images will not work. Please either use NSRT on the Japanese version, or use Gideon Zhi's English fan translation patch, if you are having trouble running this title.
With that out the way, a few other improvements have been made to this release: xinput1_3.dll is no longer required for the Windows port (though you will need it if you want to use an Xbox 360 controller), the video drivers in ruby now allocate the smallest texture size possible for blitting video, and the code has been updated with preliminary compilation support for Mac OS X. Note that I will not be releasing binaries for this: it is primarily meant for developers and for porting my other libraries to the platform. Richard Bannister maintains a much better OS X port with full EE support and a native Apple GUI that follows their interface guidelines much better than a Qt port ever could. He has also synced the Mac port with this release. You can find a link to that in the bsnes download section.

license.txt

@@ -1,84 +0,0 @@
-bsnes (TM) Reference License
-Copyright (C) 2004 - 2008 byuu
-All rights reserved
-
-1. Definitions
-
-The terms "reproduce", "reproduction", "distribute" and "distribution" have the
-same meaning here as under U.S. copyright law.
-
-"The software" means this software package as a whole, including, but not
-limited to, this license, binaries, source code, documentation, and data.
-
-"You" means the licensee of the software.
-
-"The licensor" means the copyright holder of the software, byuu.
-
-2. Grant of Rights
-
-Subject to the terms of this license, the licensor grants you a
-non-transferable, non-exclusive, worldwide, royalty-free copyright license to
-reproduce the software for non-commercial use only, provided the software
-remains unmodified, and there is no charge for the software itself, its' use,
-nor for the medium upon which the software is distributed. The reproduction of
-modified or derivative works of the software is strictly prohibited, except when
-transmitted solely to the licensor.
-
-3. Limitations
-
-This license does not grant you any rights to use the licensor's name, logo or
-trademarks.
-
-The software is provided "as is", and any express or implied warranties,
-including, but not limited to, the implied warranties of merchantability and
-fitness for a particular purpose are disclaimed. In no event shall the licensor
-be liable for any direct, indirect, incidental, special, exemplary, or
-consequential damages (including, but not limited to, procurement of substitute
-goods or services; loss of use, data, or profits; or business interruption)
-however caused and on any theory of liability, whether in contract, strict
-liability, or tort (including negligence or otherwise) arising in any way out of
-the use of the software, even if advised of the possibility of such damage.
-
-In the event that this license is determined to be invalid or unenforceable, the
-Grant of Rights will become null and void, and no rights shall be granted to the
-licensee, within the scope of U.S. copyright law.
-
-4. Exemptions
-
-The software includes the work of other copyright holders, which is licensed
-under different agreements, and exempt from this license. Below is a complete
-list of all such software, and their respective copyright holders and licenses.
-Further, respective source code files are labeled with their correct licensing
-information in the header. The lack of such a header indicates said file falls
-under the bsnes license.
-
-HQ2x filter, author: MaxST, license: LGPL
-JMA decompressor, author: NSRT Team, license: GPL*
-NTSC filter, author: blargg, license: LGPL
-zlib decompressor, license: zlib license
-
-(* bsnes has received an exemption from the copyright holder to use this work.)
-
-The software also includes works which have been released to the public domain,
-which are not bound to any licensing agreements. Below is a complete list of all
-such software.
-
-libco, author: byuu
-S-DD1 decompressor, author: Andreas Naive
-SPC7110 decompressor, author: neviksti
-
-Any software listed above as exemptions may be relicensed individually from
-bsnes under their respective terms. However, no bsnes licensed portions can be
-combined with such a derivative work.
-
-The software also includes the work of other copyright holders, which is
-licensed under the terms of the bsnes license, with permission to do so from the
-respective authors. Below is a complete list of all such software.
-
-Cx4 emu, authors: anomie, Overload, zsKnight, Nach
-DSP-1 emu, authors: Overload, John Weidman, Neviksti, Andreas Naive
-DSP-2 emu, author: Overload
-DSP-3 emu, authors: John Weidman, Kris Bleakley, Lancer, z80 gaiden
-DSP-4 emu, authors: Dreamer Nom, John Weidman, Kris Bleakley, Nach, z80 gaiden
-S-DSP emu, author: blargg
-ST-010 emu, authors: John Weidman, Matthew Kendora, Overload, Feather

readme.txt

@@ -1,108 +0,0 @@
-bsnes
-Version: 0.037
-Author: byuu
-
-========
-General:
-========
-
-bsnes is a Super Nintendo / Super Famicom emulator that began on
-October 14th, 2004.
-
-The latest version can be downloaded from:
-http://byuu.org/
-
-Please see license.txt for important licensing information.
-
-==============
-Configuration:
-==============
-
-bsnes has two configuration files: bsnes.cfg, for program settings; and
-locale.cfg, for localization.
-
-For each file, bsnes will start by looking inside the same folder where the
-bsnes executable is located. If said file is not found, it will then check your
-user profile folder. On Windows, this is located at "%APPDATA%/.bsnes". On all
-other operating systems, this is located at "~/.bsnes". If said file is still
-not found, it will automatically be created in your user profile folder.
-
-If you wish to use bsnes in single-user mode, be sure that both files exist
-inside the same folder as the bsnes executable. If they do not, you can simply
-create new blank files and bsnes will use them in the future.
-
-If you wish to use bsnes in multi-user mode, simply delete these two files from
-the bsnes executable directory if they exist.
-
-If you wish to have multiple configuration profiles for the same user, you will
-need to make copies of the bsnes executable, and use each one in single-user
-mode.
-
-====================
-Known Limitation(s):
-====================
-
-S-CPU
-- Multiply / divide register delays not implemented
-- "Glitch" when reading joypad registers during auto polling not implemented
-
-S-PPU
-- Uses scanline-based renderer. This is very inaccurate, but few (if any)
-  games rely on mid-scanline writes to function correctly
-- Does not support FirstSprite+Y priority
-- OAM / CGRAM accesses during active display not supported correctly
-- RTO flags are not calculated on frames that are skipped when frameskipping
-  is enabled. This provides a major speedup, however it will cause in issues
-  in games that test these flags, eg the SNES Test Program Electronics Test.
-  Turning frameskipping off will allow RTO flag calculation on every frame
-
-Hardware Bugs
-- S-CPU.r1 HDMA crashing bug not emulated
-- S-CPU<>S-SMP communication bus conflicts not emulated
-
-===============
-Known Issue(s):
-===============
-
-On Windows, attempting to load a ZIP, GZ or JMA compressed archive with
-non-ANSI characters in the filename will fail. This is because Windows
-requires UTF-16 encoding, but these libraries only work with UTF-8.
-Note that loading uncompressed images (SMC, SFC, etc) with non-ANSI characters
-works properly on all platforms.
-
-=====================
-Unsupported Hardware:
-=====================
-
-SA-1
-Coprocessor used in many popular games, including:
-- Dragon Ball Z Hyper Dimension
-- Kirby Super Star
-- Kirby's Dreamland 3
-- Marvelous
-- SD Gundam G-NEXT
-- Super Mario RPG
-
-Super FX
-Coprocessor used in many popular games, including:
-- Doom
-- Star Fox
-- Star Fox 2 (unreleased beta)
-- Super Mario World 2: Yoshi's Island
-
-ST-011
-SETA DSP used by Quick-move Shogi Match with Nidan Rank-holder Morita
-
-ST-018
-SETA RISC CPU used by Quick-move Shogi Match with Nidan Rank-holder Morita 2
-
-Super Gameboy
-Cartridge passthrough used for playing Gameboy games
-
-=============
-Contributors:
-=============
-
-Andreas Naive, anomie, blargg, DMV27, FitzRoy, GIGO, Jonas Quinn, kode54, krom,
-Matthew Callis, mudlord, Nach, neviksti, Overload, RedDwarf, Richard Bannister,
-tetsuo55, TRAC, zones

src/Makefile

@@ -1,55 +1,53 @@
-include lib/nall/Makefile.string
-prefix = /usr/local
+include lib/nall/Makefile
+include lib/nall/Makefile-qt
+ui = ui_qt
 
 ################
 ### compiler ###
 ################
 
-ifneq ($(findstring gcc,$(compiler)),) # GCC family
-  flags = -O3 -fomit-frame-pointer -Ilib
-  c = $(compiler) $(flags)
-  cpp = $(subst cc,++,$(compiler)) $(flags)
-  obj = o
-  rule = -c $< -o $@
-  link = -s
-  mkbin = -o$1
-  mkdef = -D$1
-  mklib = -l$1
-else ifeq ($(compiler),cl) # Visual C++
-  flags = /nologo /wd4355 /wd4996 /O2 /EHsc /Ilib
-  c = cl $(flags)
-  cpp = cl $(flags)
-  obj = obj
-  rule = /c $< /Fo$@
-  link = /link
-  mkbin = /Fe$1
-  mkdef = /D$1
-  mklib = $1.lib
-else
-  unknown_compiler: help;
-endif
+c     := $(compiler)
+cpp   := $(subst cc,++,$(compiler))
+flags := -O3 -fomit-frame-pointer -Ilib
+link  :=
 
-##########
-### os ###
-##########
+# profile-guided instrumentation:
+# flags += -fprofile-generate
+# link += -lgcov
 
-ifeq ($(platform),x) # X11
-  ruby = video.glx video.xv video.sdl audio.openal audio.oss audio.alsa audio.ao input.sdl input.x
-  link += `pkg-config --libs gtk+-2.0`
-  link += $(call mklib,Xtst)
-  delete = rm -f $1
-else ifeq ($(platform),win) # Windows
-  ruby = video.direct3d video.wgl video.directdraw video.gdi audio.directsound input.directinput
-  link += $(if $(findstring mingw,$(compiler)),-mwindows)
-  link += $(call mklib,uuid)
-  link += $(call mklib,kernel32)
-  link += $(call mklib,user32)
-  link += $(call mklib,gdi32)
-  link += $(call mklib,shell32)
-  link += $(call mklib,winmm)
-  link += $(call mklib,comdlg32)
-  link += $(call mklib,comctl32)
-  delete = $(if $(findstring i586-mingw-gcc,$(compiler)),rm -f $1,del $(subst /,\,$1))
+# profile-guided optimization:
+# flags += -fprofile-use
+
+################
+### platform ###
+################
+
+ifeq ($(platform),x)
+  link += -s
+
+  ruby := video.glx video.xv video.sdl video.qtimage
+  ruby += audio.alsa audio.openal audio.oss audio.pulseaudio audio.ao
+  ruby += input.sdl input.x
+
+  link += $(if $(findstring audio.openal,$(ruby)),-lopenal)
+else ifeq ($(platform),osx)
+  ruby := video.qtimage
+  ruby += audio.openal
+  ruby += input.carbon
+
+  link += $(if $(findstring audio.openal,$(ruby)),-framework OpenAL)
+else ifeq ($(platform),win)
+  link += -mwindows
+# link += -mconsole
+  link += -s -luuid -lkernel32 -luser32 -lgdi32 -lshell32
+  # statically link Qt for Windows build
+  link += -enable-stdcall-fixup -Wl,-enable-auto-import -Wl,-enable-runtime-pseudo-reloc
+
+  ruby := video.direct3d video.wgl video.directdraw video.gdi video.qtimage
+  ruby += audio.directsound
+  ruby += input.rawinput input.directinput
+
+  link += $(if $(findstring audio.openal,$(ruby)),-lopenal32)
 else
   unknown_platform: help;
 endif
@@ -58,200 +56,193 @@ endif
 ### ruby ###
 ############
 
-rubyflags =
-rubyflags += $(if $(findstring .sdl,$(ruby)),`sdl-config --cflags`)
+rubyflags := $(call ifhas,.sdl,$(ruby),`sdl-config --cflags`)
+rubyflags += $(call ifhas,.qt,$(ruby),$(qtinc))
 
-link += $(if $(findstring video.direct3d,$(ruby)),$(call mklib,d3d9))
-link += $(if $(findstring video.directdraw,$(ruby)),$(call mklib,ddraw))
-link += $(if $(findstring video.glx,$(ruby)),$(call mklib,GL))
-link += $(if $(findstring video.wgl,$(ruby)),$(call mklib,opengl32))
-link += $(if $(findstring video.xv,$(ruby)),$(call mklib,Xv))
-link += $(if $(findstring audio.alsa,$(ruby)),$(call mklib,asound))
-link += $(if $(findstring audio.ao,$(ruby)),$(call mklib,ao))
-link += $(if $(findstring audio.directsound,$(ruby)),$(call mklib,dsound))
-link += $(if $(findstring audio.openal,$(ruby)),$(if $(call streq,$(platform),x),$(call mklib,openal),$(call mklib,openal32)))
-link += $(if $(findstring input.directinput,$(ruby)),$(call mklib,dinput8) $(call mklib,dxguid))
-link += $(if $(findstring input.sdl,$(ruby)),`sdl-config --libs`)
+link += $(call ifhas,.sdl,$(ruby),`sdl-config --libs`)
+link += $(call ifhas,video.direct3d,$(ruby),-ld3d9)
+link += $(call ifhas,video.directdraw,$(ruby),-lddraw)
+link += $(call ifhas,video.glx,$(ruby),-lGL)
+link += $(call ifhas,video.wgl,$(ruby),-lopengl32)
+link += $(call ifhas,video.xv,$(ruby),-lXv)
+link += $(call ifhas,audio.alsa,$(ruby),-lasound)
+link += $(call ifhas,audio.ao,$(ruby),-lao)
+link += $(call ifhas,audio.directsound,$(ruby),-ldsound)
+link += $(call ifhas,audio.pulseaudio,$(ruby),-lpulse-simple)
+link += $(call ifhas,input.directinput,$(ruby),-ldinput8 -ldxguid)
+link += $(call ifhas,input.rawinput,$(ruby),-ldinput8 -ldxguid)
 
-####################################
-### main target and dependencies ###
-####################################
+####################
+### core objects ###
+####################
 
-objects = main libco hiro ruby libfilter string reader cart cheat \
-  memory smemory cpu scpu smp ssmp sdsp ppu bppu snes \
-  bsx srtc sdd1 spc7110 cx4 dsp1 dsp2 dsp3 dsp4 obc1 st010
+objects := libco ruby libreader libfilter
+objects += system cartridge cheat
+objects += memory smemory cpu cpucore scpu smp smpcore ssmp sdsp ppu bppu
+objects += sgb superfx sa1 bsx srtc sdd1 spc7110 cx4 dsp1 dsp2 dsp3 dsp4 obc1 st010
 
 ifeq ($(enable_gzip),true)
   objects += adler32 compress crc32 deflate gzio inffast inflate inftrees ioapi trees unzip zip zutil
-  flags += $(call mkdef,GZIP_SUPPORT)
+  flags += -DGZIP_SUPPORT
 endif
 
 ifeq ($(enable_jma),true)
   objects += jma jcrc32 lzmadec 7zlzma iiostrm inbyte lzma winout
-  flags += $(call mkdef,JMA_SUPPORT)
+  flags += -DJMA_SUPPORT
 endif
 
-objects := $(patsubst %,obj/%.$(obj),$(objects))
-rubydef := $(foreach c,$(subst .,_,$(call strupper,$(ruby))),$(call mkdef,$c))
-
-# Windows resource file
-ifeq ($(platform),win)
-  ifeq ($(compiler),cl)
-    objects += obj/bsnes.res
-  else ifneq ($(findstring gcc,$(compiler)),)
-    objects += obj/bsnesrc.$(obj)
-  endif
-endif
-
-################
-### implicit ###
-################
+######################
+### implicit rules ###
+######################
 
 compile = \
   $(strip \
     $(if $(filter %.c,$<), \
-      $(c) $1 $(rule), \
+      $(c) $(flags) $1 -c $< -o $@, \
       $(if $(filter %.cpp,$<), \
-        $(cpp) $1 $(rule) \
+        $(cpp) $(flags) $1 -c $< -o $@ \
       ) \
     ) \
   )
 
-%.$(obj): $<; $(call compile)
+%.o: $<; $(call compile)
 
 all: build;
 
-############
-### main ###
-############
-
-obj/main.$(obj): ui/main.cpp ui/* ui/base/* ui/loader/* ui/settings/*
-obj/bsnes.res: ui/bsnes.rc; rc /r /foobj/bsnes.res ui/bsnes.rc
-obj/bsnesrc.$(obj): ui/bsnes.rc; windres ui/bsnes.rc obj/bsnesrc.$(obj)
+include $(ui)/Makefile
+objects := $(patsubst %,obj/%.o,$(objects))
+rubydef := $(foreach c,$(subst .,_,$(call strupper,$(ruby))),-D$c)
 
 #################
 ### libraries ###
 #################
 
-obj/ruby.$(obj): lib/ruby/ruby.cpp lib/ruby/* lib/ruby/video/* lib/ruby/audio/* lib/ruby/input/*
+obj/ruby.o: lib/ruby/ruby.cpp $(call rwildcard,lib/ruby/*)
 	$(call compile,$(rubydef) $(rubyflags))
-obj/hiro.$(obj): lib/hiro/hiro.cpp lib/hiro/* lib/hiro/gtk/* lib/hiro/win/*
-	$(call compile,$(if $(call streq,$(platform),x),`pkg-config --cflags gtk+-2.0`))
-obj/libco.$(obj):     lib/libco/libco.c lib/libco/*
-	$(call compile,-static)
-obj/libfilter.$(obj): lib/libfilter/libfilter.cpp lib/libfilter/*
-obj/string.$(obj):    lib/nall/string.cpp lib/nall/*
+obj/libco.o: lib/libco/libco.c lib/libco/*
+	$(c) -O3 -fomit-frame-pointer -static -Ilib -c $< -o $@
+obj/libreader.o: lib/libreader/libreader.cpp lib/libreader/*
+obj/libfilter.o: lib/libfilter/libfilter.cpp lib/libfilter/*
 
 #################
 ### utilities ###
 #################
 
-obj/reader.$(obj): reader/reader.cpp reader/*
-obj/cart.$(obj)  : cart/cart.cpp cart/*
-obj/cheat.$(obj) : cheat/cheat.cpp cheat/*
+obj/cartridge.o: cartridge/cartridge.cpp cartridge/*
+obj/cheat.o    : cheat/cheat.cpp cheat/*
 
 ##############
 ### memory ###
 ##############
 
-obj/memory.$(obj) : memory/memory.cpp memory/*
-obj/smemory.$(obj): memory/smemory/smemory.cpp memory/smemory/* memory/smemory/mapper/*
+obj/memory.o : memory/memory.cpp memory/*
+obj/smemory.o: memory/smemory/smemory.cpp $(call rwildcard,memory/smemory/)
 
 ###########
 ### cpu ###
 ###########
 
-obj/cpu.$(obj) : cpu/cpu.cpp cpu/*
-obj/scpu.$(obj): cpu/scpu/scpu.cpp cpu/scpu/* cpu/scpu/core/* cpu/scpu/dma/* cpu/scpu/memory/* cpu/scpu/mmio/* cpu/scpu/timing/*
+obj/cpu.o    : cpu/cpu.cpp cpu/*
+obj/cpucore.o: cpu/core/core.cpp $(call rwildcard,cpu/core/)
+obj/scpu.o   : cpu/scpu/scpu.cpp $(call rwildcard,cpu/scpu/)
 
 ###########
 ### smp ###
 ###########
 
-obj/smp.$(obj) : smp/smp.cpp smp/*
-obj/ssmp.$(obj): smp/ssmp/ssmp.cpp smp/ssmp/* smp/ssmp/core/* smp/ssmp/memory/* smp/ssmp/timing/*
+obj/smp.o    : smp/smp.cpp smp/*
+obj/smpcore.o: smp/core/core.cpp $(call rwildcard,smp/core/)
+obj/ssmp.o   : smp/ssmp/ssmp.cpp $(call rwildcard,smp/ssmp/)
 
 ###########
 ### dsp ###
 ###########
 
-obj/adsp.$(obj): dsp/adsp/adsp.cpp dsp/adsp/*
-obj/bdsp.$(obj): dsp/bdsp/bdsp.cpp dsp/bdsp/*
-obj/sdsp.$(obj): dsp/sdsp/sdsp.cpp dsp/sdsp/*
+obj/adsp.o: dsp/adsp/adsp.cpp dsp/adsp/*
+obj/sdsp.o: dsp/sdsp/sdsp.cpp dsp/sdsp/*
 
 ###########
 ### ppu ###
 ###########
 
-obj/ppu.$(obj) : ppu/ppu.cpp ppu/*
-obj/bppu.$(obj): ppu/bppu/bppu.cpp ppu/bppu/*
+obj/ppu.o : ppu/ppu.cpp ppu/*
+obj/bppu.o: ppu/bppu/bppu.cpp ppu/bppu/*
 
-############
-### snes ###
-############
+##############
+### system ###
+##############
 
-obj/snes.$(obj): snes/snes.cpp snes/* snes/scheduler/* snes/video/* snes/audio/* snes/input/*
+obj/system.o: system/system.cpp $(call rwildcard,system/)
 
 #####################
 ### special chips ###
 #####################
 
-obj/bsx.$(obj)    : chip/bsx/bsx.cpp chip/bsx/*
-obj/srtc.$(obj)   : chip/srtc/srtc.cpp chip/srtc/*
-obj/sdd1.$(obj)   : chip/sdd1/sdd1.cpp chip/sdd1/*
-obj/spc7110.$(obj): chip/spc7110/spc7110.cpp chip/spc7110/*
-obj/cx4.$(obj)    : chip/cx4/cx4.cpp chip/cx4/*
-obj/dsp1.$(obj)   : chip/dsp1/dsp1.cpp chip/dsp1/*
-obj/dsp2.$(obj)   : chip/dsp2/dsp2.cpp chip/dsp2/*
-obj/dsp3.$(obj)   : chip/dsp3/dsp3.cpp chip/dsp3/*
-obj/dsp4.$(obj)   : chip/dsp4/dsp4.cpp chip/dsp4/*
-obj/obc1.$(obj)   : chip/obc1/obc1.cpp chip/obc1/*
-obj/st010.$(obj)  : chip/st010/st010.cpp chip/st010/*
+obj/sgb.o    : chip/sgb/sgb.cpp $(call rwildcard,chip/sgb/)
+obj/superfx.o: chip/superfx/superfx.cpp $(call rwildcard,chip/superfx/)
+obj/sa1.o    : chip/sa1/sa1.cpp $(call rwildcard,chip/sa1/)
+obj/bsx.o    : chip/bsx/bsx.cpp chip/bsx/*
+obj/srtc.o   : chip/srtc/srtc.cpp chip/srtc/*
+obj/sdd1.o   : chip/sdd1/sdd1.cpp chip/sdd1/*
+obj/spc7110.o: chip/spc7110/spc7110.cpp chip/spc7110/*
+obj/cx4.o    : chip/cx4/cx4.cpp chip/cx4/*
+obj/dsp1.o   : chip/dsp1/dsp1.cpp chip/dsp1/*
+obj/dsp2.o   : chip/dsp2/dsp2.cpp chip/dsp2/*
+obj/dsp3.o   : chip/dsp3/dsp3.cpp chip/dsp3/*
+obj/dsp4.o   : chip/dsp4/dsp4.cpp chip/dsp4/*
+obj/obc1.o   : chip/obc1/obc1.cpp chip/obc1/*
+obj/st010.o  : chip/st010/st010.cpp chip/st010/*
 
 ############
 ### zlib ###
 ############
 
-obj/adler32.$(obj) : reader/zlib/adler32.c reader/zlib/*
-obj/compress.$(obj): reader/zlib/compress.c reader/zlib/*
-obj/crc32.$(obj)   : reader/zlib/crc32.c reader/zlib/*
-obj/deflate.$(obj) : reader/zlib/deflate.c reader/zlib/*
-obj/gzio.$(obj)    : reader/zlib/gzio.c reader/zlib/*
-obj/inffast.$(obj) : reader/zlib/inffast.c reader/zlib/*
-obj/inflate.$(obj) : reader/zlib/inflate.c reader/zlib/*
-obj/inftrees.$(obj): reader/zlib/inftrees.c reader/zlib/*
-obj/ioapi.$(obj)   : reader/zlib/ioapi.c reader/zlib/*
-obj/trees.$(obj)   : reader/zlib/trees.c reader/zlib/*
-obj/unzip.$(obj)   : reader/zlib/unzip.c reader/zlib/*
-obj/zip.$(obj)     : reader/zlib/zip.c reader/zlib/*
-obj/zutil.$(obj)   : reader/zlib/zutil.c reader/zlib/*
+obj/adler32.o : lib/zlib/adler32.c lib/zlib/*
+obj/compress.o: lib/zlib/compress.c lib/zlib/*
+obj/crc32.o   : lib/zlib/crc32.c lib/zlib/*
+obj/deflate.o : lib/zlib/deflate.c lib/zlib/*
+obj/gzio.o    : lib/zlib/gzio.c lib/zlib/*
+obj/inffast.o : lib/zlib/inffast.c lib/zlib/*
+obj/inflate.o : lib/zlib/inflate.c lib/zlib/*
+obj/inftrees.o: lib/zlib/inftrees.c lib/zlib/*
+obj/ioapi.o   : lib/zlib/ioapi.c lib/zlib/*
+obj/trees.o   : lib/zlib/trees.c lib/zlib/*
+obj/unzip.o   : lib/zlib/unzip.c lib/zlib/*
+obj/zip.o     : lib/zlib/zip.c lib/zlib/*
+obj/zutil.o   : lib/zlib/zutil.c lib/zlib/*
 
-###########
-### jma ###
-###########
+##############
+### libjma ###
+##############
 
-obj/jma.$(obj)    : reader/jma/jma.cpp reader/jma/*
-obj/jcrc32.$(obj) : reader/jma/jcrc32.cpp reader/jma/*
-obj/lzmadec.$(obj): reader/jma/lzmadec.cpp reader/jma/*
-obj/7zlzma.$(obj) : reader/jma/7zlzma.cpp reader/jma/*
-obj/iiostrm.$(obj): reader/jma/iiostrm.cpp reader/jma/*
-obj/inbyte.$(obj) : reader/jma/inbyte.cpp reader/jma/*
-obj/lzma.$(obj)   : reader/jma/lzma.cpp reader/jma/*
-obj/winout.$(obj) : reader/jma/winout.cpp reader/jma/*
+obj/jma.o    : lib/libjma/jma.cpp lib/libjma/*
+obj/jcrc32.o : lib/libjma/jcrc32.cpp lib/libjma/*
+obj/lzmadec.o: lib/libjma/lzmadec.cpp lib/libjma/*
+obj/7zlzma.o : lib/libjma/7zlzma.cpp lib/libjma/*
+obj/iiostrm.o: lib/libjma/iiostrm.cpp lib/libjma/*
+obj/inbyte.o : lib/libjma/inbyte.cpp lib/libjma/*
+obj/lzma.o   : lib/libjma/lzma.cpp lib/libjma/*
+obj/winout.o : lib/libjma/winout.cpp lib/libjma/*
 
 ###############
 ### targets ###
 ###############
 
-build: $(objects)
-	$(strip $(cpp) $(call mkbin,../bsnes) $(objects) $(link))
+build: ui_build $(objects)
+ifeq ($(platform),osx)
+	test -d ../bsnes.app || mkdir -p ../bsnes.app/Contents/MacOS
+	$(strip $(cpp) -o ../bsnes.app/Contents/MacOS/bsnes $(objects) $(link))
+else
+	$(strip $(cpp) -o ../bsnes $(objects) $(link))
+endif
 
 install:
 	install -D -m 755 ../bsnes $(DESTDIR)$(prefix)/bin/bsnes
-	install -D -m 644 data/bsnes.png $(DESTDIR)$(prefix)/share/icons/bsnes.png
+	install -D -m 644 data/bsnes.png $(DESTDIR)$(prefix)/share/pixmaps/bsnes.png
+	install -D -m 644 data/bsnes.desktop $(DESTDIR)$(prefix)/share/applications/bsnes.desktop
 
-clean:
-	-@$(call delete,obj/*.$(obj))
+clean: ui_clean
+	-@$(call delete,obj/*.o)
 	-@$(call delete,*.res)
 	-@$(call delete,*.pgd)
 	-@$(call delete,*.pgc)
@@ -270,7 +261,6 @@ help:
 	@echo "  gcc              - GCC compiler"
 	@echo "  mingw32-gcc      - MinGW compiler"
 	@echo "  i586-mingw32-gcc - MinGW cross compiler"
-	@echo "  cl               - Visual C++"
 	@echo ""
 	@echo "Available options:"
 	@echo "  enable_gzip=[true|false] - Enable ZIP / GZ support (default=false)"

src/base.hpp

@@ -1,4 +1,4 @@
-#define BSNES_VERSION "0.037"
+#define BSNES_VERSION "0.047"
 #define BSNES_TITLE   "bsnes v" BSNES_VERSION
 
 #define BUSCORE sBus
@@ -9,38 +9,35 @@
 
 //S-DSP can be encapsulated into a state machine using #define magic
 //this avoids ~2.048m co_switch() calls per second (~5% speedup)
-#define USE_STATE_MACHINE
-
-//FAST_FRAMESKIP disables calculation of RTO during frameskip
-//frameskip offers near-zero speedup if RTO is calculated
-//accuracy is not affected by this define when frameskipping is off
-#define FAST_FRAMESKIP
+#define DSP_STATE_MACHINE
 
 //game genie + pro action replay code support (~2% speed hit)
 #define CHEAT_SYSTEM
 
+#include <libco/libco.h>
+
 #include <nall/algorithm.hpp>
 #include <nall/array.hpp>
 #include <nall/bit.hpp>
-#include <nall/config.hpp>
 #include <nall/detect.hpp>
+#include <nall/dl.hpp>
 #include <nall/endian.hpp>
-#include <nall/file.hpp>
 #include <nall/function.hpp>
-#include <nall/modulo.hpp>
+#include <nall/moduloarray.hpp>
 #include <nall/new.hpp>
-#include <nall/sort.hpp>
+#include <nall/platform.hpp>
+#include <nall/property.hpp>
 #include <nall/stdint.hpp>
 #include <nall/string.hpp>
 #include <nall/utility.hpp>
 #include <nall/vector.hpp>
 using namespace nall;
 
-#include <libco/libco.h>
-#include <bbase.h>
+typedef int8_t   int8;
+typedef int16_t  int16;
+typedef int32_t  int32;
+typedef uint8_t  uint8;
+typedef uint16_t uint16;
+typedef uint32_t uint32;
 
-//platform-specific global functions
-void alert(const char*, ...);
-void dprintf(const char*, ...);
-
-#include "interface.h"
+#include "interface.hpp"

src/cart/cart.cpp

@@ -1,167 +0,0 @@
-#include "../base.h"
-#define CART_CPP
-
-#include <nall/crc32.hpp>
-#include <nall/ups.hpp>
-
-#include "cart_load.cpp"
-#include "cart_normal.cpp"
-#include "cart_bsx.cpp"
-#include "cart_bsc.cpp"
-#include "cart_st.cpp"
-
-#include "cart_file.cpp"
-#include "cart_header.cpp"
-
-namespace memory {
-  MappedRAM cartrom, cartram, cartrtc;
-  MappedRAM bscram;
-  MappedRAM stArom, stAram;
-  MappedRAM stBrom, stBram;
-};
-
-Cartridge cartridge;
-
-const char* Cartridge::name() { return info.filename; }
-Cartridge::CartridgeMode Cartridge::mode() { return info.mode; }
-Cartridge::MemoryMapper Cartridge::mapper() { return info.mapper; }
-Cartridge::Region Cartridge::region() { return info.region; }
-bool Cartridge::loaded() { return cart.loaded; }
-
-void Cartridge::load_begin(CartridgeMode mode) {
-  cart.rom = cart.ram = cart.rtc = 0;
-  bs.ram   = 0;
-  stA.rom  = stA.ram  = 0;
-  stB.rom  = stB.ram  = 0;
-
-  cart.rom_size = cart.ram_size = cart.rtc_size = 0;
-  bs.ram_size   = 0;
-  stA.rom_size  = stA.ram_size  = 0;
-  stB.rom_size  = stB.ram_size  = 0;
-
-  info.mode = mode;
-  info.patched = false;
-
-  info.bsxcart  = false;
-  info.bsxflash = false;
-}
-
-void Cartridge::load_end() {
-  memory::cartrom.map(cart.rom, cart.rom_size);
-  memory::cartram.map(cart.ram, cart.ram_size);
-  memory::cartrtc.map(cart.rtc, cart.rtc_size);
-  memory::bscram.map(bs.ram, bs.ram_size);
-  memory::stArom.map(stA.rom, stA.rom_size);
-  memory::stAram.map(stA.ram, stA.ram_size);
-  memory::stBrom.map(stB.rom, stB.rom_size);
-  memory::stBram.map(stB.ram, stB.ram_size);
-
-  memory::cartrom.write_protect(true);
-  memory::cartram.write_protect(false);
-  memory::bscram.write_protect(true);
-  memory::stArom.write_protect(true);
-  memory::stAram.write_protect(false);
-  memory::stBrom.write_protect(true);
-  memory::stBram.write_protect(false);
-
-  if(file::exists(get_cheat_filename(cart.fn, "cht"))) {
-    cheat.clear();
-    cheat.load(cheatfn);
-  }
-
-  cart.loaded = true;
-  bus.load_cart();
-}
-
-bool Cartridge::unload() {
-  if(cart.loaded == false) return false;
-
-  bus.unload_cart();
-
-  switch(info.mode) {
-    case ModeNormal:      unload_cart_normal(); break;
-    case ModeBSX:         unload_cart_bsx();    break;
-    case ModeBSC:         unload_cart_bsc();    break;
-    case ModeSufamiTurbo: unload_cart_st();     break;
-  }
-
-  if(cart.rom) { delete[] cart.rom; cart.rom = 0; }
-  if(cart.ram) { delete[] cart.ram; cart.ram = 0; }
-  if(cart.rtc) { delete[] cart.rtc; cart.rtc = 0; }
-  if(bs.ram)   { delete[] bs.ram;   bs.ram   = 0; }
-  if(stA.rom)  { delete[] stA.rom;  stA.rom  = 0; }
-  if(stA.ram)  { delete[] stA.ram;  stA.ram  = 0; }
-  if(stB.rom)  { delete[] stB.rom;  stB.rom  = 0; }
-  if(stB.ram)  { delete[] stB.ram;  stB.ram  = 0; }
-
-  if(cheat.count() > 0 || file::exists(get_cheat_filename(cart.fn, "cht"))) {
-    cheat.save(cheatfn);
-    cheat.clear();
-  }
-
-  cart.loaded = false;
-  return true;
-}
-
-Cartridge::Cartridge() {
-  cart.loaded = false;
-}
-
-Cartridge::~Cartridge() {
-  if(cart.loaded == true) unload();
-}
-
-//
-
-void Cartridge::cartinfo_t::reset() {
-  type        = TypeUnknown;
-  mapper      = LoROM;
-  dsp1_mapper = DSP1Unmapped;
-  region      = NTSC;
-
-  rom_size = 0;
-  ram_size = 0;
-
-  bsxslot    = false;
-  superfx    = false;
-  sa1        = false;
-  srtc       = false;
-  sdd1       = false;
-  spc7110    = false;
-  spc7110rtc = false;
-  cx4        = false;
-  dsp1       = false;
-  dsp2       = false;
-  dsp3       = false;
-  dsp4       = false;
-  obc1       = false;
-  st010      = false;
-  st011      = false;
-  st018      = false;
-}
-
-//apply cart-specific settings to current cartridge mode settings
-Cartridge::info_t& Cartridge::info_t::operator=(const Cartridge::cartinfo_t &source) {
-  mapper      = source.mapper;
-  dsp1_mapper = source.dsp1_mapper;
-  region      = source.region;
-
-  bsxslot    = source.bsxslot;
-  superfx    = source.superfx;
-  sa1        = source.sa1;
-  srtc       = source.srtc;
-  sdd1       = source.sdd1;
-  spc7110    = source.spc7110;
-  spc7110rtc = source.spc7110rtc;
-  cx4        = source.cx4;
-  dsp1       = source.dsp1;
-  dsp2       = source.dsp2;
-  dsp3       = source.dsp3;
-  dsp4       = source.dsp4;
-  obc1       = source.obc1;
-  st010      = source.st010;
-  st011      = source.st011;
-  st018      = source.st018;
-
-  return *this;
-}

src/cart/cart.h

@@ -1,203 +0,0 @@
-class Cartridge {
-public:
-  enum CartridgeMode {
-    ModeNormal,
-    ModeBSC,
-    ModeBSX,
-    ModeSufamiTurbo,
-  };
-
-  enum CartridgeType {
-    TypeNormal,
-    TypeBSC,
-    TypeBSXBIOS,
-    TypeBSX,
-    TypeSufamiTurboBIOS,
-    TypeSufamiTurbo,
-    TypeUnknown,
-  };
-
-  enum HeaderField {
-    CART_NAME = 0x00,
-    MAPPER    = 0x15,
-    ROM_TYPE  = 0x16,
-    ROM_SIZE  = 0x17,
-    RAM_SIZE  = 0x18,
-    REGION    = 0x19,
-    COMPANY   = 0x1a,
-    VERSION   = 0x1b,
-    ICKSUM    = 0x1c,
-    CKSUM     = 0x1e,
-    RESETV    = 0x3c,
-  };
-
-  enum Region {
-    NTSC,
-    PAL,
-  };
-
-  enum MemoryMapper {
-    LoROM,
-    HiROM,
-    ExLoROM,
-    ExHiROM,
-    SPC7110ROM,
-    BSCLoROM,
-    BSCHiROM,
-    BSXROM,
-    STROM,
-  };
-
-  enum DSP1MemoryMapper {
-    DSP1Unmapped,
-    DSP1LoROM1MB,
-    DSP1LoROM2MB,
-    DSP1HiROM,
-  };
-
-  const char* name();
-  CartridgeMode mode();
-  MemoryMapper mapper();
-  Region region();
-
-  struct {
-    bool loaded;
-    char fn[PATH_MAX];
-    uint8 *rom, *ram, *rtc;
-    uint rom_size, ram_size, rtc_size;
-  } cart;
-
-  struct {
-    char fn[PATH_MAX];
-    uint8 *ram;
-    uint ram_size;
-  } bs;
-
-  struct {
-    char fn[PATH_MAX];
-    uint8 *rom, *ram;
-    uint rom_size, ram_size;
-  } stA, stB;
-
-  struct cartinfo_t {
-    CartridgeType type;
-    MemoryMapper mapper;
-    DSP1MemoryMapper dsp1_mapper;
-    Region region;
-
-    unsigned rom_size;
-    unsigned ram_size;
-
-    bool bsxslot;
-    bool superfx;
-    bool sa1;
-    bool srtc;
-    bool sdd1;
-    bool spc7110;
-    bool spc7110rtc;
-    bool cx4;
-    bool dsp1;
-    bool dsp2;
-    bool dsp3;
-    bool dsp4;
-    bool obc1;
-    bool st010;
-    bool st011;
-    bool st018;
-
-    void reset();
-  };
-
-  struct info_t {
-    char filename[PATH_MAX * 4];
-    bool patched;
-
-    CartridgeMode mode;
-    MemoryMapper mapper;
-    DSP1MemoryMapper dsp1_mapper;
-    Region region;
-
-    bool bsxcart;   //is BS-X cart inserted?
-    bool bsxflash;  //is BS-X flash cart inserted into BS-X cart?
-
-    bool bsxslot;
-    bool superfx;
-    bool sa1;
-    bool srtc;
-    bool sdd1;
-    bool spc7110;
-    bool spc7110rtc;
-    bool cx4;
-    bool dsp1;
-    bool dsp2;
-    bool dsp3;
-    bool dsp4;
-    bool obc1;
-    bool st010;
-    bool st011;
-    bool st018;
-
-    info_t& operator=(const cartinfo_t&);
-  } info;
-
-  struct {
-    char fn[PATH_MAX];
-    uint8_t *data;
-    unsigned size;
-  } image;
-  bool load_image(const char*);
-  bool inspect_image(cartinfo_t &cartinfo, const char *filename);
-  bool load_ram(const char *filename, uint8_t *&data, unsigned size, uint8_t init);
-
-  void load_cart_normal(const char*);
-  void load_cart_bsc(const char*, const char*);
-  void load_cart_bsx(const char*, const char*);
-  void load_cart_st(const char*, const char*, const char*);
-
-  void unload_cart_normal();
-  void unload_cart_bsx();
-  void unload_cart_bsc();
-  void unload_cart_st();
-
-  bool loaded();
-  void load_begin(CartridgeMode);
-  void load_end();
-  bool unload();
-
-  void read_header(cartinfo_t &info, const uint8_t *data, unsigned size);
-  unsigned find_header(const uint8_t *data, unsigned size);
-  unsigned score_header(const uint8_t *data, unsigned size, unsigned addr);
-
-  enum CompressionMode {
-    CompressionNone,    //always load without compression
-    CompressionInspect, //use file header inspection
-    CompressionAuto,    //use file extension or file header inspection (configured by user)
-  };
-  bool load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression = CompressionNone);
-  bool save_file(const char *fn, uint8 *data, uint size);
-  bool apply_patch(const uint8_t *pdata, unsigned psize, uint8_t *&data, unsigned &size);
-  char* modify_extension(char *filename, const char *extension);
-  char* get_base_filename(char *filename);
-  char* get_path_filename(char *filename, const char *path, const char *source, const char *extension);
-  char* get_patch_filename(const char *source, const char *extension);
-  char* get_save_filename(const char *source, const char *extension);
-  char* get_cheat_filename(const char *source, const char *extension);
-
-  Cartridge();
-  ~Cartridge();
-
-private:
-  char patchfn[PATH_MAX];
-  char savefn[PATH_MAX];
-  char rtcfn[PATH_MAX];
-  char cheatfn[PATH_MAX];
-};
-
-namespace memory {
-  extern MappedRAM cartrom, cartram, cartrtc;
-  extern MappedRAM bscram;
-  extern MappedRAM stArom, stAram;
-  extern MappedRAM stBrom, stBram;
-};
-
-extern Cartridge cartridge;

src/cart/cart_bsc.cpp

@@ -1,44 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_bsc(const char *base, const char *slot) {
-  uint8_t *data;
-  unsigned size;
-  strcpy(cart.fn, base);
-  strcpy(bs.fn, slot);
-
-  load_begin(ModeBSC);
-  if(load_image(base) == false) return;
-
-  cartinfo_t cartinfo;
-  read_header(cartinfo, cart.rom = image.data, cart.rom_size = image.size);
-  info = cartinfo;
-
-  if(load_image(slot) == true) {
-    info.bsxflash = true;
-    bs.ram = image.data;
-    bs.ram_size = image.size;
-  }
-
-  if(cartinfo.ram_size > 0) {
-    load_ram(get_save_filename(base, "srm"), cart.ram, cart.ram_size = cartinfo.ram_size, 0xff);
-  }
-
-  load_end();
-
-  //set base filename
-  strcpy(info.filename, base);
-  get_base_filename(info.filename);
-  if(*slot) {
-    char filenameBS[PATH_MAX];
-    strcpy(filenameBS, slot);
-    get_base_filename(filenameBS);
-    strcat(info.filename, " + ");
-    strcat(info.filename, filenameBS);
-  }
-}
-
-void Cartridge::unload_cart_bsc() {
-  if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_bsx.cpp

@@ -1,49 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_bsx(const char *base, const char *slot) {
-  uint8_t *data;
-  unsigned size;
-  strcpy(cart.fn, base);
-  strcpy(bs.fn, slot);
-
-  load_begin(ModeBSX);
-  if(load_image(base) == false) return;
-  info.bsxcart = true;
-
-  cartinfo_t cartinfo;
-  read_header(cartinfo, cart.rom = image.data, cart.rom_size = image.size);
-  info = cartinfo;
-  cart.ram = 0;
-  cart.ram_size = 0;
-
-  memset(bsxcart.sram.handle (), 0x00, bsxcart.sram.size ());
-  memset(bsxcart.psram.handle(), 0x00, bsxcart.psram.size());
-
-  if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
-    memcpy(bsxcart.sram.handle (), data, min(bsxcart.sram.size (), size));
-    delete[] data;
-  }
-
-  if(load_file(get_save_filename(cart.fn, "psr"), data, size, CompressionNone) == true) {
-    memcpy(bsxcart.psram.handle(), data, min(bsxcart.psram.size(), size));
-    delete[] data;
-  }
-
-  if(load_image(slot)) {
-    info.bsxflash = true;
-    bs.ram = image.data;
-    bs.ram_size = image.size;
-  }
-
-  load_end();
-
-  strcpy(info.filename, !*slot ? base : slot);
-  get_base_filename(info.filename);
-}
-
-void Cartridge::unload_cart_bsx() {
-  save_file(get_save_filename(cart.fn, "srm"), bsxcart.sram.handle (), bsxcart.sram.size ());
-  save_file(get_save_filename(cart.fn, "psr"), bsxcart.psram.handle(), bsxcart.psram.size());
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_file.cpp

@@ -1,183 +0,0 @@
-#ifdef CART_CPP
-
-#include "../reader/filereader.h"
-
-#if defined(GZIP_SUPPORT)
-  #include "../reader/gzreader.h"
-  #include "../reader/zipreader.h"
-#endif
-
-#if defined(JMA_SUPPORT)
-  #include "../reader/jmareader.h"
-#endif
-
-char* Cartridge::modify_extension(char *filename, const char *extension) {
-  int i;
-  for(i = strlen(filename); i >= 0; i--) {
-    if(filename[i] == '.') break;
-    if(filename[i] == '/') break;
-    if(filename[i] == '\\') break;
-  }
-  if(i > 0 && filename[i] == '.') filename[i] = 0;
-  strcat(filename, ".");
-  strcat(filename, extension);
-  return filename;
-}
-
-//remove directory information and file extension ("/foo/bar.ext" -> "bar")
-char* Cartridge::get_base_filename(char *filename) {
-  //remove extension
-  for(int i = strlen(filename) - 1; i >= 0; i--) {
-    if(filename[i] == '.') {
-      filename[i] = 0;
-      break;
-    }
-  }
-
-  //remove directory information
-  for(int i = strlen(filename) - 1; i >= 0; i--) {
-    if(filename[i] == '/' || filename[i] == '\\') {
-      i++;
-      char *output = filename;
-      while(true) {
-        *output++ = filename[i];
-        if(!filename[i]) break;
-        i++;
-      }
-      break;
-    }
-  }
-
-  return filename;
-}
-
-char* Cartridge::get_path_filename(char *filename, const char *path, const char *source, const char *extension) {
-  strcpy(filename, source);
-  for(char *p = filename; *p; p++) { if(*p == '\\') *p = '/'; }
-  modify_extension(filename, extension);
-
-  //override path with user-specified folder, if one was defined
-  if(*path) {
-    lstring part;
-    split(part, "/", filename);
-    string fn = path;
-    if(strend(fn, "/") == false) strcat(fn, "/");
-    strcat(fn, part[count(part) - 1]);
-    strcpy(filename, fn);
-
-    //resolve relative path, if found
-    if(strbegin(fn, "./") == true) {
-      ltrim(fn, "./");
-      strcpy(filename, config::path.base);
-      strcat(filename, fn);
-    }
-  }
-
-  return filename;
-}
-
-char* Cartridge::get_patch_filename(const char *source, const char *extension) {
-  return get_path_filename(patchfn, config::path.patch, source, extension);
-}
-
-char* Cartridge::get_save_filename(const char *source, const char *extension) {
-  return get_path_filename(savefn, config::path.save, source, extension);
-}
-
-char* Cartridge::get_cheat_filename(const char *source, const char *extension) {
-  return get_path_filename(cheatfn, config::path.cheat, source, extension);
-}
-
-bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression) {
-  if(file::exists(fn) == false) return false;
-
-  Reader::Type filetype = Reader::Normal;
-  if(compression == CompressionInspect) filetype = Reader::detect(fn, true);
-  if(compression == CompressionAuto) filetype = Reader::detect(fn, config::file.autodetect_type);
-
-  switch(filetype) {
-    default:
-      dprintf("* Warning: filetype detected as unsupported compression type.");
-      dprintf("* Will attempt to load as uncompressed file -- may fail.");
-    case Reader::Normal: {
-      FileReader ff(fn);
-      if(!ff.ready()) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-      size = ff.size();
-      data = ff.read();
-    } break;
-
-    #ifdef GZIP_SUPPORT
-    case Reader::GZIP: {
-      GZReader gf(fn);
-      if(!gf.ready()) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-      size = gf.size();
-      data = gf.read();
-    } break;
-
-    case Reader::ZIP: {
-      ZipReader zf(fn);
-      if(!zf.ready()) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-      size = zf.size();
-      data = zf.read();
-    } break;
-    #endif
-
-    #ifdef JMA_SUPPORT
-    case Reader::JMA: {
-      try {
-        JMAReader jf(fn);
-        size = jf.size();
-        data = jf.read();
-      } catch(JMA::jma_errors jma_error) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-    } break;
-    #endif
-  }
-
-  return true;
-}
-
-bool Cartridge::apply_patch(const uint8_t *pdata, const unsigned psize, uint8_t *&data, unsigned &size) {
-  uint8_t *outdata = 0;
-  unsigned outsize;
-  ups patcher;
-  ups::result result = patcher.apply(pdata, psize, data, size, outdata, outsize);
-
-  bool apply = false;
-  if(result == ups::ok) apply = true;
-  if(config::file.bypass_patch_crc32 == true) {
-    if(result == ups::input_crc32_invalid) apply = true;
-    if(result == ups::output_crc32_invalid) apply = true;
-  }
-
-  //if patch application was successful, replace old data, size with new data, size
-  if(apply == true) {
-    delete[] data;
-    data = new uint8_t[size = outsize];
-    memcpy(data, outdata, outsize);
-  }
-
-  if(outdata) delete[] outdata;
-  return apply;
-}
-
-bool Cartridge::save_file(const char *fn, uint8 *data, uint size) {
-  file fp;
-  if(!fp.open(fn, file::mode_write)) return false;
-  fp.write(data, size);
-  fp.close();
-  return true;
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_load.cpp

@@ -1,50 +0,0 @@
-#ifdef CART_CPP
-
-bool Cartridge::load_image(const char *filename) {
-  if(!filename || !*filename) return false;
-
-  uint8_t *data;
-  unsigned size;
-  if(!load_file(filename, data, size, CompressionAuto)) return false;
-
-  if((size & 0x7fff) != 512) {
-    image.data = data;
-    image.size = size;
-  } else {
-    //remove 512-byte header
-    image.data = new uint8_t[image.size = size - 512];
-    memcpy(image.data, data + 512, image.size);
-  }
-
-  if(load_file(get_patch_filename(filename, "ups"), data, size, CompressionInspect) == true) {
-    apply_patch(data, size, image.data, image.size);
-    delete[] data;
-    info.patched = true;
-  }
-
-  return true;
-}
-
-bool Cartridge::inspect_image(cartinfo_t &cartinfo, const char *filename) {
-  cartinfo.reset();
-  if(!load_image(filename)) return false;
-
-  read_header(cartinfo, image.data, image.size);
-  delete[] image.data;
-  return true;
-}
-
-bool Cartridge::load_ram(const char *filename, uint8_t *&data, unsigned size, uint8_t init) {
-  data = new uint8_t[size];
-  memset(data, init, size);
-
-  uint8_t *savedata;
-  unsigned savesize;
-  if(load_file(filename, savedata, savesize, CompressionNone) == false) return false;
-
-  memcpy(data, savedata, min(size, savesize));
-  delete[] savedata;
-  return true;
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_normal.cpp

@@ -1,35 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_normal(const char *base) {
-  uint8_t *data;
-  unsigned size;
-  strcpy(cart.fn, base);
-
-  load_begin(ModeNormal);
-  if(load_image(base) == false) return;
-
-  cartinfo_t cartinfo;
-  read_header(cartinfo, cart.rom = image.data, cart.rom_size = image.size);
-  info = cartinfo;
-
-  if(cartinfo.ram_size > 0) {
-    load_ram(get_save_filename(base, "srm"), cart.ram, cart.ram_size = cartinfo.ram_size, 0xff);
-  }
-
-  if(cartinfo.srtc || cartinfo.spc7110rtc) {
-    load_ram(get_save_filename(base, "rtc"), cart.rtc, cart.rtc_size = 20, 0x00);
-  }
-
-  load_end();
-
-  //set base filename
-  strcpy(info.filename, base);
-  get_base_filename(info.filename);
-}
-
-void Cartridge::unload_cart_normal() {
-  if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
-  if(cart.rtc) save_file(get_save_filename(cart.fn, "rtc"), cart.rtc, cart.rtc_size);
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_st.cpp

@@ -1,62 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_st(const char *base, const char *slotA, const char *slotB) {
-  uint8_t *data;
-  unsigned size;
-  strcpy(cart.fn, base);
-  strcpy(stA.fn, slotA);
-  strcpy(stB.fn, slotB);
-
-  load_begin(ModeSufamiTurbo);
-  if(load_image(base) == false) return;
-
-  cartinfo_t cartinfo;
-  read_header(cartinfo, cart.rom = image.data, cart.rom_size = image.size);
-  info = cartinfo;
-
-  if(load_image(slotA)) {
-    stA.rom = new(zeromemory) uint8_t[stA.rom_size = 0x100000];
-    memcpy(stA.rom, image.data, min(image.size, stA.rom_size));
-    delete[] image.data;
-
-    load_ram(get_save_filename(slotA, "srm"), stA.ram, stA.ram_size = 0x020000, 0xff);
-  }
-
-  if(load_image(slotB)) {
-    stB.rom = new(zeromemory) uint8_t[stB.rom_size = 0x100000];
-    memcpy(stB.rom, image.data, min(image.size, stB.rom_size));
-    delete[] image.data;
-
-    load_ram(get_save_filename(slotB, "srm"), stB.ram, stB.ram_size = 0x020000, 0xff);
-  }
-
-  load_end();
-
-  //set base filename
-  if(!*slotA && !*slotB) {
-    strcpy(info.filename, cart.fn);
-    get_base_filename(info.filename);
-  } else if(*slotA && !*slotB) {
-    strcpy(info.filename, slotA);
-    get_base_filename(info.filename);
-  } else if(!*slotA && *slotB) {
-    strcpy(info.filename, slotB);
-    get_base_filename(info.filename);
-  } else {
-    char filenameA[PATH_MAX], filenameB[PATH_MAX];
-    strcpy(filenameA, slotA);
-    get_base_filename(filenameA);
-    strcpy(filenameB, slotB);
-    get_base_filename(filenameB);
-    strcpy(info.filename, filenameA);
-    strcat(info.filename, " + ");
-    strcat(info.filename, filenameB);
-  }
-}
-
-void Cartridge::unload_cart_st() {
-  if(stA.ram) save_file(get_save_filename(stA.fn, "srm"), stA.ram, stA.ram_size);
-  if(stB.ram) save_file(get_save_filename(stB.fn, "srm"), stB.ram, stB.ram_size);
-}
-
-#endif //ifdef CART_CPP

src/cartridge/cartridge.cpp

@@ -0,0 +1,157 @@
+#include <../base.hpp>
+
+#define CARTRIDGE_CPP
+namespace SNES {
+
+#include "header.cpp"
+
+namespace memory {
+  MappedRAM cartrom, cartram, cartrtc;
+  MappedRAM bsxflash, bsxram, bsxpram;
+  MappedRAM stArom, stAram;
+  MappedRAM stBrom, stBram;
+  MappedRAM gbrom, gbram;
+};
+
+Cartridge cartridge;
+
+void Cartridge::load(Mode cartridge_mode) {
+  cartinfo_t cartinfo;
+  read_header(cartinfo, memory::cartrom.data(), memory::cartrom.size());
+  set_cartinfo(cartinfo);
+
+  set(mode, cartridge_mode);
+
+  if(cartinfo.ram_size > 0) {
+    memory::cartram.map(new(zeromemory) uint8_t[cartinfo.ram_size], cartinfo.ram_size);
+  }
+
+  if(cartinfo.srtc || cartinfo.spc7110rtc) {
+    memory::cartrtc.map(new(zeromemory) uint8_t[20], 20);
+  }
+
+  if(mode() == ModeBsx) {
+    memory::bsxram.map (new(zeromemory) uint8_t[ 32 * 1024],  32 * 1024);
+    memory::bsxpram.map(new(zeromemory) uint8_t[512 * 1024], 512 * 1024);
+  }
+
+  if(mode() == ModeSufamiTurbo) {
+    if(memory::stArom.data()) memory::stAram.map(new(zeromemory) uint8_t[128 * 1024], 128 * 1024);
+    if(memory::stBrom.data()) memory::stBram.map(new(zeromemory) uint8_t[128 * 1024], 128 * 1024);
+  }
+
+  if(mode() == ModeSuperGameBoy) {
+    if(memory::gbrom.data()) memory::gbram.map(new(zeromemory) uint8_t[64 * 1024], 64 * 1024);
+  }
+
+  memory::cartrom.write_protect(true);
+  memory::cartram.write_protect(false);
+  memory::cartrtc.write_protect(false);
+  memory::bsxflash.write_protect(true);
+  memory::bsxram.write_protect(false);
+  memory::bsxpram.write_protect(false);
+  memory::stArom.write_protect(true);
+  memory::stAram.write_protect(false);
+  memory::stBrom.write_protect(true);
+  memory::stBram.write_protect(false);
+  memory::gbrom.write_protect(true);
+  memory::gbram.write_protect(false);
+
+  bus.load_cart();
+  set(loaded, true);
+}
+
+void Cartridge::unload() {
+  memory::cartrom.reset();
+  memory::cartram.reset();
+  memory::cartrtc.reset();
+  memory::bsxflash.reset();
+  memory::bsxram.reset();
+  memory::bsxpram.reset();
+  memory::stArom.reset();
+  memory::stAram.reset();
+  memory::stBrom.reset();
+  memory::stBram.reset();
+  memory::gbrom.reset();
+  memory::gbram.reset();
+
+  if(loaded() == false) return;
+  bus.unload_cart();
+  set(loaded, false);
+}
+
+Cartridge::Type Cartridge::detect_image_type(uint8_t *data, unsigned size) const {
+  cartinfo_t info;
+  read_header(info, data, size);
+  return info.type;
+}
+
+Cartridge::Cartridge() {
+  set(loaded, false);
+  unload();
+}
+
+Cartridge::~Cartridge() {
+  unload();
+}
+
+void Cartridge::set_cartinfo(const Cartridge::cartinfo_t &source) {
+  set(region,         source.region);
+  set(mapper,         source.mapper);
+  set(dsp1_mapper,    source.dsp1_mapper);
+
+  set(has_bsx_slot,   source.bsx_slot);
+  set(has_superfx,    source.superfx);
+  set(has_sa1,        source.sa1);
+  set(has_srtc,       source.srtc);
+  set(has_sdd1,       source.sdd1);
+  set(has_spc7110,    source.spc7110);
+  set(has_spc7110rtc, source.spc7110rtc);
+  set(has_cx4,        source.cx4);
+  set(has_dsp1,       source.dsp1);
+  set(has_dsp2,       source.dsp2);
+  set(has_dsp3,       source.dsp3);
+  set(has_dsp4,       source.dsp4);
+  set(has_obc1,       source.obc1);
+  set(has_st010,      source.st010);
+  set(has_st011,      source.st011);
+  set(has_st018,      source.st018);
+}
+
+//==========
+//cartinfo_t
+//==========
+
+void Cartridge::cartinfo_t::reset() {
+  type        = TypeUnknown;
+  mapper      = LoROM;
+  dsp1_mapper = DSP1Unmapped;
+  region      = NTSC;
+
+  rom_size = 0;
+  ram_size = 0;
+
+  bsx_slot   = false;
+  superfx    = false;
+  sa1        = false;
+  srtc       = false;
+  sdd1       = false;
+  spc7110    = false;
+  spc7110rtc = false;
+  cx4        = false;
+  dsp1       = false;
+  dsp2       = false;
+  dsp3       = false;
+  dsp4       = false;
+  obc1       = false;
+  st010      = false;
+  st011      = false;
+  st018      = false;
+}
+
+Cartridge::cartinfo_t::cartinfo_t() {
+  reset();
+}
+
+};
+

src/cartridge/cartridge.hpp

@@ -0,0 +1,131 @@
+class Cartridge : public property {
+public:
+  enum Mode {
+    ModeNormal,
+    ModeBsxSlotted,
+    ModeBsx,
+    ModeSufamiTurbo,
+    ModeSuperGameBoy,
+  };
+
+  enum Type {
+    TypeNormal,
+    TypeBsxSlotted,
+    TypeBsxBios,
+    TypeBsx,
+    TypeSufamiTurboBios,
+    TypeSufamiTurbo,
+    TypeSuperGameBoyBios,
+    TypeGameBoy,
+    TypeUnknown,
+  };
+
+  enum Region {
+    NTSC,
+    PAL,
+  };
+
+  enum MemoryMapper {
+    LoROM,
+    HiROM,
+    ExLoROM,
+    ExHiROM,
+    SuperFXROM,
+    SA1ROM,
+    SPC7110ROM,
+    BSCLoROM,
+    BSCHiROM,
+    BSXROM,
+    STROM,
+  };
+
+  enum DSP1MemoryMapper {
+    DSP1Unmapped,
+    DSP1LoROM1MB,
+    DSP1LoROM2MB,
+    DSP1HiROM,
+  };
+
+  //properties can be read via operator(), eg "if(cartridge.loaded() == true)";
+  //warning: if loaded() == false, no other property is considered valid!
+
+  property_t<bool> loaded;  //is a base cartridge inserted?
+
+  property_t<Mode>             mode;
+  property_t<Region>           region;
+  property_t<MemoryMapper>     mapper;
+  property_t<DSP1MemoryMapper> dsp1_mapper;
+
+  property_t<bool> has_bsx_slot;
+  property_t<bool> has_superfx;
+  property_t<bool> has_sa1;
+  property_t<bool> has_srtc;
+  property_t<bool> has_sdd1;
+  property_t<bool> has_spc7110, has_spc7110rtc;
+  property_t<bool> has_cx4;
+  property_t<bool> has_dsp1, has_dsp2, has_dsp3, has_dsp4;
+  property_t<bool> has_obc1;
+  property_t<bool> has_st010, has_st011, has_st018;
+
+  //main interface
+  void load(Mode);
+//void read();
+//void load();
+  void unload();
+  Type detect_image_type(uint8_t *data, unsigned size) const;
+
+  Cartridge();
+  ~Cartridge();
+
+private:
+  struct cartinfo_t {
+    Type type;
+    Region region;
+    MemoryMapper mapper;
+    DSP1MemoryMapper dsp1_mapper;
+    unsigned rom_size, ram_size;
+
+    bool bsx_slot;
+    bool superfx;
+    bool sa1;
+    bool srtc;
+    bool sdd1;
+    bool spc7110, spc7110rtc;
+    bool cx4;
+    bool dsp1, dsp2, dsp3, dsp4;
+    bool obc1;
+    bool st010, st011, st018;
+
+    void reset();
+    cartinfo_t();
+  };
+
+  enum HeaderField {
+    CartName    = 0x00,
+    Mapper      = 0x15,
+    RomType     = 0x16,
+    RomSize     = 0x17,
+    RamSize     = 0x18,
+    CartRegion  = 0x19,
+    Company     = 0x1a,
+    Version     = 0x1b,
+    Complement  = 0x1c,  //inverse checksum
+    Checksum    = 0x1e,
+    ResetVector = 0x3c,
+  };
+
+  void read_header(cartinfo_t &info, const uint8_t *data, unsigned size) const;
+  unsigned find_header(const uint8_t *data, unsigned size) const;
+  unsigned score_header(const uint8_t *data, unsigned size, unsigned addr) const;
+  void set_cartinfo(const cartinfo_t&);
+};
+
+namespace memory {
+  extern MappedRAM cartrom, cartram, cartrtc;
+  extern MappedRAM bsxflash, bsxram, bsxpram;
+  extern MappedRAM stArom, stAram;
+  extern MappedRAM stBrom, stBram;
+  extern MappedRAM gbrom, gbram;
+};
+
+extern Cartridge cartridge;

src/cartridge/header.cpp

@@ -1,16 +1,43 @@
-#ifdef CART_CPP
+#ifdef CARTRIDGE_CPP
 
-void Cartridge::read_header(cartinfo_t &info, const uint8_t *data, unsigned size) {
+void Cartridge::read_header(cartinfo_t &info, const uint8_t *data, unsigned size) const {
   info.reset();
-  unsigned index = find_header(data, size);
 
+  //=====================
+  //detect Game Boy carts
+  //=====================
+
+  if(size >= 0x0140) {
+    if(data[0x0104] == 0xce && data[0x0105] == 0xed && data[0x0106] == 0x66 && data[0x0107] == 0x66
+    && data[0x0108] == 0xcc && data[0x0109] == 0x0d && data[0x010a] == 0x00 && data[0x010b] == 0x0b) {
+      info.type = TypeGameBoy;
+      return;
+    }
+  }
+
+  const unsigned index = find_header(data, size);
+  const uint8 mapper   = data[index + Mapper];
+  const uint8 rom_type = data[index + RomType];
+  const uint8 rom_size = data[index + RomSize];
+  const uint8 company  = data[index + Company];
+  const uint8 region   = data[index + CartRegion] & 0x7f;
+
+  info.ram_size = 1024 << (data[index + RamSize] & 7);
+  if(info.ram_size == 1024) info.ram_size = 0;  //no RAM present, eg RamSize == 0
+
+  //0, 1, 13 = NTSC; 2 - 12 = PAL
+  info.region = (region <= 1 || region >= 13) ? NTSC : PAL;
+
+  //=======================
   //detect BS-X flash carts
+  //=======================
+
   if(data[index + 0x13] == 0x00 || data[index + 0x13] == 0xff) {
     if(data[index + 0x14] == 0x00) {
       const uint8_t n15 = data[index + 0x15];
       if(n15 == 0x00 || n15 == 0x80 || n15 == 0x84 || n15 == 0x9c || n15 == 0xbc || n15 == 0xfc) {
         if(data[index + 0x1a] == 0x33 || data[index + 0x1a] == 0xff) {
-          info.type = TypeBSX;
+          info.type = TypeBsx;
           info.mapper = BSXROM;
           info.region = NTSC;  //BS-X only released in Japan
           return;
@@ -19,24 +46,33 @@ void Cartridge::read_header(cartinfo_t &info, const uint8_t *data, unsigned size
     }
   }
 
+  //=========================
   //detect Sufami Turbo carts
+  //=========================
+
   if(!memcmp(data, "BANDAI SFC-ADX", 14)) {
     if(!memcmp(data + 16, "SFC-ADX BACKUP", 14)) {
-      info.type = TypeSufamiTurboBIOS;
+      info.type = TypeSufamiTurboBios;
     } else {
       info.type = TypeSufamiTurbo;
     }
     info.mapper = STROM;
     info.region = NTSC;  //Sufami Turbo only released in Japan
+    return;              //RAM size handled internally by load_cart_st();
+  }
+
+  //==========================
+  //detect Super Game Boy BIOS
+  //==========================
+
+  if(!memcmp(data + index, "Super GAMEBOY", 13)) {
+    info.type = TypeSuperGameBoyBios;
     return;
   }
 
-  //standard cart
-  uint8 mapper   = data[index + MAPPER];
-  uint8 rom_type = data[index + ROM_TYPE];
-  uint8 rom_size = data[index + ROM_SIZE];
-  uint8 company  = data[index + COMPANY];
-  uint8 region   = data[index + REGION] & 0x7f;
+  //=====================
+  //detect standard carts
+  //=====================
 
   //detect presence of BS-X flash cartridge connector (reads extended header information)
   if(data[index - 14] == 'Z') {
@@ -44,24 +80,25 @@ void Cartridge::read_header(cartinfo_t &info, const uint8_t *data, unsigned size
       uint8 n13 = data[index - 13];
       if((n13 >= 'A' && n13 <= 'Z') || (n13 >= '0' && n13 <= '9')) {
         if(company == 0x33 || (data[index - 10] == 0x00 && data[index - 4] == 0x00)) {
-          info.bsxslot = true;
+          info.bsx_slot = true;
         }
       }
     }
   }
 
-  if(info.bsxslot == true) {
+  if(info.bsx_slot == true) {
     if(!memcmp(data + index, "Satellaview BS-X     ", 21)) {
       //BS-X base cart
-      info.type = TypeBSXBIOS;
+      info.type = TypeBsxBios;
       info.mapper = BSXROM;
+      info.region = NTSC;  //BS-X only released in Japan
+      return;              //RAM size handled internally by load_cart_bsx() -> BSXCart class
     } else {
-      info.type = TypeBSC;
+      info.type = TypeBsxSlotted;
       info.mapper = (index == 0x7fc0 ? BSCLoROM : BSCHiROM);
     }
-    return;
-  }
-
+  } else {
+    //standard cart
     info.type = TypeNormal;
 
     if(index == 0x7fc0 && size >= 0x401000) {
@@ -75,13 +112,18 @@ void Cartridge::read_header(cartinfo_t &info, const uint8_t *data, unsigned size
     } else {  //index == 0x40ffc0
       info.mapper = ExHiROM;
     }
+  }
 
   if(mapper == 0x20 && (rom_type == 0x13 || rom_type == 0x14 || rom_type == 0x15 || rom_type == 0x1a)) {
     info.superfx = true;
+    info.mapper = SuperFXROM;
+    info.ram_size = 1024 << (data[index - 3] & 7);
+    if(info.ram_size == 1024) info.ram_size = 0;
   }
 
-  if(mapper == 0x23 && (rom_type == 0x34 || rom_type == 0x35)) {
+  if(mapper == 0x23 && (rom_type == 0x32 || rom_type == 0x34 || rom_type == 0x35)) {
     info.sa1 = true;
+    info.mapper = SA1ROM;
   }
 
   if(mapper == 0x35 && rom_type == 0x55) {
@@ -151,18 +193,9 @@ void Cartridge::read_header(cartinfo_t &info, const uint8_t *data, unsigned size
   if(mapper == 0x30 && rom_type == 0xf5) {
     info.st018 = true;
   }
-
-  if(data[index + RAM_SIZE] & 7) {
-    info.ram_size = 1024 << (data[index + RAM_SIZE] & 7);
-  } else {
-    info.ram_size = 0;
-  }
-
-  //0, 1, 13 = NTSC; 2 - 12 = PAL
-  info.region = (region <= 1 || region >= 13) ? NTSC : PAL;
 }
 
-unsigned Cartridge::find_header(const uint8_t *data, unsigned size) {
+unsigned Cartridge::find_header(const uint8_t *data, unsigned size) const {
   unsigned score_lo = score_header(data, size, 0x007fc0);
   unsigned score_hi = score_header(data, size, 0x00ffc0);
   unsigned score_ex = score_header(data, size, 0x40ffc0);
@@ -177,16 +210,16 @@ unsigned Cartridge::find_header(const uint8_t *data, unsigned size) {
   }
 }
 
-unsigned Cartridge::score_header(const uint8_t *data, unsigned size, unsigned addr) {
+unsigned Cartridge::score_header(const uint8_t *data, unsigned size, unsigned addr) const {
   if(size < addr + 64) return 0;  //image too small to contain header at this location?
   int score = 0;
 
-  uint16 resetvector = data[addr + RESETV] | (data[addr + RESETV + 1] << 8);
-  uint16 checksum    = data[addr +  CKSUM] | (data[addr +  CKSUM + 1] << 8);
-  uint16 ichecksum   = data[addr + ICKSUM] | (data[addr + ICKSUM + 1] << 8);
+  uint16 resetvector = data[addr + ResetVector] | (data[addr + ResetVector + 1] << 8);
+  uint16 checksum    = data[addr + Checksum   ] | (data[addr + Checksum    + 1] << 8);
+  uint16 complement  = data[addr + Complement ] | (data[addr + Complement  + 1] << 8);
 
   uint8 resetop = data[(addr & ~0x7fff) | (resetvector & 0x7fff)];  //first opcode executed upon reset
-  uint8 mapper  = data[addr + MAPPER] & ~0x10; //mask off irrelevent FastROM-capable bit
+  uint8 mapper  = data[addr + Mapper] & ~0x10;                      //mask off irrelevent FastROM-capable bit
 
   //$00:[000-7fff] contains uninitialized RAM and MMIO.
   //reset vector must point to ROM at $00:[8000-ffff] to be considered valid.
@@ -241,21 +274,21 @@ unsigned Cartridge::score_header(const uint8_t *data, unsigned size, unsigned ad
   //fallback and rely on info validity in these cases to determine more likely header.
 
   //a valid checksum is the biggest indicator of a valid header.
-  if((checksum + ichecksum) == 0xffff && (checksum != 0) && (ichecksum != 0)) score += 4;
+  if((checksum + complement) == 0xffff && (checksum != 0) && (complement != 0)) score += 4;
 
   if(addr == 0x007fc0 && mapper == 0x20) score += 2;  //0x20 is usually LoROM
   if(addr == 0x00ffc0 && mapper == 0x21) score += 2;  //0x21 is usually HiROM
   if(addr == 0x007fc0 && mapper == 0x22) score += 2;  //0x22 is usually ExLoROM
   if(addr == 0x40ffc0 && mapper == 0x25) score += 2;  //0x25 is usually ExHiROM
 
-  if(data[addr + COMPANY] == 0x33) score += 2; //0x33 indicates extended header
-  if(data[addr + ROM_TYPE] < 0x08) score++;
-  if(data[addr + ROM_SIZE] < 0x10) score++;
-  if(data[addr + RAM_SIZE] < 0x08) score++;
-  if(data[addr + REGION] < 14) score++;
+  if(data[addr + Company] == 0x33) score += 2;        //0x33 indicates extended header
+  if(data[addr + RomType] < 0x08) score++;
+  if(data[addr + RomSize] < 0x10) score++;
+  if(data[addr + RamSize] < 0x08) score++;
+  if(data[addr + CartRegion] < 14) score++;
 
   if(score < 0) score = 0;
   return score;
 }
 
-#endif //ifdef CART_CPP
+#endif

src/cc.bat

@@ -1,3 +1,5 @@
-@make platform=win compiler=mingw32-gcc
-::@make platform=win compiler=mingw32-gcc enable_gzip=true enable_jma=true
+@mingw32-make
+
+::@mingw32-make enable_gzip=true enable_jma=true
+
 @pause

src/cc.sh

@@ -1,2 +0,0 @@
-make platform=x compiler=gcc
-#make platform=x compiler=gcc enable_gzip=true enable_jma=true

src/cheat/cheat.cpp

@@ -1,13 +1,23 @@
-#include "../base.h"
+#include <../base.hpp>
+
+#define CHEAT_CPP
+namespace SNES {
 
 Cheat cheat;
 
 Cheat::cheat_t& Cheat::cheat_t::operator=(const Cheat::cheat_t& source) {
   enabled = source.enabled;
-  addr    = source.addr;
-  data    = source.data;
   code = source.code;
   desc = source.desc;
+  count = source.count;
+
+  addr.reset();
+  data.reset();
+  for(unsigned n = 0; n < count; n++) {
+    addr[n] = source.addr[n];
+    data[n] = source.data[n];
+  }
+
   return *this;
 }
 
@@ -16,14 +26,206 @@ bool Cheat::cheat_t::operator<(const Cheat::cheat_t& source) {
   return strcmp(desc, source.desc) < 0;
 }
 
-/*****
- * string <> binary code translation routines
- * decode() "7e1234:56" ->  0x7e123456
- * encode()  0x7e123456 -> "7e1234:56"
- *****/
+//parse item ("0123-4567+89AB-CDEF"), return cheat_t item
+//return true if code is valid, false otherwise
+bool Cheat::decode(const char *s, Cheat::cheat_t &item) const {
+  item.enabled = false;
+  item.count = 0;
 
-bool Cheat::decode(const char *str, unsigned &addr, uint8 &data, type_t &type) {
-  string t = str;
+  lstring list;
+  list.split("+", s);
+
+  for(unsigned n = 0; n < list.size(); n++) {
+    unsigned addr;
+    uint8_t data;
+    type_t type;
+    if(decode(list[n], addr, data, type) == false) return false;
+
+    item.addr[item.count] = addr;
+    item.data[item.count] = data;
+    item.count++;
+  }
+
+  return true;
+}
+
+//read() is used by MemBus::read() if Cheat::enabled(addr) returns true to look up cheat code.
+//returns true if cheat code was found, false if it was not.
+//when true, cheat code substitution value is stored in data.
+bool Cheat::read(unsigned addr, uint8_t &data) const {
+  addr = mirror_address(addr);
+  for(unsigned i = 0; i < code.size(); i++) {
+    if(enabled(i) == false) continue;
+
+    for(unsigned n = 0; n < code[i].count; n++) {
+      if(addr == mirror_address(code[i].addr[n])) {
+        data = code[i].data[n];
+        return true;
+      }
+    }
+  }
+
+  //code not found, or code is disabled
+  return false;
+}
+
+//==============
+//master control
+//==============
+
+//global cheat system enable/disable:
+//if disabled, *all* cheat codes are disabled;
+//otherwise only individually disabled codes are.
+
+bool Cheat::enabled() const {
+  return cheat_system_enabled;
+}
+
+void Cheat::enable() {
+  cheat_system_enabled = true;
+  cheat_enabled = (cheat_system_enabled && cheat_enabled_code_exists);
+}
+
+void Cheat::disable() {
+  cheat_system_enabled = false;
+  cheat_enabled = false;
+}
+
+//================================
+//cheat list manipulation routines
+//================================
+
+bool Cheat::add(bool enable, const char *code_, const char *desc_) {
+  cheat_t item;
+  if(decode(code_, item) == false) return false;
+
+  unsigned i = code.size();
+  code[i] = item;
+  code[i].enabled = enable;
+  code[i].desc = desc_;
+  code[i].code = code_;
+  encode_description(code[i].desc);
+  update(code[i]);
+
+  update_cheat_status();
+  return true;
+}
+
+bool Cheat::edit(unsigned i, bool enable, const char *code_, const char *desc_) {
+  cheat_t item;
+  if(decode(code_, item) == false) return false;
+
+  //disable current code and clear from code lookup table
+  code[i].enabled = false;
+  update(code[i]);
+
+  code[i] = item;
+  code[i].enabled = enable;
+  code[i].desc = desc_;
+  code[i].code = code_;
+  encode_description(code[i].desc);
+  update(code[i]);
+
+  update_cheat_status();
+  return true;
+}
+
+bool Cheat::remove(unsigned i) {
+  unsigned size = code.size();
+  if(i >= size) return false;  //also verifies size cannot be < 1
+
+  for(unsigned n = i; n < size - 1; n++) code[n] = code[n + 1];
+  code.resize(size - 1);
+
+  update_cheat_status();
+  return true;
+}
+
+bool Cheat::get(unsigned i, cheat_t &item) const {
+  if(i >= code.size()) return false;
+
+  item = code[i];
+  decode_description(item.desc);
+  return true;
+}
+
+//==============================
+//cheat status modifier routines
+//==============================
+
+bool Cheat::enabled(unsigned i) const {
+  return (i < code.size() ? code[i].enabled : false);
+}
+
+void Cheat::enable(unsigned i) {
+  if(i >= code.size()) return;
+
+  code[i].enabled = true;
+  update(code[i]);
+  update_cheat_status();
+}
+
+void Cheat::disable(unsigned i) {
+  if(i >= code.size()) return;
+
+  code[i].enabled = false;
+  update(code[i]);
+  update_cheat_status();
+}
+
+//===============================
+//cheat file load / save routines
+//
+//file format:
+//"description", status, nnnn-nnnn[+nnnn-nnnn...]\r\n
+//...
+//===============================
+
+void Cheat::load(string data) {
+  data.replace("\r\n", "\n");
+  data.qreplace(" ", "");
+
+  lstring line;
+  line.split("\n", data);
+  for(unsigned i = 0; i < line.size(); i++) {
+    lstring part;
+    part.qsplit(",", line[i]);
+    if(part.size() != 3) continue;
+    trim(part[0], "\"");
+    add(part[1] == "enabled", /* code = */ part[2], /* desc = */ part[0]);
+  }
+}
+
+string Cheat::save() const {
+  string data;
+  for(unsigned i = 0; i < code.size(); i++) {
+    data << "\"" << code[i].desc << "\", "
+         << (code[i].enabled ? "enabled, " : "disabled, ")
+         << code[i].code << "\r\n";
+  }
+  return data;
+}
+
+void Cheat::clear() {
+  cheat_enabled_code_exists = false;
+  memset(mask, 0, 0x200000);
+  code.reset();
+}
+
+Cheat::Cheat() : cheat_system_enabled(true) {
+  clear();
+}
+
+//==================
+//internal functions
+//==================
+
+//string <> binary code translation routines
+//decode() "7e123456" -> 0x7e123456
+//encode() 0x7e123456 -> "7e123456"
+
+bool Cheat::decode(const char *s, unsigned &addr, uint8_t &data, type_t &type) const {
+  string t = s;
   strlower(t);
 
   #define ischr(n) ((n >= '0' && n <= '9') || (n >= 'a' && n <= 'f'))
@@ -51,18 +253,18 @@ bool Cheat::decode(const char *str, unsigned &addr, uint8 &data, type_t &type) {
     //8421 8421 8421 8421 8421 8421
     //abcd efgh ijkl mnop qrst uvwx
     //ijkl qrst opab cduv wxef ghmn
-    addr = (!!(r & 0x002000) << 23) | (!!(r & 0x001000) << 22) |
-           (!!(r & 0x000800) << 21) | (!!(r & 0x000400) << 20) |
-           (!!(r & 0x000020) << 19) | (!!(r & 0x000010) << 18) |
-           (!!(r & 0x000008) << 17) | (!!(r & 0x000004) << 16) |
-           (!!(r & 0x800000) << 15) | (!!(r & 0x400000) << 14) |
-           (!!(r & 0x200000) << 13) | (!!(r & 0x100000) << 12) |
-           (!!(r & 0x000002) << 11) | (!!(r & 0x000001) << 10) |
-           (!!(r & 0x008000) <<  9) | (!!(r & 0x004000) <<  8) |
-           (!!(r & 0x080000) <<  7) | (!!(r & 0x040000) <<  6) |
-           (!!(r & 0x020000) <<  5) | (!!(r & 0x010000) <<  4) |
-           (!!(r & 0x000200) <<  3) | (!!(r & 0x000100) <<  2) |
-           (!!(r & 0x000080) <<  1) | (!!(r & 0x000040) <<  0);
+    addr = (!!(r & 0x002000) << 23) | (!!(r & 0x001000) << 22)
+         | (!!(r & 0x000800) << 21) | (!!(r & 0x000400) << 20)
+         | (!!(r & 0x000020) << 19) | (!!(r & 0x000010) << 18)
+         | (!!(r & 0x000008) << 17) | (!!(r & 0x000004) << 16)
+         | (!!(r & 0x800000) << 15) | (!!(r & 0x400000) << 14)
+         | (!!(r & 0x200000) << 13) | (!!(r & 0x100000) << 12)
+         | (!!(r & 0x000002) << 11) | (!!(r & 0x000001) << 10)
+         | (!!(r & 0x008000) <<  9) | (!!(r & 0x004000) <<  8)
+         | (!!(r & 0x080000) <<  7) | (!!(r & 0x040000) <<  6)
+         | (!!(r & 0x020000) <<  5) | (!!(r & 0x010000) <<  4)
+         | (!!(r & 0x000200) <<  3) | (!!(r & 0x000100) <<  2)
+         | (!!(r & 0x000080) <<  1) | (!!(r & 0x000040) <<  0);
     data = r >> 24;
     return true;
   } else {
@@ -70,43 +272,54 @@ bool Cheat::decode(const char *str, unsigned &addr, uint8 &data, type_t &type) {
   }
 }
 
-bool Cheat::encode(string &str, unsigned addr, uint8 data, type_t type) {
+bool Cheat::encode(string &s, unsigned addr, uint8_t data, type_t type) const {
   char t[16];
 
   if(type == ProActionReplay) {
-    sprintf(t, "%0.6x:%0.2x", addr, data);
-    str = t;
+    sprintf(t, "%.6x%.2x", addr, data);
+    s = t;
     return true;
   } else if(type == GameGenie) {
     unsigned r = addr;
-    addr = (!!(r & 0x008000) << 23) | (!!(r & 0x004000) << 22) |
-           (!!(r & 0x002000) << 21) | (!!(r & 0x001000) << 20) |
-           (!!(r & 0x000080) << 19) | (!!(r & 0x000040) << 18) |
-           (!!(r & 0x000020) << 17) | (!!(r & 0x000010) << 16) |
-           (!!(r & 0x000200) << 15) | (!!(r & 0x000100) << 14) |
-           (!!(r & 0x800000) << 13) | (!!(r & 0x400000) << 12) |
-           (!!(r & 0x200000) << 11) | (!!(r & 0x100000) << 10) |
-           (!!(r & 0x000008) <<  9) | (!!(r & 0x000004) <<  8) |
-           (!!(r & 0x000002) <<  7) | (!!(r & 0x000001) <<  6) |
-           (!!(r & 0x080000) <<  5) | (!!(r & 0x040000) <<  4) |
-           (!!(r & 0x020000) <<  3) | (!!(r & 0x010000) <<  2) |
-           (!!(r & 0x000800) <<  1) | (!!(r & 0x000400) <<  0);
-    sprintf(t, "%0.2x%0.2x-%0.4x", data, addr >> 16, addr & 0xffff);
+    addr = (!!(r & 0x008000) << 23) | (!!(r & 0x004000) << 22)
+         | (!!(r & 0x002000) << 21) | (!!(r & 0x001000) << 20)
+         | (!!(r & 0x000080) << 19) | (!!(r & 0x000040) << 18)
+         | (!!(r & 0x000020) << 17) | (!!(r & 0x000010) << 16)
+         | (!!(r & 0x000200) << 15) | (!!(r & 0x000100) << 14)
+         | (!!(r & 0x800000) << 13) | (!!(r & 0x400000) << 12)
+         | (!!(r & 0x200000) << 11) | (!!(r & 0x100000) << 10)
+         | (!!(r & 0x000008) <<  9) | (!!(r & 0x000004) <<  8)
+         | (!!(r & 0x000002) <<  7) | (!!(r & 0x000001) <<  6)
+         | (!!(r & 0x080000) <<  5) | (!!(r & 0x040000) <<  4)
+         | (!!(r & 0x020000) <<  3) | (!!(r & 0x010000) <<  2)
+         | (!!(r & 0x000800) <<  1) | (!!(r & 0x000400) <<  0);
+    sprintf(t, "%.2x%.2x-%.4x", data, addr >> 16, addr & 0xffff);
     strtr(t, "0123456789abcdef", "df4709156bc8a23e");
-    str = t;
+    s = t;
     return true;
   } else {
     return false;
   }
 }
 
-/*****
- * address lookup table manipulation and mirroring
- * mirror_address() 0x000000 -> 0x7e0000
- * set() enable specified address, mirror accordingly
- * clear() disable specified address, mirror accordingly
- *****/
+//speed up S-CPU memory reads by disabling cheat code lookup when either:
+//a) cheat system is disabled by user, or b) no enabled cheat codes exist
+void Cheat::update_cheat_status() {
+  for(unsigned i = 0; i < code.size(); i++) {
+    if(code[i].enabled) {
+      cheat_enabled_code_exists = true;
+      cheat_enabled = (cheat_system_enabled && cheat_enabled_code_exists);
+      return;
+    }
+  }
+  cheat_enabled_code_exists = false;
+  cheat_enabled = false;
+}
 
+//address lookup table manipulation and mirroring
+//mirror_address() 0x000000 -> 0x7e0000
+//set() enable specified address, mirror accordingly
+//clear() disable specified address, mirror accordingly
 unsigned Cheat::mirror_address(unsigned addr) const {
   if((addr & 0x40e000) != 0x0000) return addr;
   //8k WRAM mirror
@@ -114,6 +327,14 @@ unsigned Cheat::mirror_address(unsigned addr) const {
   return (0x7e0000 + (addr & 0x1fff));
 }
 
+//updates mask[] table enabled bits;
+//must be called after modifying item.enabled state.
+void Cheat::update(const cheat_t &item) {
+  for(unsigned n = 0; n < item.count; n++) {
+    (item.enabled) ? set(item.addr[n]) : clear(item.addr[n]);
+  }
+}
+
 void Cheat::set(unsigned addr) {
   addr = mirror_address(addr);
 
@@ -136,7 +357,7 @@ void Cheat::clear(unsigned addr) {
   //if there is more than one cheat code using the same address,
   //(eg with a different override value) then do not clear code
   //lookup table entry.
-  uint8 r;
+  uint8_t r;
   if(read(addr, r) == true) return;
 
   mask[addr >> 3] &= ~(1 << (addr & 7));
@@ -152,185 +373,19 @@ void Cheat::clear(unsigned addr) {
   }
 }
 
-/*****
- * read() is used by MemBus::read() if Cheat::enabled(addr)
- * returns true to look up cheat code.
- * returns true if cheat code was found, false if it was not.
- * when true, cheat code substitution value is stored in data.
- *****/
+//these two functions are used to safely store description text inside .cfg file format.
 
-bool Cheat::read(unsigned addr, uint8 &data) const {
-  addr = mirror_address(addr);
-  for(unsigned i = 0; i < code.size(); i++) {
-    if(enabled(i) == false) continue;
-    if(addr == mirror_address(code[i].addr)) {
-      data = code[i].data;
-      return true;
-    }
-  }
-  //code not found, or code is disabled
-  return false;
+string& Cheat::encode_description(string &desc) const {
+  desc.replace("\"", "\\q");
+  desc.replace("\n", "\\n");
+  return desc;
 }
 
-/*****
- * update_cheat_status() will scan to see if any codes are
- * enabled. if any are, make sure the cheat system is on.
- * otherwise, turn cheat system off to speed up emulation.
- *****/
-
-void Cheat::update_cheat_status() {
-  for(unsigned i = 0; i < code.size(); i++) {
-    if(code[i].enabled) {
-      cheat_system_enabled = true;
-      return;
-    }
-  }
-  cheat_system_enabled = false;
+string& Cheat::decode_description(string &desc) const {
+  desc.replace("\\q", "\"");
+  desc.replace("\\n", "\n");
+  return desc;
 }
 
-/*****
- * cheat list manipulation routines
- *****/
+};
 
-bool Cheat::add(bool enable, const char *code_, const char *desc_) {
-  unsigned addr;
-  uint8    data;
-  type_t   type;
-  if(decode(code_, addr, data, type) == false) return false;
-
-  unsigned n = code.size();
-  code[n].enabled = enable;
-  code[n].addr = addr;
-  code[n].data = data;
-  code[n].code = code_;
-  code[n].desc = desc_;
-  (enable) ? set(addr) : clear(addr);
-
-  update_cheat_status();
-  return true;
-}
-
-bool Cheat::edit(unsigned n, bool enable, const char *code_, const char *desc_) {
-  unsigned addr;
-  uint8    data;
-  type_t   type;
-  if(decode(code_, addr, data, type) == false) return false;
-
-  //disable current code and clear from code lookup table
-  code[n].enabled = false;
-  clear(code[n].addr);
-
-  //update code and enable in code lookup table
-  code[n].enabled = enable;
-  code[n].addr = addr;
-  code[n].data = data;
-  code[n].code = code_;
-  code[n].desc = desc_;
-  set(addr);
-
-  update_cheat_status();
-  return true;
-}
-
-bool Cheat::remove(unsigned n) {
-  unsigned size = code.size();
-  if(n >= size) return false; //also verifies size cannot be < 1
-
-  for(unsigned i = n; i < size - 1; i++) code[i] = code[i + 1];
-  code.resize(size - 1);
-
-  update_cheat_status();
-  return true;
-}
-
-bool Cheat::get(unsigned n, cheat_t &cheat) const {
-  if(n >= code.size()) return false;
-
-  cheat = code[n];
-  return true;
-}
-
-/*****
- * code status modifier routines
- *****/
-
-bool Cheat::enabled(unsigned n) const {
-  return (n < code.size()) ? code[n].enabled : false;
-}
-
-void Cheat::enable(unsigned n) {
-  if(n >= code.size()) return;
-
-  code[n].enabled = true;
-  set(code[n].addr);
-  update_cheat_status();
-}
-
-void Cheat::disable(unsigned n) {
-  if(n >= code.size()) return;
-
-  code[n].enabled = false;
-  clear(code[n].addr);
-  update_cheat_status();
-}
-
-/*****
- * cheat file manipulation routines
- *****/
-
-/* file format: */
-/* nnnn-nnnn = status, "description" \r\n */
-/* ... */
-
-bool Cheat::load(const char *fn) {
-  string data;
-  if(!fread(data, fn)) return false;
-  replace(data, "\r\n", "\n");
-  qreplace(data, "=", ",");
-  qreplace(data, " ", "");
-
-  lstring line;
-  split(line, "\n", data);
-  for(unsigned i = 0; i < ::count(line); i++) {
-    lstring part;
-    split(part, ",", line[i]);
-    if(::count(part) != 3) continue;
-    trim(part[2], "\"");
-    add(part[1] == "enabled", part[0], part[2]);
-  }
-
-  return true;
-}
-
-bool Cheat::save(const char *fn) const {
-  file fp;
-  if(!fp.open(fn, file::mode_write)) return false;
-  for(unsigned i = 0; i < code.size(); i++) {
-    fp.print(string()
-      << code[i].code << " = "
-      << (code[i].enabled ? "enabled" : "disabled") << ", "
-      << "\"" << code[i].desc << "\""
-      << "\r\n");
-  }
-  fp.close();
-  return true;
-}
-
-void Cheat::sort() {
-  if(code.size() <= 1) return;  //nothing to sort?
-  cheat_t *buffer = new cheat_t[code.size()];
-  for(unsigned i = 0; i < code.size(); i++) buffer[i] = code[i];
-  nall::sort(buffer, code.size());
-  for(unsigned i = 0; i < code.size(); i++) code[i] = buffer[i];
-  delete[] buffer;
-}
-
-void Cheat::clear() {
-  cheat_system_enabled = false;
-  memset(mask, 0, 0x200000);
-  code.reset();
-}
-
-Cheat::Cheat() {
-  clear();
-}

src/cheat/cheat.h

@@ -1,55 +0,0 @@
-class Cheat {
-public:
-  enum type_t {
-    ProActionReplay,
-    GameGenie,
-  };
-
-  struct cheat_t {
-    bool     enabled;
-    unsigned addr;
-    uint8    data;
-    string   code;
-    string   desc;
-
-    cheat_t& operator=(const cheat_t&);
-    bool operator<(const cheat_t&);
-  };
-
-  static bool decode(const char *str, unsigned &addr, uint8 &data, type_t &type);
-  static bool encode(string &str, unsigned addr, uint8 data, type_t type);
-
-  inline bool enabled() const { return cheat_system_enabled; }
-  inline unsigned count() const { return code.size(); }
-  inline bool exists(unsigned addr) const { return bool(mask[addr >> 3] & 1 << (addr & 7)); }
-
-  bool read(unsigned addr, uint8 &data) const;
-
-  bool add(bool enable, const char *code, const char *desc);
-  bool edit(unsigned n, bool enable, const char *code, const char *desc);
-  bool get(unsigned n, cheat_t &cheat) const;
-  bool remove(unsigned n);
-  bool enabled(unsigned n) const;
-  void enable(unsigned n);
-  void disable(unsigned n);
-
-  bool load(const char *fn);
-  bool save(const char *fn) const;
-
-  void sort();
-  void clear();
-
-  Cheat();
-
-private:
-  bool cheat_system_enabled;
-  uint8 mask[0x200000];
-  vector<cheat_t> code;
-
-  void update_cheat_status();
-  unsigned mirror_address(unsigned addr) const;
-  void set(unsigned addr);
-  void clear(unsigned addr);
-};
-
-extern Cheat cheat;

src/cheat/cheat.hpp

@@ -0,0 +1,69 @@
+class Cheat {
+public:
+  enum type_t {
+    ProActionReplay,
+    GameGenie,
+  };
+
+  struct cheat_t {
+    bool enabled;
+    string code;
+    string desc;
+
+    unsigned count;
+    array<unsigned> addr;
+    array<uint8_t> data;
+
+    cheat_t& operator=(const cheat_t&);
+    bool operator<(const cheat_t&);
+  };
+
+  bool decode(const char *s, cheat_t &item) const;
+  bool read(unsigned addr, uint8_t &data) const;
+
+  bool enabled() const;
+  void enable();
+  void disable();
+
+  inline unsigned count() const { return code.size(); }
+  inline bool active() const { return cheat_enabled; }
+  inline bool exists(unsigned addr) const { return mask[addr >> 3] & 1 << (addr & 7); }
+
+  bool add(bool enable, const char *code, const char *desc);
+  bool edit(unsigned i, bool enable, const char *code, const char *desc);
+  bool remove(unsigned i);
+  bool get(unsigned i, cheat_t &item) const;
+
+  bool enabled(unsigned i) const;
+  void enable(unsigned i);
+  void disable(unsigned i);
+
+  void load(string data);
+  string save() const;
+  void clear();
+
+  Cheat();
+
+private:
+  bool cheat_enabled;  //cheat_enabled == (cheat_enabled_code_exists && cheat_system_enabled);
+  bool cheat_enabled_code_exists;
+  bool cheat_system_enabled;
+
+  uint8_t mask[0x200000];
+  vector<cheat_t> code;
+
+  bool decode(const char *str, unsigned &addr, uint8_t &data, type_t &type) const;
+  bool encode(string &str, unsigned addr, uint8_t data, type_t type) const;
+
+  void update_cheat_status();
+  unsigned mirror_address(unsigned addr) const;
+
+  void update(const cheat_t& item);
+  void set(unsigned addr);
+  void clear(unsigned addr);
+
+  string& encode_description(string &desc) const;
+  string& decode_description(string &desc) const;
+};
+
+extern Cheat cheat;

src/chip/bsx/bsx.cpp

@@ -1,6 +1,10 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define BSX_CPP
+namespace SNES {
 
 #include "bsx_base.cpp"
 #include "bsx_cart.cpp"
 #include "bsx_flash.cpp"
+};
+

src/chip/bsx/bsx.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 mmio_read(uint addr);
-  void mmio_write(uint addr, uint8 data);
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
 
 private:
   struct {
@@ -29,19 +29,13 @@ public:
   void power();
   void reset();
 
-  uint8 mmio_read(uint addr);
-  void mmio_write(uint addr, uint8 data);
-
-  MappedRAM sram;
-  MappedRAM psram;
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
 
   BSXCart();
   ~BSXCart();
 
 private:
-  uint8 *sram_data;  //256kbit SRAM
-  uint8 *psram_data; //  4mbit PSRAM
-
   struct {
     uint8 r[16];
   } regs;
@@ -56,13 +50,13 @@ public:
   void power();
   void reset();
 
-  uint size();
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  unsigned size() const;
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 
 private:
   struct {
-    uint command;
+    unsigned command;
     uint8 write_old;
     uint8 write_new;
 

src/chip/bsx/bsx_base.cpp

@@ -1,5 +1,7 @@
 #ifdef BSX_CPP
 
+BSXBase bsxbase;
+
 void BSXBase::init() {
 }
 
@@ -15,7 +17,7 @@ void BSXBase::reset() {
   memset(&regs, 0x00, sizeof regs);
 }
 
-uint8 BSXBase::mmio_read(uint addr) {
+uint8 BSXBase::mmio_read(unsigned addr) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -28,7 +30,7 @@ uint8 BSXBase::mmio_read(uint addr) {
     case 0x2190: return regs.r2190;
 
     case 0x2192: {
-    uint counter = regs.r2192_counter++;
+      unsigned counter = regs.r2192_counter++;
       if(regs.r2192_counter >= 18) regs.r2192_counter = 0;
 
       if(counter == 0) {
@@ -73,7 +75,7 @@ uint8 BSXBase::mmio_read(uint addr) {
   return cpu.regs.mdr;
 }
 
-void BSXBase::mmio_write(uint addr, uint8 data) {
+void BSXBase::mmio_write(unsigned addr, uint8 data) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -134,4 +136,5 @@ void BSXBase::mmio_write(uint addr, uint8 data) {
   }
 }
 
-#endif //ifdef BSX_CPP
+#endif
+

src/chip/bsx/bsx_cart.cpp

@@ -1,5 +1,7 @@
 #ifdef BSX_CPP
 
+BSXCart bsxcart;
+
 void BSXCart::init() {
 }
 
@@ -12,7 +14,7 @@ void BSXCart::power() {
 }
 
 void BSXCart::reset() {
-  for(uint i = 0; i < 16; i++) regs.r[i] = 0x00;
+  for(unsigned i = 0; i < 16; i++) regs.r[i] = 0x00;
   regs.r[0x07] = 0x80;
   regs.r[0x08] = 0x80;
 
@@ -20,12 +22,14 @@ void BSXCart::reset() {
 }
 
 void BSXCart::update_memory_map() {
-  Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)psram;
+  Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)memory::bsxpram;
 
-  if((regs.r[0x02] & 0x80) == 0x00) { //LoROM mapping
+  if((regs.r[0x02] & 0x80) == 0x00) {
+    //LoROM mapping
     bus.map(Bus::MapLinear, 0x00, 0x7d, 0x8000, 0xffff, cart);
     bus.map(Bus::MapLinear, 0x80, 0xff, 0x8000, 0xffff, cart);
-  } else { //HiROM mapping
+  } else {
+    //HiROM mapping
     bus.map(Bus::MapShadow, 0x00, 0x3f, 0x8000, 0xffff, cart);
     bus.map(Bus::MapLinear, 0x40, 0x7d, 0x0000, 0xffff, cart);
     bus.map(Bus::MapShadow, 0x80, 0xbf, 0x8000, 0xffff, cart);
@@ -33,16 +37,16 @@ void BSXCart::update_memory_map() {
   }
 
   if(regs.r[0x03] & 0x80) {
-    bus.map(Bus::MapLinear, 0x60, 0x6f, 0x0000, 0xffff, psram);
-  //bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
+    bus.map(Bus::MapLinear, 0x60, 0x6f, 0x0000, 0xffff, memory::bsxpram);
+  //bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, memory::bsxpram);
   }
 
   if((regs.r[0x05] & 0x80) == 0x00) {
-    bus.map(Bus::MapLinear, 0x40, 0x4f, 0x0000, 0xffff, psram);
+    bus.map(Bus::MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::bsxpram);
   }
 
   if((regs.r[0x06] & 0x80) == 0x00) {
-    bus.map(Bus::MapLinear, 0x50, 0x5f, 0x0000, 0xffff, psram);
+    bus.map(Bus::MapLinear, 0x50, 0x5f, 0x0000, 0xffff, memory::bsxpram);
   }
 
   if(regs.r[0x07] & 0x80) {
@@ -53,24 +57,24 @@ void BSXCart::update_memory_map() {
     bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom);
   }
 
-  bus.map(Bus::MapShadow, 0x20, 0x3f, 0x6000, 0x7fff, psram);
-  bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
+  bus.map(Bus::MapShadow, 0x20, 0x3f, 0x6000, 0x7fff, memory::bsxpram);
+  bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, memory::bsxpram);
 }
 
-uint8 BSXCart::mmio_read(uint addr) {
+uint8 BSXCart::mmio_read(unsigned addr) {
   if((addr & 0xf0ffff) == 0x005000) {  //$[00-0f]:5000 MMIO
     uint8 n = (addr >> 16) & 15;
     return regs.r[n];
   }
 
   if((addr & 0xf8f000) == 0x105000) {  //$[10-17]:[5000-5fff] SRAM
-    return sram.read(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
+    return memory::bsxram.read(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
   }
 
   return 0x00;
 }
 
-void BSXCart::mmio_write(uint addr, uint8 data) {
+void BSXCart::mmio_write(unsigned addr, uint8 data) {
   if((addr & 0xf0ffff) == 0x005000) {  //$[00-0f]:5000 MMIO
     uint8 n = (addr >> 16) & 15;
     regs.r[n] = data;
@@ -79,21 +83,15 @@ void BSXCart::mmio_write(uint addr, uint8 data) {
   }
 
   if((addr & 0xf8f000) == 0x105000) {  //$[10-17]:[5000-5fff] SRAM
-    return sram.write(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
+    return memory::bsxram.write(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
   }
 }
 
 BSXCart::BSXCart() {
-  sram_data  = new uint8_t[ 32 * 1024];
-  psram_data = new uint8_t[512 * 1024];
-
-  sram.map (sram_data,   32 * 1024);
-  psram.map(psram_data, 512 * 1024);
 }
 
 BSXCart::~BSXCart() {
-  delete[] sram_data;
-  delete[] psram_data;
 }
 
-#endif //ifdef BSX_CPP
+#endif
+

src/chip/bsx/bsx_flash.cpp

@@ -1,5 +1,7 @@
 #ifdef BSX_CPP
 
+BSXFlash bsxflash;
+
 void BSXFlash::init() {}
 void BSXFlash::enable() {}
 
@@ -15,13 +17,14 @@ void BSXFlash::reset() {
   regs.flash_enable = false;
   regs.read_enable  = false;
   regs.write_enable = false;
+  memory::bsxflash.write_protect(!regs.write_enable);
 }
 
-uint BSXFlash::size() {
-  return memory::bscram.size();
+unsigned BSXFlash::size() const {
+  return memory::bsxflash.size();
 }
 
-uint8 BSXFlash::read(uint addr) {
+uint8 BSXFlash::read(unsigned addr) {
   if(addr == 0x0002) {
     if(regs.flash_enable) return 0x80;
   }
@@ -45,18 +48,18 @@ uint8 BSXFlash::read(uint addr) {
     }
   }
 
-  return memory::bscram.read(addr);
+  return memory::bsxflash.read(addr);
 }
 
-void BSXFlash::write(uint addr, uint8 data) {
-//there exist both read-only and read-write BS-X flash cartridges ...
-//unfortunately, the vendor info is not stored inside memory dumps
-//of BS-X flashcarts, so it is impossible to determine whether a
-//given flashcart is writeable.
-//however, it has been observed that LoROM-mapped BS-X carts always
-//use read-write flashcarts, and HiROM-mapped BS-X carts always use
-//read-only flashcarts.
-//below is an unfortunately necessary workaround to this problem.
+void BSXFlash::write(unsigned addr, uint8 data) {
+  //there exist both read-only and read-write BS-X flash cartridges ...
+  //unfortunately, the vendor info is not stored inside memory dumps
+  //of BS-X flashcarts, so it is impossible to determine whether a
+  //given flashcart is writeable.
+  //however, it has been observed that LoROM-mapped BS-X carts always
+  //use read-write flashcarts, and HiROM-mapped BS-X carts always use
+  //read-only flashcarts.
+  //below is an unfortunately necessary workaround to this problem.
   if(cartridge.mapper() == Cartridge::BSCHiROM) return;
 
   if((addr & 0xff0000) == 0) {
@@ -64,11 +67,11 @@ void BSXFlash::write(uint addr, uint8 data) {
     regs.write_new = data;
 
     if(regs.write_enable && regs.write_old == regs.write_new) {
-      return memory::bscram.write(addr, data);
+      return memory::bsxflash.write(addr, data);
     }
   } else {
     if(regs.write_enable) {
-      return memory::bscram.write(addr, data);
+      return memory::bsxflash.write(addr, data);
     }
   }
 
@@ -107,7 +110,10 @@ void BSXFlash::write(uint addr, uint8 data) {
       regs.read_enable  = false;
       regs.write_enable = false;
     }
+
+    memory::bsxflash.write_protect(!regs.write_enable);
   }
 }
 
-#endif //ifdef BSX_CPP
+#endif
+

src/chip/chip.h

@@ -1,11 +0,0 @@
-#include "bsx/bsx.h"
-#include "srtc/srtc.h"
-#include "sdd1/sdd1.h"
-#include "spc7110/spc7110.h"
-#include "cx4/cx4.h"
-#include "dsp1/dsp1.h"
-#include "dsp2/dsp2.h"
-#include "dsp3/dsp3.h"
-#include "dsp4/dsp4.h"
-#include "obc1/obc1.h"
-#include "st010/st010.h"

src/chip/chip.hpp

@@ -0,0 +1,14 @@
+#include "sgb/sgb.hpp"
+#include "superfx/superfx.hpp"
+#include "sa1/sa1.hpp"
+#include "bsx/bsx.hpp"
+#include "srtc/srtc.hpp"
+#include "sdd1/sdd1.hpp"
+#include "spc7110/spc7110.hpp"
+#include "cx4/cx4.hpp"
+#include "dsp1/dsp1.hpp"
+#include "dsp2/dsp2.hpp"
+#include "dsp3/dsp3.hpp"
+#include "dsp4/dsp4.hpp"
+#include "obc1/obc1.hpp"
+#include "st010/st010.hpp"

src/chip/cx4/cx4.cpp

@@ -5,8 +5,12 @@
   Portions (c) anomie, Overload, zsKnight, Nach, byuu
 */
 
-#include "../../base.h"
+#include <../base.hpp>
+
 #define CX4_CPP
+namespace SNES {
+
+Cx4 cx4;
 
 #include "cx4data.cpp"
 #include "cx4fn.cpp"
@@ -29,8 +33,8 @@ uint16 addr = 0x0080 + (r * 3);
 }
 
 void Cx4::mul(uint32 x, uint32 y, uint32 &rl, uint32 &rh) {
-int64 rx = x & 0xffffff;
-int64 ry = y & 0xffffff;
+int64_t rx = x & 0xffffff;
+int64_t ry = y & 0xffffff;
   if(rx & 0x800000)rx |= ~0x7fffff;
   if(ry & 0x800000)ry |= ~0x7fffff;
 
@@ -78,7 +82,7 @@ uint16 dest, count;
   }
 }
 
-void Cx4::write(uint addr, uint8 data) {
+void Cx4::write(unsigned addr, uint8 data) {
   addr &= 0x1fff;
 
   if(addr < 0x0c00) {
@@ -160,7 +164,7 @@ void Cx4::writel(uint16 addr, uint32 data) {
   write(addr + 2, data >> 16);
 }
 
-uint8 Cx4::read(uint addr) {
+uint8 Cx4::read(unsigned addr) {
   addr &= 0x1fff;
 
   if(addr < 0x0c00) {
@@ -194,3 +198,5 @@ void Cx4::reset() {
   memset(ram, 0, 0x0c00);
   memset(reg, 0, 0x0100);
 }
+};
+

src/chip/cx4/cx4.hpp

@@ -90,8 +90,8 @@ public:
   void   power();
   void   reset();
 
-  uint8  read (uint addr);
-  void   write(uint addr, uint8 data);
+  uint8  read (unsigned addr);
+  void   write(unsigned addr, uint8 data);
 };
 
 extern Cx4 cx4;

src/chip/cx4/cx4data.cpp

@@ -184,4 +184,4 @@ const int16 Cx4::CosTable[512] = {
    32610,  32647,  32679,  32706,  32728,  32745,  32758,  32765
 };
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/cx4fn.cpp

@@ -243,4 +243,4 @@ uint8 bit    = 0x80;
   }
 }
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/cx4oam.cpp

@@ -220,4 +220,4 @@ uint16 mask2   = 0x3f3f;
   }
 }
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/cx4ops.cpp

@@ -223,4 +223,4 @@ void Cx4::op89() {
   str(1, 0xffffff);
 }
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/dsp1/dsp1.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define DSP1_CPP
+namespace SNES {
+
+DSP1 dsp1;
 
 #include "dsp1emu.cpp"
 
@@ -26,7 +30,7 @@ void DSP1::reset() {
  * of expected ranges
  *****/
 bool DSP1::addr_decode(uint16 addr) {
-  switch(cartridge.info.dsp1_mapper) {
+  switch(cartridge.dsp1_mapper()) {
     case Cartridge::DSP1LoROM1MB: {
     //$[20-3f]:[8000-bfff] = DR, $[20-3f]:[c000-ffff] = SR
       return (addr >= 0xc000);
@@ -46,12 +50,14 @@ bool DSP1::addr_decode(uint16 addr) {
   return 0;
 }
 
-uint8 DSP1::read(uint addr) {
+uint8 DSP1::read(unsigned addr) {
   return (addr_decode(addr) == 0) ? dsp1.getDr() : dsp1.getSr();
 }
 
-void DSP1::write(uint addr, uint8 data) {
+void DSP1::write(unsigned addr, uint8 data) {
   if(addr_decode(addr) == 0) {
     dsp1.setDr(data);
   }
 }
+};
+

src/chip/dsp1/dsp1.hpp

@@ -1,4 +1,4 @@
-#include "dsp1emu.h"
+#include "dsp1emu.hpp"
 
 class DSP1 : public Memory {
 private:
@@ -11,8 +11,8 @@ public:
   void power();
   void reset();
 
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 };
 
 extern DSP1 dsp1;

src/chip/dsp1/dsp1emu.cpp

@@ -1622,4 +1622,4 @@ const int16 Dsp1::SinTable[256] = {
 
 //////////////////////////////////////////////////////////////////
 
-#endif //ifdef DSP1_CPP
+#endif

src/chip/dsp2/dsp2.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define DSP2_CPP
+namespace SNES {
+
+DSP2 dsp2;
 
 #include "dsp2_op.cpp"
 
@@ -29,8 +33,8 @@ void DSP2::reset() {
   status.op0dinlen       = 0;
 }
 
-uint8 DSP2::read(uint addr) {
-uint8 r = 0xff;
+uint8 DSP2::read(unsigned addr) {
+  uint8 r = 0xff;
   if(status.out_count) {
     r = status.output[status.out_index++];
     status.out_index &= 511;
@@ -41,7 +45,7 @@ uint8 r = 0xff;
   return r;
 }
 
-void DSP2::write(uint addr, uint8 data) {
+void DSP2::write(unsigned addr, uint8 data) {
   if(status.waiting_for_command) {
     status.command  = data;
     status.in_index = 0;
@@ -133,3 +137,5 @@ void DSP2::write(uint addr, uint8 data) {
 
 DSP2::DSP2() {}
 DSP2::~DSP2() {}
+};
+

src/chip/dsp2/dsp2.hpp

@@ -2,9 +2,9 @@ class DSP2 : public Memory {
 public:
   struct {
     bool waiting_for_command;
-    uint   command;
-    uint   in_count,  in_index;
-    uint   out_count, out_index;
+    unsigned command;
+    unsigned in_count,  in_index;
+    unsigned out_count, out_index;
 
     uint8  parameters[512];
     uint8  output[512];
@@ -26,8 +26,8 @@ public:
   void power();
   void reset();
 
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 
   DSP2();
   ~DSP2();

src/chip/dsp2/dsp2_op.cpp

@@ -174,4 +174,4 @@ uint8  pixelarray[512];
   }
 }
 
-#endif //ifdef DSP2_CPP
+#endif

src/chip/dsp3/dsp3.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define DSP3_CPP
+namespace SNES {
+
+DSP3 dsp3;
 
 namespace DSP3i {
   #define bool8 uint8
@@ -21,14 +25,16 @@ void DSP3::reset() {
   DSP3i::DSP3_Reset();
 }
 
-uint8 DSP3::read(uint addr) {
+uint8 DSP3::read(unsigned addr) {
   DSP3i::dsp3_address = addr & 0xffff;
   DSP3i::DSP3GetByte();
   return DSP3i::dsp3_byte;
 }
 
-void DSP3::write(uint addr, uint8 data) {
+void DSP3::write(unsigned addr, uint8 data) {
   DSP3i::dsp3_address = addr & 0xffff;
   DSP3i::dsp3_byte = data;
   DSP3i::DSP3SetByte();
 }
+
+};

src/chip/dsp3/dsp3.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
 };
 
 extern DSP3 dsp3;

src/chip/dsp3/dsp3emu.c

@@ -1143,4 +1143,4 @@ void InitDSP3()
   DSP3_Reset();
 }
 
-#endif //ifdef DSP3_CPP
+#endif

src/chip/dsp4/dsp4.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define DSP4_CPP
+namespace SNES {
+
+DSP4 dsp4;
 
 namespace DSP4i {
   inline uint16 READ_WORD(uint8 *addr) {
@@ -34,7 +38,7 @@ void DSP4::reset() {
   DSP4i::InitDSP4();
 }
 
-uint8 DSP4::read(uint addr) {
+uint8 DSP4::read(unsigned addr) {
   addr &= 0xffff;
   if(addr < 0xc000) {
     DSP4i::dsp4_address = addr;
@@ -44,7 +48,7 @@ uint8 DSP4::read(uint addr) {
   return 0x80;
 }
 
-void DSP4::write(uint addr, uint8 data) {
+void DSP4::write(unsigned addr, uint8 data) {
   addr &= 0xffff;
   if(addr < 0xc000) {
     DSP4i::dsp4_address = addr;
@@ -52,3 +56,5 @@ void DSP4::write(uint addr, uint8 data) {
     DSP4i::DSP4SetByte();
   }
 }
+
+};

src/chip/dsp4/dsp4.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
 };
 
 extern DSP4 dsp4;

src/chip/dsp4/dsp4emu.c

@@ -2147,4 +2147,4 @@ void DSP4GetByte()
   }
 }
 
-#endif //ifdef DSP4_CPP
+#endif

src/chip/obc1/obc1.cpp

@@ -1,4 +1,9 @@
-#include "../../base.h"
+#include <../base.hpp>
+
+#define OBC1_CPP
+namespace SNES {
+
+OBC1 obc1;
 
 void OBC1::init() {}
 void OBC1::enable() {}
@@ -68,3 +73,5 @@ void OBC1::ram_write(unsigned addr, uint8 data) {
 
 OBC1::OBC1() {}
 OBC1::~OBC1() {}
+
+};

src/chip/sa1/bus/bus.cpp

@@ -0,0 +1,159 @@
+#ifdef SA1_CPP
+
+SA1Bus sa1bus;
+
+namespace memory {
+  static VectorSelectionPage vectorsp;
+  static StaticRAM iram(2048);
+  static MappedRAM &bwram = memory::cartram;
+  static CC1BWRAM cc1bwram;
+  static BitmapRAM bitmapram;
+}
+
+void SA1Bus::init() {
+  map(MapDirect, 0x00, 0xff, 0x0000, 0xffff, memory::memory_unmapped);
+  for(uint16_t i = 0x2200; i <= 0x23ff; i++) memory::mmio.map(i, sa1);
+
+  map(MapLinear, 0x00, 0x3f, 0x0000, 0x07ff, memory::iram);
+  map(MapDirect, 0x00, 0x3f, 0x2200, 0x23ff, memory::mmio);
+  map(MapLinear, 0x00, 0x3f, 0x3000, 0x37ff, memory::iram);
+  map(MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::bwram);
+  map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::cartrom);
+  map(MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::bwram);
+  map(MapLinear, 0x60, 0x6f, 0x0000, 0xffff, memory::bitmapram);
+  map(MapLinear, 0x80, 0xbf, 0x0000, 0x07ff, memory::iram);
+  map(MapDirect, 0x80, 0xbf, 0x2200, 0x23ff, memory::mmio);
+  map(MapLinear, 0x80, 0xbf, 0x3000, 0x37ff, memory::iram);
+  map(MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::bwram);
+  map(MapLinear, 0x80, 0xbf, 0x8000, 0xffff, memory::cartrom);
+  map(MapLinear, 0xc0, 0xff, 0x0000, 0xffff, memory::cartrom);
+
+  bus.map(MapLinear, 0x00, 0x3f, 0x3000, 0x37ff, memory::iram);
+  bus.map(MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::cc1bwram);
+  bus.map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::cartrom);
+  bus.map(MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::cc1bwram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x3000, 0x37ff, memory::iram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::cc1bwram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x8000, 0xffff, memory::cartrom);
+  bus.map(MapLinear, 0xc0, 0xff, 0x0000, 0xffff, memory::cartrom);
+
+  memory::vectorsp.sync();
+}
+
+//===================
+//VectorSelectionPage
+//===================
+
+//this class maps $00:[ff00-ffff] for the purpose of supporting:
+//$2209.d6 IVSW (S-CPU IRQ vector selection) (0 = cart, 1 = SA-1)
+//$2209.d4 NVSW (S-CPU NMI vector selection) (0 = cart, 1 = SA-1)
+//when set, vector addresses are over-ridden with SA-1 register settings:
+//SIV = S-CPU IRQ vector address override
+//SNV = S-CPU NMI vector address override
+//
+//$00:[ffea-ffeb|ffee-ffef] are special cased on read;
+//all other addresses return original mapped data.
+
+uint8_t VectorSelectionPage::read(unsigned addr) {
+  switch(0xff00 | (addr & 0xff)) {
+    case 0xffea: case 0xffeb: {
+      if(sa1.mmio.cpu_nvsw == true) return (sa1.mmio.snv >> ((addr & 1) << 3));
+    } break;
+
+    case 0xffee: case 0xffef: {
+      if(sa1.mmio.cpu_ivsw == true) return (sa1.mmio.siv >> ((addr & 1) << 3));
+    } break;
+  }
+
+  return access->read(addr);
+}
+
+void VectorSelectionPage::write(unsigned addr, uint8_t data) {
+  return access->write(addr, data);
+}
+
+//call this whenever bus is remapped.
+//note: S-CPU and SA-1 bus always share $00:[ff00-ffff] as cartridge ROM data;
+//the SA-1 MMC does not allow mapping these independently between processors.
+//this allows this class to be shared for both, caching only ones' access class.
+void VectorSelectionPage::sync() {
+  if(bus.page[0x00ff00 >> 8].access != this) {
+    //bus was re-mapped, hook access routine
+    access = bus.page[0x00ff00 >> 8].access;
+       bus.page[0x00ff00 >> 8].access = this;
+    sa1bus.page[0x00ff00 >> 8].access = this;
+  }
+}
+
+//========
+//CC1BWRAM
+//========
+
+unsigned CC1BWRAM::size() const {
+  return memory::cartram.size();
+}
+
+uint8_t CC1BWRAM::read(unsigned addr) {
+  if(dma) return sa1.dma_cc1_read(addr);
+  return memory::cartram.read(addr);
+}
+
+void CC1BWRAM::write(unsigned addr, uint8_t data) {
+  memory::cartram.write(addr, data);
+}
+
+//=========
+//BitmapRAM
+//=========
+
+unsigned BitmapRAM::size() const {
+  return 0x100000;
+}
+
+uint8_t BitmapRAM::read(unsigned addr) {
+  if(sa1.mmio.bbf == 0) {
+    //4bpp
+    unsigned shift = addr & 1;
+    addr = (addr >> 1) & (memory::cartram.size() - 1);
+    switch(shift) { default:
+      case 0: return (memory::cartram.read(addr) >> 0) & 15;
+      case 1: return (memory::cartram.read(addr) >> 4) & 15;
+    }
+  } else {
+    //2bpp
+    unsigned shift = addr & 3;
+    addr = (addr >> 2) & (memory::cartram.size() - 1);
+    switch(shift) { default:
+      case 0: return (memory::cartram.read(addr) >> 0) & 3;
+      case 1: return (memory::cartram.read(addr) >> 2) & 3;
+      case 2: return (memory::cartram.read(addr) >> 4) & 3;
+      case 3: return (memory::cartram.read(addr) >> 6) & 3;
+    }
+  }
+}
+
+void BitmapRAM::write(unsigned addr, uint8_t data) {
+  if(sa1.mmio.bbf == 0) {
+    //4bpp
+    uint8_t shift = addr & 1;
+    addr = (addr >> 1) & (memory::cartram.size() - 1);
+    switch(shift) { default:
+      case 0: data = (memory::cartram.read(addr) & 0xf0) | ((data & 15) << 0); break;
+      case 1: data = (memory::cartram.read(addr) & 0x0f) | ((data & 15) << 4); break;
+    }
+  } else {
+    //2bpp
+    uint8_t shift = addr & 3;
+    addr = (addr >> 2) & (memory::cartram.size() - 1);
+    switch(shift) { default:
+      case 0: data = (memory::cartram.read(addr) & 0xfc) | ((data &  3) << 0); break;
+      case 1: data = (memory::cartram.read(addr) & 0xf3) | ((data &  3) << 2); break;
+      case 2: data = (memory::cartram.read(addr) & 0xcf) | ((data &  3) << 4); break;
+      case 3: data = (memory::cartram.read(addr) & 0x3f) | ((data &  3) << 6); break;
+    }
+  }
+
+  memory::cartram.write(addr, data);
+}
+
+#endif

src/chip/sa1/bus/bus.hpp

@@ -0,0 +1,23 @@
+struct SA1Bus : Bus {
+  void init();
+};
+
+struct VectorSelectionPage : Memory {
+  alwaysinline uint8_t read(unsigned);
+  alwaysinline void write(unsigned, uint8_t);
+  void sync();
+  Memory *access;
+};
+
+struct CC1BWRAM : Memory {
+  unsigned size() const;
+  alwaysinline uint8_t read(unsigned);
+  alwaysinline void write(unsigned, uint8_t);
+  bool dma;
+};
+
+struct BitmapRAM : Memory {
+  unsigned size() const;
+  alwaysinline uint8_t read(unsigned);
+  alwaysinline void write(unsigned, uint8_t);
+};

src/chip/sa1/dma/dma.cpp

@@ -0,0 +1,139 @@
+#ifdef SA1_CPP
+
+//====================
+//direct data transfer
+//====================
+
+void SA1::dma_normal() {
+  while(mmio.dtc--) {
+    uint8_t data = regs.mdr;
+    uint32_t dsa = mmio.dsa++;
+    uint32_t dda = mmio.dda++;
+
+    //source and destination cannot be the same
+    if(mmio.sd == DMA::SourceBWRAM && mmio.dd == DMA::DestBWRAM) continue;
+    if(mmio.sd == DMA::SourceIRAM  && mmio.dd == DMA::DestIRAM ) continue;
+
+    switch(mmio.sd) {
+      case DMA::SourceROM: {
+        if((dsa & 0x408000) == 0x008000 || (dsa & 0xc00000) == 0xc00000) {
+          data = sa1bus.read(dsa);
+        }
+      } break;
+
+      case DMA::SourceBWRAM: {
+        if((dsa & 0x40e000) == 0x006000 || (dsa & 0xf00000) == 0x400000) {
+          data = sa1bus.read(dsa);
+        }
+      } break;
+
+      case DMA::SourceIRAM: {
+        data = memory::iram.read(dsa & 0x07ff);
+      } break;
+    }
+
+    switch(mmio.dd) {
+      case DMA::DestBWRAM: {
+        if((dda & 0x40e000) == 0x006000 || (dda & 0xf00000) == 0x400000) {
+          sa1bus.write(dda, data);
+        }
+      } break;
+
+      case DMA::DestIRAM: {
+        memory::iram.write(dda & 0x07ff, data);
+      } break;
+    }
+  }
+
+  mmio.dma_irqfl = true;
+  if(mmio.dma_irqen) mmio.dma_irqcl = 0;
+}
+
+//((byte & 6) << 3) + (byte & 1) explanation:
+//transforms a byte index (0-7) into a planar index:
+//result[] = {  0,  1, 16, 17, 32, 33, 48, 49 };
+//works for 2bpp, 4bpp and 8bpp modes
+
+//===========================
+//type-1 character conversion
+//===========================
+
+void SA1::dma_cc1() {
+  memory::cc1bwram.dma = true;
+  mmio.chdma_irqfl = true;
+  if(mmio.chdma_irqen) {
+    mmio.chdma_irqcl = 0;
+    cpu.regs.irq = 1;
+  }
+}
+
+uint8_t SA1::dma_cc1_read(unsigned addr) {
+  //16 bytes/char (2bpp); 32 bytes/char (4bpp); 64 bytes/char (8bpp)
+  unsigned charmask = (1 << (6 - mmio.dmacb)) - 1;
+
+  if((addr & charmask) == 0) {
+    //buffer next character to I-RAM
+    unsigned bpp = 2 << (2 - mmio.dmacb);
+    unsigned bpl = (8 << mmio.dmasize) >> mmio.dmacb;
+    unsigned bwmask = memory::bwram.size() - 1;
+    unsigned tile = ((addr - mmio.dsa) & bwmask) >> (6 - mmio.dmacb);
+    unsigned ty = (tile >> mmio.dmasize);
+    unsigned tx = tile & ((1 << mmio.dmasize) - 1);
+    unsigned bwaddr = mmio.dsa + ty * 8 * bpl + tx * bpp;
+
+    for(unsigned y = 0; y < 8; y++) {
+      uint64_t data = 0;
+      for(unsigned byte = 0; byte < bpp; byte++) {
+        data |= (uint64_t)memory::bwram.read((bwaddr + byte) & bwmask) << (byte << 3);
+      }
+      bwaddr += bpl;
+
+      uint8_t out[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+      for(unsigned x = 0; x < 8; x++) {
+        out[0] |= (data & 1) << (7 - x); data >>= 1;
+        out[1] |= (data & 1) << (7 - x); data >>= 1;
+        if(mmio.dmacb == 2) continue;
+        out[2] |= (data & 1) << (7 - x); data >>= 1;
+        out[3] |= (data & 1) << (7 - x); data >>= 1;
+        if(mmio.dmacb == 1) continue;
+        out[4] |= (data & 1) << (7 - x); data >>= 1;
+        out[5] |= (data & 1) << (7 - x); data >>= 1;
+        out[6] |= (data & 1) << (7 - x); data >>= 1;
+        out[7] |= (data & 1) << (7 - x); data >>= 1;
+      }
+
+      for(unsigned byte = 0; byte < bpp; byte++) {
+        unsigned p = mmio.dda + (y << 1) + ((byte & 6) << 3) + (byte & 1);
+        memory::iram.write(p & 0x07ff, out[byte]);
+      }
+    }
+  }
+
+  return memory::iram.read((mmio.dda + (addr & charmask)) & 0x07ff);
+}
+
+//===========================
+//type-2 character conversion
+//===========================
+
+void SA1::dma_cc2() {
+  //select register file index (0-7 or 8-15)
+  const uint8_t *brf = &mmio.brf[(dma.line & 1) << 3];
+  unsigned bpp = 2 << (2 - mmio.dmacb);
+  unsigned addr = mmio.dda & 0x07ff;
+  addr &= ~((1 << (7 - mmio.dmacb)) - 1);
+  addr += (dma.line & 8) * bpp;
+  addr += (dma.line & 7) * 2;
+
+  for(unsigned byte = 0; byte < bpp; byte++) {
+    uint8_t output = 0;
+    for(unsigned bit = 0; bit < 8; bit++) {
+      output |= ((brf[bit] >> byte) & 1) << (7 - bit);
+    }
+    memory::iram.write(addr + ((byte & 6) << 3) + (byte & 1), output);
+  }
+
+  dma.line = (dma.line + 1) & 15;
+}
+
+#endif

src/chip/sa1/dma/dma.hpp

@@ -0,0 +1,11 @@
+struct DMA {
+  enum CDEN { DmaNormal = 0, DmaCharConversion = 1 };
+  enum SD { SourceROM = 0, SourceBWRAM = 1, SourceIRAM = 2 };
+  enum DD { DestIRAM = 0, DestBWRAM = 1 };
+  unsigned line;
+} dma;
+
+void dma_normal();
+void dma_cc1();
+uint8_t dma_cc1_read(unsigned addr);
+void dma_cc2();

src/chip/sa1/memory/memory.cpp

@@ -0,0 +1,39 @@
+#ifdef SA1_CPP
+
+//==========================
+//SA-1 opcode core functions
+//==========================
+
+void SA1::op_io() {
+  tick();
+  if(regs.wai) scheduler.sync_copcpu();
+}
+
+//ROM, I-RAM and MMIO registers are accessed at ~10.74MHz (2 clock ticks)
+//BW-RAM is accessed at ~5.37MHz (4 clock ticks)
+//tick() == 2 clock ticks
+//note: bus conflict delays are not emulated at this time
+
+#define is_bwram(addr) (\
+   ((addr & 0x40e000) == 0x006000) \
+|| ((addr & 0xf00000) == 0x400000) \
+|| ((addr & 0xf00000) == 0x600000) \
+)
+
+uint8_t SA1::op_read(unsigned addr) {
+  tick();
+  if(is_bwram(addr)) tick();
+  scheduler.sync_copcpu();
+  return sa1bus.read(addr);
+}
+
+void SA1::op_write(unsigned addr, uint8_t data) {
+  tick();
+  if(is_bwram(addr)) tick();
+  scheduler.sync_copcpu();
+  sa1bus.write(addr, data);
+}
+
+#undef is_bwram
+
+#endif

src/chip/sa1/memory/memory.hpp

@@ -0,0 +1,4 @@
+alwaysinline void op_io();
+alwaysinline uint8_t op_read(unsigned addr);
+alwaysinline void op_write(unsigned addr, uint8_t data);
+alwaysinline unsigned bus_speed(unsigned addr);

src/chip/sa1/mmio/mmio.cpp

@@ -0,0 +1,631 @@
+#ifdef SA1_CPP
+
+//BS-X flash carts, when present, are mapped to 0x400000+
+Memory& SA1::mmio_access(unsigned &addr) {
+  if(!memory::bsxflash.data()) return memory::cartrom;
+  if(addr < 0x400000) return memory::cartrom;
+  addr &= 0x3fffff;
+  return bsxflash;
+}
+
+//(CCNT) SA-1 control
+void SA1::mmio_w2200(uint8_t data) {
+  if(mmio.sa1_resb && !(data & 0x80)) {
+    //reset SA-1 CPU
+    regs.pc.w = mmio.crv;
+    regs.pc.b = 0x00;
+  }
+
+  mmio.sa1_irq  = (data & 0x80);
+  mmio.sa1_rdyb = (data & 0x40);
+  mmio.sa1_resb = (data & 0x20);
+  mmio.sa1_nmi  = (data & 0x10);
+  mmio.smeg     = (data & 0x0f);
+
+  if(mmio.sa1_irq) {
+    mmio.sa1_irqfl = true;
+    if(mmio.sa1_irqen) mmio.sa1_irqcl = 0;
+  }
+
+  if(mmio.sa1_nmi) {
+    mmio.sa1_nmifl = true;
+    if(mmio.sa1_nmien) mmio.sa1_nmicl = 0;
+  }
+}
+
+//(SIE) S-CPU interrupt enable
+void SA1::mmio_w2201(uint8_t data) {
+  if(!mmio.cpu_irqen && (data & 0x80)) {
+    if(mmio.cpu_irqfl) {
+      mmio.cpu_irqcl = 0;
+      cpu.regs.irq = 1;
+    }
+  }
+
+  if(!mmio.chdma_irqen && (data & 0x20)) {
+    if(mmio.chdma_irqfl) {
+      mmio.chdma_irqcl = 0;
+      cpu.regs.irq = 1;
+    }
+  }
+
+  mmio.cpu_irqen   = (data & 0x80);
+  mmio.chdma_irqen = (data & 0x20);
+}
+
+//(SIC) S-CPU interrupt clear
+void SA1::mmio_w2202(uint8_t data) {
+  mmio.cpu_irqcl   = (data & 0x80);
+  mmio.chdma_irqcl = (data & 0x20);
+
+  if(mmio.cpu_irqcl  ) mmio.cpu_irqfl   = false;
+  if(mmio.chdma_irqcl) mmio.chdma_irqfl = false;
+
+  if(!mmio.cpu_irqfl && !mmio.chdma_irqfl) cpu.regs.irq = 0;
+}
+
+//(CRV) SA-1 reset vector
+void SA1::mmio_w2203(uint8_t data) { mmio.crv = (mmio.crv & 0xff00) | data; }
+void SA1::mmio_w2204(uint8_t data) { mmio.crv = (data << 8) | (mmio.crv & 0xff); }
+
+//(CNV) SA-1 NMI vector
+void SA1::mmio_w2205(uint8_t data) { mmio.cnv = (mmio.cnv & 0xff00) | data; }
+void SA1::mmio_w2206(uint8_t data) { mmio.cnv = (data << 8) | (mmio.cnv & 0xff); }
+
+//(CIV) SA-1 IRQ vector
+void SA1::mmio_w2207(uint8_t data) { mmio.civ = (mmio.civ & 0xff00) | data; }
+void SA1::mmio_w2208(uint8_t data) { mmio.civ = (data << 8) | (mmio.civ & 0xff); }
+
+//(SCNT) S-CPU control
+void SA1::mmio_w2209(uint8_t data) {
+  mmio.cpu_irq  = (data & 0x80);
+  mmio.cpu_ivsw = (data & 0x40);
+  mmio.cpu_nvsw = (data & 0x10);
+  mmio.cmeg     = (data & 0x0f);
+
+  if(mmio.cpu_irq) {
+    mmio.cpu_irqfl = true;
+    if(mmio.cpu_irqen) {
+      mmio.cpu_irqcl = 0;
+      cpu.regs.irq = 1;
+    }
+  }
+}
+
+//(CIE) SA-1 interrupt enable
+void SA1::mmio_w220a(uint8_t data) {
+  if(!mmio.sa1_irqen   && (data & 0x80) && mmio.sa1_irqfl  ) mmio.sa1_irqcl   = 0;
+  if(!mmio.timer_irqen && (data & 0x40) && mmio.timer_irqfl) mmio.timer_irqcl = 0;
+  if(!mmio.dma_irqen   && (data & 0x20) && mmio.dma_irqfl  ) mmio.dma_irqcl   = 0;
+  if(!mmio.sa1_nmien   && (data & 0x10) && mmio.sa1_nmifl  ) mmio.sa1_nmicl   = 0;
+
+  mmio.sa1_irqen   = (data & 0x80);
+  mmio.timer_irqen = (data & 0x40);
+  mmio.dma_irqen   = (data & 0x20);
+  mmio.sa1_nmien   = (data & 0x10);
+}
+
+//(CIC) SA-1 interrupt clear
+void SA1::mmio_w220b(uint8_t data) {
+  mmio.sa1_irqcl   = (data & 0x80);
+  mmio.timer_irqcl = (data & 0x40);
+  mmio.dma_irqcl   = (data & 0x20);
+  mmio.sa1_nmicl   = (data & 0x10);
+
+  if(mmio.sa1_irqcl)   mmio.sa1_irqfl   = false;
+  if(mmio.timer_irqcl) mmio.timer_irqfl = false;
+  if(mmio.dma_irqcl)   mmio.dma_irqfl   = false;
+  if(mmio.sa1_nmicl)   mmio.sa1_nmifl   = false;
+}
+
+//(SNV) S-CPU NMI vector
+void SA1::mmio_w220c(uint8_t data) { mmio.snv = (mmio.snv & 0xff00) | data;      }
+void SA1::mmio_w220d(uint8_t data) { mmio.snv = (data << 8) | (mmio.snv & 0xff); }
+
+//(SIV) S-CPU IRQ vector
+void SA1::mmio_w220e(uint8_t data) { mmio.siv = (mmio.siv & 0xff00) | data;      }
+void SA1::mmio_w220f(uint8_t data) { mmio.siv = (data << 8) | (mmio.siv & 0xff); }
+
+//(TMC) H/V timer control
+void SA1::mmio_w2210(uint8_t data) {
+  mmio.hvselb = (data & 0x80);
+  mmio.ven    = (data & 0x02);
+  mmio.hen    = (data & 0x01);
+}
+
+//(CTR) SA-1 timer restart
+void SA1::mmio_w2211(uint8_t data) {
+  status.vcounter = 0;
+  status.hcounter = 0;
+}
+
+//(HCNT) H-count
+void SA1::mmio_w2212(uint8_t data) { mmio.hcnt = (mmio.hcnt & 0xff00) | (data << 0); }
+void SA1::mmio_w2213(uint8_t data) { mmio.hcnt = (mmio.hcnt & 0x00ff) | (data << 8); }
+
+//(VCNT) V-count
+void SA1::mmio_w2214(uint8_t data) { mmio.vcnt = (mmio.vcnt & 0xff00) | (data << 0); }
+void SA1::mmio_w2215(uint8_t data) { mmio.vcnt = (mmio.vcnt & 0x00ff) | (data << 8); }
+
+//(CXB) Super MMC bank C
+void SA1::mmio_w2220(uint8_t data) {
+  mmio.cbmode = (data & 0x80);
+  mmio.cb     = (data & 0x07);
+
+  unsigned addr = mmio.cb << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.cbmode == 0) {
+       bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, memory::cartrom, 0x000000);
+    sa1bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, memory::cartrom, 0x000000);
+  } else {
+       bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, access, addr);
+
+  memory::vectorsp.sync();
+}
+
+//(DXB) Super MMC bank D
+void SA1::mmio_w2221(uint8_t data) {
+  mmio.dbmode = (data & 0x80);
+  mmio.db     = (data & 0x07);
+
+  unsigned addr = mmio.db << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.dbmode == 0) {
+       bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, memory::cartrom, 0x100000);
+    sa1bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, memory::cartrom, 0x100000);
+  } else {
+       bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, access, addr);
+}
+
+//(EXB) Super MMC bank E
+void SA1::mmio_w2222(uint8_t data) {
+  mmio.ebmode = (data & 0x80);
+  mmio.eb     = (data & 0x07);
+
+  unsigned addr = mmio.eb << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.ebmode == 0) {
+       bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom, 0x200000);
+    sa1bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom, 0x200000);
+  } else {
+       bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, access, addr);
+}
+
+//(FXB) Super MMC bank F
+void SA1::mmio_w2223(uint8_t data) {
+  mmio.fbmode = (data & 0x80);
+  mmio.fb     = (data & 0x07);
+
+  unsigned addr = mmio.fb << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.fbmode == 0) {
+       bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, memory::cartrom, 0x300000);
+    sa1bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, memory::cartrom, 0x300000);
+  } else {
+       bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, access, addr);
+}
+
+//(BMAPS) S-CPU BW-RAM address mapping
+void SA1::mmio_w2224(uint8_t data) {
+  mmio.sbm = (data & 0x1f);
+
+  bus.map(Bus::MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::cc1bwram, mmio.sbm * 0x2000, 0x2000);
+  bus.map(Bus::MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::cc1bwram, mmio.sbm * 0x2000, 0x2000);
+}
+
+//(BMAP) SA-1 BW-RAM address mapping
+void SA1::mmio_w2225(uint8_t data) {
+  mmio.sw46 = (data & 0x80);
+  mmio.cbm  = (data & 0x7f);
+
+  if(mmio.sw46 == 0) {
+    //$[40-43]:[0000-ffff] x  32 projection
+    sa1bus.map(Bus::MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::bwram, (mmio.cbm & 0x1f) * 0x2000, 0x2000);
+    sa1bus.map(Bus::MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::bwram, (mmio.cbm & 0x1f) * 0x2000, 0x2000);
+  } else {
+    //$[60-6f]:[0000-ffff] x 128 projection
+    sa1bus.map(Bus::MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::bitmapram, mmio.cbm * 0x2000, 0x2000);
+    sa1bus.map(Bus::MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::bitmapram, mmio.cbm * 0x2000, 0x2000);
+  }
+}
+
+//(SWBE) S-CPU BW-RAM write enable
+void SA1::mmio_w2226(uint8_t data) {
+  mmio.swen = (data & 0x80);
+}
+
+//(CWBE) SA-1 BW-RAM write enable
+void SA1::mmio_w2227(uint8_t data) {
+  mmio.cwen = (data & 0x80);
+}
+
+//(BWPA) BW-RAM write-protected area
+void SA1::mmio_w2228(uint8_t data) {
+  mmio.bwp = (data & 0x0f);
+}
+
+//(SIWP) S-CPU I-RAM write protection
+void SA1::mmio_w2229(uint8_t data) {
+  mmio.siwp = data;
+}
+
+//(CIWP) SA-1 I-RAM write protection
+void SA1::mmio_w222a(uint8_t data) {
+  mmio.ciwp = data;
+}
+
+//(DCNT) DMA control
+void SA1::mmio_w2230(uint8_t data) {
+  mmio.dmaen = (data & 0x80);
+  mmio.dprio = (data & 0x40);
+  mmio.cden  = (data & 0x20);
+  mmio.cdsel = (data & 0x10);
+  mmio.dd    = (data & 0x04);
+  mmio.sd    = (data & 0x03);
+
+  if(mmio.dmaen == 0) dma.line = 0;
+}
+
+//(CDMA) character conversion DMA parameters
+void SA1::mmio_w2231(uint8_t data) {
+  mmio.chdend  = (data & 0x80);
+  mmio.dmasize = (data >> 2) & 7;
+  mmio.dmacb   = (data & 0x03);
+
+  if(mmio.chdend) memory::cc1bwram.dma = false;
+  if(mmio.dmasize > 5) mmio.dmasize = 5;
+  if(mmio.dmacb   > 2) mmio.dmacb   = 2;
+}
+
+//(SDA) DMA source device start address
+void SA1::mmio_w2232(uint8_t data) { mmio.dsa = (mmio.dsa & 0xffff00) | (data <<  0); }
+void SA1::mmio_w2233(uint8_t data) { mmio.dsa = (mmio.dsa & 0xff00ff) | (data <<  8); }
+void SA1::mmio_w2234(uint8_t data) { mmio.dsa = (mmio.dsa & 0x00ffff) | (data << 16); }
+
+//(DDA) DMA destination start address
+void SA1::mmio_w2235(uint8_t data) {
+  mmio.dda = (mmio.dda & 0xffff00) | (data <<  0);
+}
+
+void SA1::mmio_w2236(uint8_t data) {
+  mmio.dda = (mmio.dda & 0xff00ff) | (data <<  8);
+
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 0 && mmio.dd == DMA::DestIRAM) {
+      dma_normal();
+    } else if(mmio.cden == 1 && mmio.cdsel == 1) {
+      dma_cc1();
+    }
+  }
+}
+
+void SA1::mmio_w2237(uint8_t data) {
+  mmio.dda = (mmio.dda & 0x00ffff) | (data << 16);
+
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 0 && mmio.dd == DMA::DestBWRAM) {
+      dma_normal();
+    }
+  }
+}
+
+//(DTC) DMA terminal counter
+void SA1::mmio_w2238(uint8_t data) { mmio.dtc = (mmio.dtc & 0xff00) | (data << 0); }
+void SA1::mmio_w2239(uint8_t data) { mmio.dtc = (mmio.dtc & 0x00ff) | (data << 8); }
+
+//(BBF) BW-RAM bitmap format
+void SA1::mmio_w223f(uint8_t data) {
+  mmio.bbf = (data & 0x80);
+}
+
+//(BRF) bitmap register files
+void SA1::mmio_w2240(uint8_t data) { mmio.brf[ 0] = data; }
+void SA1::mmio_w2241(uint8_t data) { mmio.brf[ 1] = data; }
+void SA1::mmio_w2242(uint8_t data) { mmio.brf[ 2] = data; }
+void SA1::mmio_w2243(uint8_t data) { mmio.brf[ 3] = data; }
+void SA1::mmio_w2244(uint8_t data) { mmio.brf[ 4] = data; }
+void SA1::mmio_w2245(uint8_t data) { mmio.brf[ 5] = data; }
+void SA1::mmio_w2246(uint8_t data) { mmio.brf[ 6] = data; }
+void SA1::mmio_w2247(uint8_t data) { mmio.brf[ 7] = data;
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 1 && mmio.cdsel == 0) {
+      dma_cc2();
+    }
+  }
+}
+
+void SA1::mmio_w2248(uint8_t data) { mmio.brf[ 8] = data; }
+void SA1::mmio_w2249(uint8_t data) { mmio.brf[ 9] = data; }
+void SA1::mmio_w224a(uint8_t data) { mmio.brf[10] = data; }
+void SA1::mmio_w224b(uint8_t data) { mmio.brf[11] = data; }
+void SA1::mmio_w224c(uint8_t data) { mmio.brf[12] = data; }
+void SA1::mmio_w224d(uint8_t data) { mmio.brf[13] = data; }
+void SA1::mmio_w224e(uint8_t data) { mmio.brf[14] = data; }
+void SA1::mmio_w224f(uint8_t data) { mmio.brf[15] = data;
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 1 && mmio.cdsel == 0) {
+      dma_cc2();
+    }
+  }
+}
+
+//(MCNT) arithmetic control
+void SA1::mmio_w2250(uint8_t data) {
+  mmio.acm = (data & 0x02);
+  mmio.md  = (data & 0x01);
+
+  if(mmio.acm) mmio.mr = 0;
+}
+
+//(MAL) multiplicand / dividend low
+void SA1::mmio_w2251(uint8_t data) {
+  mmio.ma = (mmio.ma & 0xff00) | data;
+}
+
+//(MAH) multiplicand / dividend high
+void SA1::mmio_w2252(uint8_t data) {
+  mmio.ma = (data << 8) | (mmio.ma & 0x00ff);
+}
+
+//(MBL) multiplier / divisor low
+void SA1::mmio_w2253(uint8_t data) {
+  mmio.mb = (mmio.mb & 0xff00) | data;
+}
+
+//(MBH) multiplier / divisor high
+//multiplication / cumulative sum only resets MB
+//division resets both MA and MB
+void SA1::mmio_w2254(uint8_t data) {
+  mmio.mb = (data << 8) | (mmio.mb & 0x00ff);
+
+  if(mmio.acm == 0) {
+    if(mmio.md == 0) {
+      //signed multiplication
+      mmio.mr = (int16_t)mmio.ma * (int16_t)mmio.mb;
+      mmio.mb = 0;
+    } else {
+      //unsigned division
+      if(mmio.mb == 0) {
+        mmio.mr = 0;
+      } else {
+        int16_t  quotient  = (int16_t)mmio.ma / (uint16_t)mmio.mb;
+        uint16_t remainder = (int16_t)mmio.ma % (uint16_t)mmio.mb;
+        mmio.mr = (remainder << 16) | quotient;
+      }
+      mmio.ma = 0;
+      mmio.mb = 0;
+    }
+  } else {
+    //sigma (accumulative multiplication)
+    mmio.mr += (int16_t)mmio.ma * (int16_t)mmio.mb;
+    mmio.overflow = (mmio.mr >= (1ULL << 40));
+    mmio.mr &= (1ULL << 40) - 1;
+    mmio.mb = 0;
+  }
+}
+
+//(VBD) variable-length bit processing
+void SA1::mmio_w2258(uint8_t data) {
+  mmio.hl = (data & 0x80);
+  mmio.vb = (data & 0x0f);
+  if(mmio.vb == 0) mmio.vb = 16;
+
+  if(mmio.hl == 0) {
+    //fixed mode
+    mmio.vbit += mmio.vb;
+    mmio.va += (mmio.vbit >> 3);
+    mmio.vbit &= 7;
+  }
+}
+
+//(VDA) variable-length bit game pak ROM start address
+void SA1::mmio_w2259(uint8_t data) { mmio.va = (mmio.va & 0xffff00) | (data <<  0); }
+void SA1::mmio_w225a(uint8_t data) { mmio.va = (mmio.va & 0xff00ff) | (data <<  8); }
+void SA1::mmio_w225b(uint8_t data) { mmio.va = (mmio.va & 0x00ffff) | (data << 16); mmio.vbit = 0; }
+
+//(SFR) S-CPU flag read
+uint8_t SA1::mmio_r2300() {
+  uint8_t data;
+  data  = mmio.cpu_irqfl   << 7;
+  data |= mmio.cpu_ivsw    << 6;
+  data |= mmio.chdma_irqfl << 5;
+  data |= mmio.cpu_nvsw    << 4;
+  data |= mmio.cmeg;
+  return data;
+}
+
+//(CFR) SA-1 flag read
+uint8_t SA1::mmio_r2301() {
+  uint8_t data;
+  data  = mmio.sa1_irqfl   << 7;
+  data |= mmio.timer_irqfl << 6;
+  data |= mmio.dma_irqfl   << 5;
+  data |= mmio.sa1_nmifl   << 4;
+  data |= mmio.smeg;
+  return data;
+}
+
+//(HCR) hcounter read
+uint8_t SA1::mmio_r2302() {
+  //latch counters
+  mmio.hcr = status.hcounter >> 2;
+  mmio.vcr = status.vcounter;
+                            return mmio.hcr >> 0; }
+uint8_t SA1::mmio_r2303() { return mmio.hcr >> 8; }
+
+//(VCR) vcounter read
+uint8_t SA1::mmio_r2304() { return mmio.vcr >> 0; }
+uint8_t SA1::mmio_r2305() { return mmio.vcr >> 8; }
+
+//(MR) arithmetic result
+uint8_t SA1::mmio_r2306() { return mmio.mr >>  0; }
+uint8_t SA1::mmio_r2307() { return mmio.mr >>  8; }
+uint8_t SA1::mmio_r2308() { return mmio.mr >> 16; }
+uint8_t SA1::mmio_r2309() { return mmio.mr >> 24; }
+uint8_t SA1::mmio_r230a() { return mmio.mr >> 32; }
+
+//(OF) arithmetic overflow flag
+uint8_t SA1::mmio_r230b() { return mmio.overflow << 7; }
+
+//(VDPL) variable-length data read port low
+uint8_t SA1::mmio_r230c() {
+  uint32_t data = (sa1bus.read(mmio.va + 0) <<  0)
+                | (sa1bus.read(mmio.va + 1) <<  8)
+                | (sa1bus.read(mmio.va + 2) << 16);
+  data >>= mmio.vbit;
+  return data >> 0;
+}
+
+//(VDPH) variable-length data read port high
+uint8_t SA1::mmio_r230d() {
+  uint32_t data = (sa1bus.read(mmio.va + 0) <<  0)
+                | (sa1bus.read(mmio.va + 1) <<  8)
+                | (sa1bus.read(mmio.va + 2) << 16);
+  data >>= mmio.vbit;
+
+  if(mmio.hl == 1) {
+    //auto-increment mode
+    mmio.vbit += mmio.vb;
+    mmio.va += (mmio.vbit >> 3);
+    mmio.vbit &= 7;
+  }
+
+  return data >> 8;
+}
+
+//(VC) version code register
+uint8_t SA1::mmio_r230e() {
+  return 0x01;  //true value unknown
+}
+
+uint8_t SA1::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    case 0x2300: return mmio_r2300();
+    case 0x2301: return mmio_r2301();
+    case 0x2302: return mmio_r2302();
+    case 0x2303: return mmio_r2303();
+    case 0x2304: return mmio_r2304();
+    case 0x2305: return mmio_r2305();
+    case 0x2306: return mmio_r2306();
+    case 0x2307: return mmio_r2307();
+    case 0x2308: return mmio_r2308();
+    case 0x2309: return mmio_r2309();
+    case 0x230a: return mmio_r230a();
+    case 0x230b: return mmio_r230b();
+    case 0x230c: return mmio_r230c();
+    case 0x230d: return mmio_r230d();
+    case 0x230e: return mmio_r230e();
+  }
+
+  return 0x00;
+}
+
+void SA1::mmio_write(unsigned addr, uint8_t data) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    case 0x2200: return mmio_w2200(data);
+    case 0x2201: return mmio_w2201(data);
+    case 0x2202: return mmio_w2202(data);
+    case 0x2203: return mmio_w2203(data);
+    case 0x2204: return mmio_w2204(data);
+    case 0x2205: return mmio_w2205(data);
+    case 0x2206: return mmio_w2206(data);
+    case 0x2207: return mmio_w2207(data);
+    case 0x2208: return mmio_w2208(data);
+    case 0x2209: return mmio_w2209(data);
+    case 0x220a: return mmio_w220a(data);
+    case 0x220b: return mmio_w220b(data);
+    case 0x220c: return mmio_w220c(data);
+    case 0x220d: return mmio_w220d(data);
+    case 0x220e: return mmio_w220e(data);
+    case 0x220f: return mmio_w220f(data);
+
+    case 0x2210: return mmio_w2210(data);
+    case 0x2211: return mmio_w2211(data);
+    case 0x2212: return mmio_w2212(data);
+    case 0x2213: return mmio_w2213(data);
+    case 0x2214: return mmio_w2214(data);
+    case 0x2215: return mmio_w2215(data);
+
+    case 0x2220: return mmio_w2220(data);
+    case 0x2221: return mmio_w2221(data);
+    case 0x2222: return mmio_w2222(data);
+    case 0x2223: return mmio_w2223(data);
+    case 0x2224: return mmio_w2224(data);
+    case 0x2225: return mmio_w2225(data);
+    case 0x2226: return mmio_w2226(data);
+    case 0x2227: return mmio_w2227(data);
+    case 0x2228: return mmio_w2228(data);
+    case 0x2229: return mmio_w2229(data);
+    case 0x222a: return mmio_w222a(data);
+
+    case 0x2230: return mmio_w2230(data);
+    case 0x2231: return mmio_w2231(data);
+    case 0x2232: return mmio_w2232(data);
+    case 0x2233: return mmio_w2233(data);
+    case 0x2234: return mmio_w2234(data);
+    case 0x2235: return mmio_w2235(data);
+    case 0x2236: return mmio_w2236(data);
+    case 0x2237: return mmio_w2237(data);
+    case 0x2238: return mmio_w2238(data);
+    case 0x2239: return mmio_w2239(data);
+
+    case 0x223f: return mmio_w223f(data);
+    case 0x2240: return mmio_w2240(data);
+    case 0x2241: return mmio_w2241(data);
+    case 0x2242: return mmio_w2242(data);
+    case 0x2243: return mmio_w2243(data);
+    case 0x2244: return mmio_w2244(data);
+    case 0x2245: return mmio_w2245(data);
+    case 0x2246: return mmio_w2246(data);
+    case 0x2247: return mmio_w2247(data);
+    case 0x2248: return mmio_w2248(data);
+    case 0x2249: return mmio_w2249(data);
+    case 0x224a: return mmio_w224a(data);
+    case 0x224b: return mmio_w224b(data);
+    case 0x224c: return mmio_w224c(data);
+    case 0x224d: return mmio_w224d(data);
+    case 0x224e: return mmio_w224e(data);
+    case 0x224f: return mmio_w224f(data);
+
+    case 0x2250: return mmio_w2250(data);
+    case 0x2251: return mmio_w2251(data);
+    case 0x2252: return mmio_w2252(data);
+    case 0x2253: return mmio_w2253(data);
+    case 0x2254: return mmio_w2254(data);
+
+    case 0x2258: return mmio_w2258(data);
+    case 0x2259: return mmio_w2259(data);
+    case 0x225a: return mmio_w225a(data);
+    case 0x225b: return mmio_w225b(data);
+  }
+}
+
+#endif

src/chip/sa1/mmio/mmio.hpp

@@ -0,0 +1,256 @@
+uint8_t mmio_read(unsigned addr);
+void mmio_write(unsigned addr, uint8_t data);
+Memory& mmio_access(unsigned &addr);
+
+struct MMIO {
+  //$2200 CCNT
+  bool sa1_irq;
+  bool sa1_rdyb;
+  bool sa1_resb;
+  bool sa1_nmi;
+  uint8_t smeg;
+
+  //$2201 SIE
+  bool cpu_irqen;
+  bool chdma_irqen;
+
+  //$2202 SIC
+  bool cpu_irqcl;
+  bool chdma_irqcl;
+
+  //$2203,$2204 CRV
+  uint16_t crv;
+
+  //$2205,$2206 CNV
+  uint16_t cnv;
+
+  //$2207,$2208 CIV
+  uint16_t civ;
+
+  //$2209 SCNT
+  bool cpu_irq;
+  bool cpu_ivsw;
+  bool cpu_nvsw;
+  uint8_t cmeg;
+
+  //$220a CIE
+  bool sa1_irqen;
+  bool timer_irqen;
+  bool dma_irqen;
+  bool sa1_nmien;
+
+  //$220b CIC
+  bool sa1_irqcl;
+  bool timer_irqcl;
+  bool dma_irqcl;
+  bool sa1_nmicl;
+
+  //$220c,$220d SNV
+  uint16_t snv;
+
+  //$220e,$220f SIV
+  uint16_t siv;
+
+  //$2210 TMC
+  bool hvselb;
+  bool ven;
+  bool hen;
+
+  //$2212,$2213
+  uint16_t hcnt;
+
+  //$2214,$2215
+  uint16_t vcnt;
+
+  //$2220 CXB
+  bool cbmode;
+  uint8_t cb;
+
+  //$2221 DXB
+  bool dbmode;
+  uint8_t db;
+
+  //$2222 EXB
+  bool ebmode;
+  uint8_t eb;
+
+  //$2223 FXB
+  bool fbmode;
+  uint8_t fb;
+
+  //$2224 BMAPS
+  uint8_t sbm;
+
+  //$2225 BMAP
+  bool sw46;
+  uint8_t cbm;
+
+  //$2226 SBWE
+  bool swen;
+
+  //$2227 CBWE
+  bool cwen;
+
+  //$2228 BWPA
+  uint8_t bwp;
+
+  //$2229 SIWP
+  uint8_t siwp;
+
+  //$222a CIWP
+  uint8_t ciwp;
+
+  //$2230 DCNT
+  bool dmaen;
+  bool dprio;
+  bool cden;
+  bool cdsel;
+  bool dd;
+  uint8_t sd;
+
+  //$2231 CDMA
+  bool chdend;
+  uint8_t dmasize;
+  uint8_t dmacb;
+
+  //$2232-$2234 SDA
+  uint32_t dsa;
+
+  //$2235-$2237 DDA
+  uint32_t dda;
+
+  //$2238,$2239 DTC
+  uint16_t dtc;
+
+  //$223f BBF
+  bool bbf;
+
+  //$2240-224f BRF
+  uint8_t brf[16];
+
+  //$2250 MCNT
+  bool acm;
+  bool md;
+
+  //$2251,$2252 MA
+  uint16_t ma;
+
+  //$2253,$2254 MB
+  uint16_t mb;
+
+  //$2258 VBD
+  bool hl;
+  uint8_t vb;
+
+  //$2259-$225b VDA
+  uint32_t va;
+  uint8_t vbit;
+
+  //$2300 SFR
+  bool cpu_irqfl;
+  bool chdma_irqfl;
+
+  //$2301 CFR
+  bool sa1_irqfl;
+  bool timer_irqfl;
+  bool dma_irqfl;
+  bool sa1_nmifl;
+
+  //$2302,$2303 HCR
+  uint16_t hcr;
+
+  //$2304,$2305 VCR
+  uint16_t vcr;
+
+  //$2306-230a MR
+  uint64_t mr;
+
+  //$230b OF
+  bool overflow;
+} mmio;
+
+void mmio_w2200(uint8_t);  //CCNT
+void mmio_w2201(uint8_t);  //SIE
+void mmio_w2202(uint8_t);  //SIC
+void mmio_w2203(uint8_t);  //CRVL
+void mmio_w2204(uint8_t);  //CRVH
+void mmio_w2205(uint8_t);  //CNVL
+void mmio_w2206(uint8_t);  //CNVH
+void mmio_w2207(uint8_t);  //CIVL
+void mmio_w2208(uint8_t);  //CIVH
+void mmio_w2209(uint8_t);  //SCNT
+void mmio_w220a(uint8_t);  //CIE
+void mmio_w220b(uint8_t);  //CIC
+void mmio_w220c(uint8_t);  //SNVL
+void mmio_w220d(uint8_t);  //SNVH
+void mmio_w220e(uint8_t);  //SIVL
+void mmio_w220f(uint8_t);  //SIVH
+void mmio_w2210(uint8_t);  //TMC
+void mmio_w2211(uint8_t);  //CTR
+void mmio_w2212(uint8_t);  //HCNTL
+void mmio_w2213(uint8_t);  //HCNTH
+void mmio_w2214(uint8_t);  //VCNTL
+void mmio_w2215(uint8_t);  //VCNTH
+void mmio_w2220(uint8_t);  //CXB
+void mmio_w2221(uint8_t);  //DXB
+void mmio_w2222(uint8_t);  //EXB
+void mmio_w2223(uint8_t);  //FXB
+void mmio_w2224(uint8_t);  //BMAPS
+void mmio_w2225(uint8_t);  //BMAP
+void mmio_w2226(uint8_t);  //SBWE
+void mmio_w2227(uint8_t);  //CBWE
+void mmio_w2228(uint8_t);  //BWPA
+void mmio_w2229(uint8_t);  //SIWP
+void mmio_w222a(uint8_t);  //CIWP
+void mmio_w2230(uint8_t);  //DCNT
+void mmio_w2231(uint8_t);  //CDMA
+void mmio_w2232(uint8_t);  //SDAL
+void mmio_w2233(uint8_t);  //SDAH
+void mmio_w2234(uint8_t);  //SDAB
+void mmio_w2235(uint8_t);  //DDAL
+void mmio_w2236(uint8_t);  //DDAH
+void mmio_w2237(uint8_t);  //DDAB
+void mmio_w2238(uint8_t);  //DTCL
+void mmio_w2239(uint8_t);  //DTCH
+void mmio_w223f(uint8_t);  //BBF
+void mmio_w2240(uint8_t);  //BRF0
+void mmio_w2241(uint8_t);  //BRF1
+void mmio_w2242(uint8_t);  //BRF2
+void mmio_w2243(uint8_t);  //BRF3
+void mmio_w2244(uint8_t);  //BRF4
+void mmio_w2245(uint8_t);  //BRF5
+void mmio_w2246(uint8_t);  //BRF6
+void mmio_w2247(uint8_t);  //BRF7
+void mmio_w2248(uint8_t);  //BRF8
+void mmio_w2249(uint8_t);  //BRF9
+void mmio_w224a(uint8_t);  //BRFA
+void mmio_w224b(uint8_t);  //BRFB
+void mmio_w224c(uint8_t);  //BRFC
+void mmio_w224d(uint8_t);  //BRFD
+void mmio_w224e(uint8_t);  //BRFE
+void mmio_w224f(uint8_t);  //BRFF
+void mmio_w2250(uint8_t);  //MCNT
+void mmio_w2251(uint8_t);  //MAL
+void mmio_w2252(uint8_t);  //MAH
+void mmio_w2253(uint8_t);  //MBL
+void mmio_w2254(uint8_t);  //MBH
+void mmio_w2258(uint8_t);  //VBD
+void mmio_w2259(uint8_t);  //VDAL
+void mmio_w225a(uint8_t);  //VDAH
+void mmio_w225b(uint8_t);  //VDAB
+
+uint8_t mmio_r2300();  //SFR
+uint8_t mmio_r2301();  //CFR
+uint8_t mmio_r2302();  //HCRL
+uint8_t mmio_r2303();  //HCRH
+uint8_t mmio_r2304();  //VCRL
+uint8_t mmio_r2305();  //VCRH
+uint8_t mmio_r2306();  //MR [00-07]
+uint8_t mmio_r2307();  //MR [08-15]
+uint8_t mmio_r2308();  //MR [16-23]
+uint8_t mmio_r2309();  //MR [24-31]
+uint8_t mmio_r230a();  //MR [32-40]
+uint8_t mmio_r230b();  //OF
+uint8_t mmio_r230c();  //VDPL
+uint8_t mmio_r230d();  //VDPH
+uint8_t mmio_r230e();  //VC

src/chip/sa1/sa1.cpp

@@ -0,0 +1,317 @@
+#include <../base.hpp>
+
+#define SA1_CPP
+namespace SNES {
+
+SA1 sa1;
+
+#include "bus/bus.cpp"
+#include "dma/dma.cpp"
+#include "memory/memory.cpp"
+#include "mmio/mmio.cpp"
+
+void SA1::enter() {
+  while(true) {
+    while(mmio.sa1_rdyb || mmio.sa1_resb) {
+      //SA-1 co-processor is asleep
+      tick();
+      scheduler.sync_copcpu();
+    }
+
+    if(status.interrupt_pending) {
+      status.interrupt_pending = false;
+      interrupt(status.interrupt_vector);
+    }
+
+    (this->*opcode_table[op_readpc()])();
+  }
+}
+
+void SA1::last_cycle() {
+  if(mmio.sa1_nmi && !mmio.sa1_nmicl) {
+    status.interrupt_pending = true;
+    status.interrupt_vector  = mmio.cnv;
+    mmio.sa1_nmifl = true;
+    mmio.sa1_nmicl = 1;
+    regs.wai = false;
+  } else if(!regs.p.i) {
+    if(mmio.timer_irqen && !mmio.timer_irqcl) {
+      status.interrupt_pending = true;
+      status.interrupt_vector  = mmio.civ;
+      mmio.timer_irqfl = true;
+      regs.wai = false;
+    } else if(mmio.dma_irqen && !mmio.dma_irqcl) {
+      status.interrupt_pending = true;
+      status.interrupt_vector  = mmio.civ;
+      mmio.dma_irqfl = true;
+      regs.wai = false;
+    } else if(mmio.sa1_irq && !mmio.sa1_irqcl) {
+      status.interrupt_pending = true;
+      status.interrupt_vector  = mmio.civ;
+      mmio.sa1_irqfl = true;
+      regs.wai = false;
+    }
+  }
+}
+
+void SA1::interrupt(uint16_t vector) {
+  op_read(regs.pc.d);
+  op_io();
+  if(!regs.e) op_writestack(regs.pc.b);
+  op_writestack(regs.pc.h);
+  op_writestack(regs.pc.l);
+  op_writestack(regs.e ? (regs.p & ~0x10) : regs.p);
+  regs.pc.w = vector;
+  regs.pc.b = 0x00;
+  regs.p.i  = 1;
+  regs.p.d  = 0;
+}
+
+bool SA1::interrupt_pending() {
+  return status.interrupt_pending;
+}
+
+void SA1::tick() {
+  scheduler.addclocks_cop(2);
+
+  //adjust counters:
+  //note that internally, status counters are in clocks;
+  //whereas MMIO register counters are in dots (4 clocks = 1 dot)
+  if(mmio.hvselb == 0) {
+    //HV timer
+    status.hcounter += 2;
+    if(status.hcounter >= 1364) {
+      status.hcounter = 0;
+      if(++status.vcounter >= status.scanlines) status.vcounter = 0;
+    }
+  } else {
+    //linear timer
+    status.hcounter += 2;
+    status.vcounter += (status.hcounter >> 11);
+    status.hcounter &= 0x07ff;
+    status.vcounter &= 0x01ff;
+  }
+
+  //test counters for timer IRQ
+  switch((mmio.ven << 1) + (mmio.hen << 0)) {
+    case 0: break;
+    case 1: if(status.hcounter == (mmio.hcnt << 2)) trigger_irq(); break;
+    case 2: if(status.vcounter == mmio.vcnt && status.hcounter == 0) trigger_irq(); break;
+    case 3: if(status.vcounter == mmio.hcnt && status.hcounter == (mmio.hcnt << 2)) trigger_irq(); break;
+  }
+}
+
+void SA1::trigger_irq() {
+  mmio.timer_irqfl = true;
+  if(mmio.timer_irqen) mmio.timer_irqcl = 0;
+}
+
+void SA1::init() {
+}
+
+void SA1::enable() {
+}
+
+void SA1::power() {
+  regs.a = regs.x = regs.y = 0x0000;
+  regs.s = 0x01ff;
+
+  reset();
+}
+
+void SA1::reset() {
+  memory::vectorsp.access = 0;
+  memory::cc1bwram.dma = false;
+  for(unsigned addr = 0; addr < memory::iram.size(); addr++) {
+    memory::iram.write(addr, 0x00);
+  }
+  sa1bus.init();
+
+  regs.pc.d = 0x000000;
+  regs.x.h  = 0x00;
+  regs.y.h  = 0x00;
+  regs.s.h  = 0x01;
+  regs.d    = 0x0000;
+  regs.db   = 0x00;
+  regs.p    = 0x34;
+  regs.e    = 1;
+  regs.mdr  = 0x00;
+  regs.wai  = false;
+  update_table();
+
+  status.interrupt_pending = false;
+  status.interrupt_vector  = 0x0000;
+
+  status.scanlines = (system.region() == System::NTSC ? 262 : 312);
+  status.vcounter  = 0;
+  status.hcounter  = 0;
+
+  dma.line = 0;
+
+  //$2200 CCNT
+  mmio.sa1_irq  = false;
+  mmio.sa1_rdyb = false;
+  mmio.sa1_resb = true;
+  mmio.sa1_nmi  = false;
+  mmio.smeg     = 0;
+
+  //$2201 SIE
+  mmio.cpu_irqen   = false;
+  mmio.chdma_irqen = false;
+
+  //$2202 SIC
+  mmio.cpu_irqcl   = false;
+  mmio.chdma_irqcl = false;
+
+  //$2203,$2204 CRV
+  mmio.crv = 0x0000;
+
+  //$2205,$2206 CNV
+  mmio.cnv = 0x0000;
+
+  //$2207,$2208 CIV
+  mmio.civ = 0x0000;
+
+  //$2209 SCNT
+  mmio.cpu_irq  = false;
+  mmio.cpu_ivsw = false;
+  mmio.cpu_nvsw = false;
+  mmio.cmeg     = 0;
+
+  //$220a CIE
+  mmio.sa1_irqen   = false;
+  mmio.timer_irqen = false;
+  mmio.dma_irqen   = false;
+  mmio.sa1_nmien   = false;
+
+  //$220b CIC
+  mmio.sa1_irqcl   = false;
+  mmio.timer_irqcl = false;
+  mmio.dma_irqcl   = false;
+  mmio.sa1_nmicl   = false;
+
+  //$220c,$220d SNV
+  mmio.snv = 0x0000;
+
+  //$220e,$220f SIV
+  mmio.siv = 0x0000;
+
+  //$2210
+  mmio.hvselb = false;
+  mmio.ven    = false;
+  mmio.hen    = false;
+
+  //$2212,$2213 HCNT
+  mmio.hcnt = 0x0000;
+
+  //$2214,$2215 VCNT
+  mmio.vcnt = 0x0000;
+
+  //$2220-2223 CXB, DXB, EXB, FXB
+  mmio.cbmode = 0;
+  mmio.dbmode = 0;
+  mmio.ebmode = 0;
+  mmio.fbmode = 0;
+
+  mmio.cb = 0x00;
+  mmio.db = 0x01;
+  mmio.eb = 0x02;
+  mmio.fb = 0x03;
+
+  //$2224 BMAPS
+  mmio.sbm = 0x00;
+
+  //$2225 BMAP
+  mmio.sw46 = false;
+  mmio.cbm  = 0x00;
+
+  //$2226 SWBE
+  mmio.swen = false;
+
+  //$2227 CWBE
+  mmio.cwen = false;
+
+  //$2228 BWPA
+  mmio.bwp = 0x0f;
+
+  //$2229 SIWP
+  mmio.siwp = 0x00;
+
+  //$222a CIWP
+  mmio.ciwp = 0x00;
+
+  //$2230 DCNT
+  mmio.dmaen = false;
+  mmio.dprio = false;
+  mmio.cden  = false;
+  mmio.cdsel = false;
+  mmio.dd    = 0;
+  mmio.sd    = 0;
+
+  //$2231 CDMA
+  mmio.chdend  = false;
+  mmio.dmasize = 0;
+  mmio.dmacb   = 0;
+
+  //$2232-$2234 SDA
+  mmio.dsa = 0x000000;
+
+  //$2235-$2237 DDA
+  mmio.dda = 0x000000;
+
+  //$2238,$2239 DTC
+  mmio.dtc = 0x0000;
+
+  //$223f BBF
+  mmio.bbf = 0;
+
+  //$2240-$224f BRF
+  for(unsigned i = 0; i < 16; i++) {
+    mmio.brf[i] = 0x00;
+  }
+
+  //$2250 MCNT
+  mmio.acm = 0;
+  mmio.md  = 0;
+
+  //$2251,$2252 MA
+  mmio.ma = 0x0000;
+
+  //$2253,$2254 MB
+  mmio.mb = 0x0000;
+
+  //$2258 VBD
+  mmio.hl = false;
+  mmio.vb = 16;
+
+  //$2259-$225b
+  mmio.va   = 0x000000;
+  mmio.vbit = 0;
+
+  //$2300 SFR
+  mmio.cpu_irqfl   = false;
+  mmio.chdma_irqfl = false;
+
+  //$2301 CFR
+  mmio.sa1_irqfl   = false;
+  mmio.timer_irqfl = false;
+  mmio.dma_irqfl   = false;
+  mmio.sa1_nmifl   = false;
+
+  //$2302,$2303 HCR
+  mmio.hcr = 0x0000;
+
+  //$2304,$2305 VCR
+  mmio.vcr = 0x0000;
+
+  //$2306-$230a MR
+  mmio.mr = 0;
+
+  //$230b
+  mmio.overflow = false;
+}
+
+SA1::SA1() {
+}
+
+};

src/chip/sa1/sa1.hpp

@@ -0,0 +1,35 @@
+#include "bus/bus.hpp"
+
+class SA1 : public CPUcore, public MMIO {
+public:
+  #include "dma/dma.hpp"
+  #include "memory/memory.hpp"
+  #include "mmio/mmio.hpp"
+
+  struct Status {
+    bool interrupt_pending;
+    uint16_t interrupt_vector;
+
+    uint16_t scanlines;
+    uint16_t vcounter;
+    uint16_t hcounter;
+  } status;
+
+  void enter();
+  void interrupt(uint16_t vector);
+  void tick();
+
+  alwaysinline void trigger_irq();
+  alwaysinline void last_cycle();
+  alwaysinline bool interrupt_pending();
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  SA1();
+};
+
+extern SA1 sa1;
+extern SA1Bus sa1bus;

src/chip/sdd1/sdd1.cpp

@@ -1,12 +1,26 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define SDD1_CPP
+namespace SNES {
+
+SDD1 sdd1;
 
 #include "sdd1emu.cpp"
 
 void SDD1::init() {}
 
 void SDD1::enable() {
-  for(int i = 0x4800; i <= 0x4807; i++) memory::mmio.map(i, *this);
+  //hook S-CPU DMA MMIO registers to gather information for struct dma[];
+  //buffer address and transfer size information for use in SDD1::read()
+  for(unsigned i = 0x4300; i <= 0x437f; i++) {
+    cpu_mmio[i & 0x7f] = memory::mmio.mmio[i - 0x2000];
+    memory::mmio.map(i, *this);
+  }
+
+  //hook S-DD1 MMIO registers
+  for(unsigned i = 0x4800; i <= 0x4807; i++) {
+    memory::mmio.map(i, *this);
+  }
 }
 
 void SDD1::power() {
@@ -14,97 +28,135 @@ void SDD1::power() {
 }
 
 void SDD1::reset() {
-  sdd1.dma_active = false;
+  sdd1_enable = 0x00;
+  xfer_enable = 0x00;
 
-  regs.r4800 = 0x00;
-  regs.r4801 = 0x00;
+  mmc[0] = 0 << 20;
+  mmc[1] = 1 << 20;
+  mmc[2] = 2 << 20;
+  mmc[3] = 3 << 20;
 
-  regs.r4804 = 0x00;
-  regs.r4805 = 0x01;
-  regs.r4806 = 0x02;
-  regs.r4807 = 0x03;
+  for(unsigned i = 0; i < 8; i++) {
+    dma[i].addr = 0;
+    dma[i].size = 0;
+  }
 
-  bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, memory::cartrom, (regs.r4804 & 7) << 20);
-  bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, memory::cartrom, (regs.r4805 & 7) << 20);
-  bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, memory::cartrom, (regs.r4806 & 7) << 20);
-  bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, memory::cartrom, (regs.r4807 & 7) << 20);
+  buffer.ready = false;
+
+  bus.map(Bus::MapDirect, 0xc0, 0xff, 0x0000, 0xffff, *this);
 }
 
-uint8 SDD1::mmio_read(uint addr) {
-  switch(addr & 0xffff) {
-    case 0x4804: return regs.r4804;
-    case 0x4805: return regs.r4805;
-    case 0x4806: return regs.r4806;
-    case 0x4807: return regs.r4807;
+uint8 SDD1::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+
+  if((addr & 0x4380) == 0x4300) {
+    return cpu_mmio[addr & 0x7f]->mmio_read(addr);
+  }
+
+  switch(addr) {
+    case 0x4804: return (mmc[0] >> 20) & 7;
+    case 0x4805: return (mmc[1] >> 20) & 7;
+    case 0x4806: return (mmc[2] >> 20) & 7;
+    case 0x4807: return (mmc[3] >> 20) & 7;
   }
 
   return cpu.regs.mdr;
 }
 
-void SDD1::mmio_write(uint addr, uint8 data) {
-  switch(addr & 0xffff) {
-    case 0x4800: {
-      regs.r4800 = data;
-    } break;
+void SDD1::mmio_write(unsigned addr, uint8 data) {
+  addr &= 0xffff;
 
-    case 0x4801: {
-      regs.r4801 = data;
-    } break;
+  if((addr & 0x4380) == 0x4300) {
+    unsigned channel = (addr >> 4) & 7;
+    switch(addr & 15) {
+      case 2: dma[channel].addr = (dma[channel].addr & 0xffff00) + (data <<  0); break;
+      case 3: dma[channel].addr = (dma[channel].addr & 0xff00ff) + (data <<  8); break;
+      case 4: dma[channel].addr = (dma[channel].addr & 0x00ffff) + (data << 16); break;
 
-    case 0x4804: {
-      if(regs.r4804 != data) {
-        regs.r4804 = data;
-        bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4804 & 7) << 20);
+      case 5: dma[channel].size = (dma[channel].size &   0xff00) + (data <<  0); break;
+      case 6: dma[channel].size = (dma[channel].size &   0x00ff) + (data <<  8); break;
     }
-    } break;
-
-    case 0x4805: {
-      if(regs.r4805 != data) {
-        regs.r4805 = data;
-        bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4805 & 7) << 20);
+    return cpu_mmio[addr & 0x7f]->mmio_write(addr, data);
   }
-    } break;
 
-    case 0x4806: {
-      if(regs.r4806 != data) {
-        regs.r4806 = data;
-        bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4806 & 7) << 20);
-      }
-    } break;
+  switch(addr) {
+    case 0x4800: sdd1_enable = data; break;
+    case 0x4801: xfer_enable = data; break;
 
-    case 0x4807: {
-      if(regs.r4807 != data) {
-        regs.r4807 = data;
-        bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4807 & 7) << 20);
-      }
-    } break;
+    case 0x4804: mmc[0] = (data & 7) << 20; break;
+    case 0x4805: mmc[1] = (data & 7) << 20; break;
+    case 0x4806: mmc[2] = (data & 7) << 20; break;
+    case 0x4807: mmc[3] = (data & 7) << 20; break;
   }
 }
 
-void SDD1::dma_begin(uint8 channel, uint32 addr, uint16 length) {
-  if(regs.r4800 & (1 << channel) && regs.r4801 & (1 << channel)) {
-    regs.r4801 &= ~(1 << channel);
-    sdd1.dma_active   = true;
-    sdd1.buffer_index = 0;
-    sdd1.buffer_size  = length;
-    sdd1emu.decompress(addr, (length) ? length : 65536, sdd1.buffer);
+//SDD1::read() is mapped to $[c0-ff]:[0000-ffff]
+//the design is meant to be as close to the hardware design as possible, thus this code
+//avoids adding S-DD1 hooks inside S-CPU::DMA emulation.
+//
+//the real S-DD1 cannot see $420b (DMA enable) writes, as they are not placed on the bus.
+//however, $43x0-$43xf writes (DMAx channel settings) most likely do appear on the bus.
+//the S-DD1 also requires fixed addresses for transfers, which wouldn't be necessary if
+//it could see $420b writes (eg it would know when the transfer should begin.)
+//
+//the hardware needs a way to distinguish program code after $4801 writes from DMA
+//decompression that follows soon after.
+//
+//the only plausible design for hardware would be for the S-DD1 to spy on DMAx settings,
+//and begin spooling decompression on writes to $4801 that activate a channel. after that,
+//it feeds decompressed data only when the ROM read address matches the DMA channel address.
+//
+//the actual S-DD1 transfer can occur on any channel, but it is most likely limited to
+//one transfer per $420b write (for spooling purposes). however, this is not known for certain.
+uint8 SDD1::read(unsigned addr) {
+  if(sdd1_enable & xfer_enable) {
+    //at least one channel has S-DD1 decompression enabled ...
+    for(unsigned i = 0; i < 8; i++) {
+      if(sdd1_enable & xfer_enable & (1 << i)) {
+        //S-DD1 always uses fixed transfer mode, so address will not change during transfer
+        if(addr == dma[i].addr) {
+          if(!buffer.ready) {
+            //first byte read for channel performs full decompression.
+            //this really should stream byte-by-byte, but it's not necessary since the size is known
+            buffer.offset = 0;
+            buffer.size = dma[i].size ? dma[i].size : 65536;
+
+            //sdd1emu calls this function; it needs to access uncompressed data;
+            //so temporarily disable decompression mode for decompress() call.
+            uint8 temp = sdd1_enable;
+            sdd1_enable = false;
+            sdd1emu.decompress(addr, buffer.size, buffer.data);
+            sdd1_enable = temp;
+
+            buffer.ready = true;
           }
+
+          //fetch a decompressed byte; once buffer is depleted, disable channel and invalidate buffer
+          uint8 data = buffer.data[(uint16)buffer.offset++];
+          if(buffer.offset >= buffer.size) {
+            buffer.ready = false;
+            xfer_enable &= ~(1 << i);
+          }
+
+          return data;
+        }  //address matched
+      }  //channel enabled
+    }  //channel loop
+  }  //S-DD1 decompressor enabled
+
+  //S-DD1 decompression mode inactive; return ROM data
+  return memory::cartrom.read(mmc[(addr >> 20) & 3] + (addr & 0x0fffff));
 }
 
-bool SDD1::dma_active() {
-  return sdd1.dma_active;
+void SDD1::write(unsigned addr, uint8 data) {
 }
 
-uint8 SDD1::dma_read() {
-  if(--sdd1.buffer_size == 0) sdd1.dma_active = false;
-
-//sdd1.buffer[] is 65536 bytes, and sdd1.buffer_index
-//is of type uint16, so no buffer overflow is possible
-  return sdd1.buffer[sdd1.buffer_index++];
+SDD1::SDD1() {
+  buffer.data = new uint8[65536];
 }
 
-SDD1::SDD1() {}
+SDD1::~SDD1() {
+  delete[] buffer.data;
+}
+
+};

src/chip/sdd1/sdd1.h

@@ -1,39 +0,0 @@
-#include "sdd1emu.h"
-
-class SDD1 : public MMIO {
-public:
-  void init();
-  void enable();
-  void power();
-  void reset();
-
-  uint8 mmio_read (uint addr);
-  void  mmio_write(uint addr, uint8 data);
-
-  void  dma_begin(uint8 channel, uint32 addr, uint16 length);
-  bool  dma_active();
-  uint8 dma_read();
-
-  SDD1();
-
-private:
-  SDD1emu sdd1emu;
-
-  struct {
-    uint8  buffer[65536]; //pointer to decompressed S-DD1 data, max DMA length is 65536
-    uint16 buffer_index;  //DMA read index into S-DD1 decompression buffer
-    uint16 buffer_size;
-    bool   dma_active;
-  } sdd1;
-
-  struct {
-    uint8 r4800;
-    uint8 r4801;
-    uint8 r4804;
-    uint8 r4805;
-    uint8 r4806;
-    uint8 r4807;
-  } regs;
-};
-
-extern SDD1 sdd1;

src/chip/sdd1/sdd1.hpp

@@ -0,0 +1,40 @@
+#include "sdd1emu.hpp"
+
+class SDD1 : public MMIO, public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
+
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
+
+  SDD1();
+  ~SDD1();
+
+private:
+  MMIO *cpu_mmio[0x80];  //bus spying hooks to glean information for struct dma[]
+
+  uint8 sdd1_enable;     //channel bit-mask
+  uint8 xfer_enable;     //channel bit-mask
+  unsigned mmc[4];       //memory map controller ROM indices
+
+  struct {
+    unsigned addr;       //$43x2-$43x4 -- DMA transfer address
+    uint16 size;         //$43x5-$43x6 -- DMA transfer size
+  } dma[8];
+
+  SDD1emu sdd1emu;
+  struct {
+    uint8 *data;         //pointer to decompressed S-DD1 data (65536 bytes)
+    uint16 offset;       //read index into S-DD1 decompression buffer
+    unsigned size;       //length of data buffer; reads decrement counter, set ready to false at 0
+    bool ready;          //true when data[] is valid; false to invoke sdd1emu.decompress()
+  } buffer;
+};
+
+extern SDD1 sdd1;

src/chip/sdd1/sdd1emu.cpp

@@ -30,7 +30,7 @@ understood.
 
 ************************************************************************/
 
-#define SDD1_read(__addr) (bus.read(__addr))
+#define SDD1_read(__addr) (sdd1.read(__addr))
 
 ////////////////////////////////////////////////////
 
@@ -448,4 +448,4 @@ SDD1emu::SDD1emu() :
 
 ///////////////////////////////////////////////////////////
 
-#endif //ifdef SDD1_CPP
+#endif

src/chip/sgb/sgb.cpp

@@ -0,0 +1,65 @@
+#include <../base.hpp>
+
+#define SGB_CPP
+namespace SNES {
+
+SuperGameBoy sgb;
+
+void SuperGameBoy::enter() {
+  while(true) {
+    if(sgb_run) {
+      unsigned samples = sgb_run(samplebuffer, 16);
+      scheduler.addclocks_cop(samples * 10);
+      scheduler.sync_copcpu();
+    } else {
+      scheduler.addclocks_cop(64 * 1024 * 1024);
+      scheduler.sync_copcpu();
+    }
+  }
+}
+
+uint8_t SuperGameBoy::read(unsigned addr) {
+  addr &= 0xffff;
+  if(sgb_read) return sgb_read(addr);
+  return 0x00;
+}
+
+void SuperGameBoy::write(unsigned addr, uint8_t data) {
+  addr &= 0xffff;
+  if(sgb_write) return sgb_write(addr, data);
+}
+
+void SuperGameBoy::init() {
+  if(libsgb.open("SuperGameBoy")) {
+    sgb_init  = libsgb.sym("sgb_init");
+    sgb_term  = libsgb.sym("sgb_term");
+    sgb_power = libsgb.sym("sgb_power");
+    sgb_reset = libsgb.sym("sgb_reset");
+    sgb_read  = libsgb.sym("sgb_read");
+    sgb_write = libsgb.sym("sgb_write");
+    sgb_run   = libsgb.sym("sgb_run");
+  }
+}
+
+void SuperGameBoy::enable() {
+}
+
+void SuperGameBoy::power() {
+  bus.map(Bus::MapDirect, 0x00, 0x3f, 0x6000, 0x7fff, *this);
+  bus.map(Bus::MapDirect, 0x80, 0xbf, 0x6000, 0x7fff, *this);
+
+  if(sgb_init) {
+    sgb_init(SGB2,
+      memory::gbrom.data(), memory::gbrom.size(),
+      memory::gbram.data(), memory::gbram.size()
+    );
+  }
+
+  if(sgb_power) sgb_power();
+}
+
+void SuperGameBoy::reset() {
+  if(sgb_reset) sgb_reset();
+}
+
+};

src/chip/sgb/sgb.hpp

@@ -0,0 +1,27 @@
+class SuperGameBoy : public Memory {
+public:
+  void enter();
+
+  uint8_t read(unsigned addr);
+  void write(unsigned addr, uint8_t data);
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+private:
+  library libsgb;
+  uint32_t samplebuffer[4096];
+
+  enum { SGB1 = 0, SGB2 = 1 };
+  function<bool (bool, uint8_t*, unsigned, uint8_t*, unsigned)> sgb_init;
+  function<void ()> sgb_term;
+  function<void ()> sgb_power;
+  function<void ()> sgb_reset;
+  function<uint8_t (unsigned)> sgb_read;
+  function<void (unsigned, uint8_t)> sgb_write;
+  function<unsigned (uint32_t*, unsigned)> sgb_run;
+};
+
+extern SuperGameBoy sgb;

src/chip/spc7110/spc7110.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define SPC7110_CPP
+namespace SNES {
+
+SPC7110 spc7110;
 
 #include "decomp.cpp"
 
@@ -8,7 +12,7 @@ const unsigned SPC7110::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 3
 void SPC7110::init() {}
 
 void SPC7110::enable() {
-  uint16_t limit = (cartridge.info.spc7110rtc ? 0x4842 : 0x483f);
+  uint16_t limit = (cartridge.has_spc7110rtc() ? 0x4842 : 0x483f);
   for(uint16_t i = 0x4800; i <= limit; i++) memory::mmio.map(i, *this);
 }
 
@@ -72,7 +76,7 @@ void SPC7110::reset() {
   r4841 = 0x00;
   r4842 = 0x00;
 
-  if(cartridge.info.spc7110rtc) {
+  if(cartridge.has_spc7110rtc()) {
     rtc_state = RTCS_Inactive;
     rtc_mode  = RTCM_Linear;
     rtc_index = 0;
@@ -92,18 +96,30 @@ void SPC7110::set_data_pointer(unsigned addr) { r4811 = addr; r4812 = addr >> 8;
 void SPC7110::set_data_adjust(unsigned addr)  { r4814 = addr; r4815 = addr >> 8; }
 
 void SPC7110::update_time(int offset) {
-  time_t rtc_time;
-  rtc_time  = memory::cartrtc.read(16);
-  rtc_time |= memory::cartrtc.read(17) << 8;
-  rtc_time |= memory::cartrtc.read(18) << 16;
-  rtc_time |= memory::cartrtc.read(19) << 24;
+  time_t rtc_time
+  = (memory::cartrtc.read(16) <<  0)
+  | (memory::cartrtc.read(17) <<  8)
+  | (memory::cartrtc.read(18) << 16)
+  | (memory::cartrtc.read(19) << 24);
+  time_t current_time = time(0) - offset;
+
+  //sizeof(time_t) is platform-dependent; though memory::cartrtc needs to be platform-agnostic.
+  //yet platforms with 32-bit signed time_t will overflow every ~68 years. handle this by
+  //accounting for overflow at the cost of 1-bit precision (to catch underflow). this will allow
+  //memory::cartrtc timestamp to remain valid for up to ~34 years from the last update, even if
+  //time_t overflows. calculation should be valid regardless of number representation, time_t size,
+  //or whether time_t is signed or unsigned.
+  time_t diff
+  = (current_time >= rtc_time)
+  ? (current_time - rtc_time)
+  : (std::numeric_limits<time_t>::max() - rtc_time + current_time + 1);  //compensate for overflow
+  if(diff > std::numeric_limits<time_t>::max() / 2) diff = 0;            //compensate for underflow
 
   bool update = true;
   if(memory::cartrtc.read(13) & 1) update = false;  //do not update if CR0 timer disable flag is set
   if(memory::cartrtc.read(15) & 3) update = false;  //do not update if CR2 timer disable flags are set
 
-  time_t current_time = time(0) - offset;
-  if(update && current_time > rtc_time) {
+  if(diff > 0 && update == true) {
     unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
     unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
     unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
@@ -116,7 +132,7 @@ void SPC7110::update_time(int offset) {
     month--;
     year += (year >= 90) ? 1900 : 2000;  //range = 1990-2089
 
-    second += (unsigned)(current_time - rtc_time);
+    second += diff;
     while(second >= 60) {
       second -= 60;
 
@@ -168,13 +184,13 @@ void SPC7110::update_time(int offset) {
     memory::cartrtc.write(12, weekday % 7);
   }
 
-  memory::cartrtc.write(16, current_time);
+  memory::cartrtc.write(16, current_time >>  0);
   memory::cartrtc.write(17, current_time >>  8);
   memory::cartrtc.write(18, current_time >> 16);
   memory::cartrtc.write(19, current_time >> 24);
 }
 
-uint8 SPC7110::mmio_read(uint addr) {
+uint8 SPC7110::mmio_read(unsigned addr) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -322,7 +338,7 @@ uint8 SPC7110::mmio_read(uint addr) {
   return cpu.regs.mdr;
 }
 
-void SPC7110::mmio_write(uint addr, uint8 data) {
+void SPC7110::mmio_write(unsigned addr, uint8 data) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -615,7 +631,7 @@ void SPC7110::mmio_write(uint addr, uint8 data) {
   }
 }
 
-uint8 SPC7110::read(uint addr) {
+uint8 SPC7110::read(unsigned addr) {
   //$[00-0f|80-8f]:[8000-ffff], $[c0-cf]:[0000-ffff] mapped directly to memory::cartrom
 
   if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
@@ -646,7 +662,7 @@ uint8 SPC7110::read(uint addr) {
   return cpu.regs.mdr;
 }
 
-void SPC7110::write(uint addr, uint8 data) {
+void SPC7110::write(unsigned addr, uint8 data) {
   if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
     //$[00|30]:[6000-7fff]
     if(r4830 & 0x80) memory::cartram.write(addr & 0x1fff, data);
@@ -656,3 +672,5 @@ void SPC7110::write(uint addr, uint8 data) {
 
 SPC7110::SPC7110() {
 }
+
+};

src/chip/spc7110/spc7110.hpp

@@ -15,7 +15,7 @@
  * or in connection with the use or performance of this software.
  *****/
 
-#include "decomp.h"
+#include "decomp.hpp"
 
 class SPC7110 : public MMIO, public Memory {
 public:
@@ -35,11 +35,11 @@ public:
   void update_time(int offset = 0);
   time_t create_time();
 
-  uint8 mmio_read (uint addr);
-  void  mmio_write(uint addr, uint8 data);
+  uint8 mmio_read (unsigned addr);
+  void  mmio_write(unsigned addr, uint8 data);
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
 
   //spc7110decomp
   void decomp_init();

src/chip/srtc/srtc.cpp

@@ -1,4 +1,9 @@
-#include "../../base.h"
+#include <../base.hpp>
+
+#define SRTC_CPP
+namespace SNES {
+
+SRTC srtc;
 
 const unsigned SRTC::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
 
@@ -21,14 +26,26 @@ void SRTC::reset() {
 }
 
 void SRTC::update_time() {
-  time_t rtc_time;
-  rtc_time  = memory::cartrtc.read(16);
-  rtc_time |= memory::cartrtc.read(17) << 8;
-  rtc_time |= memory::cartrtc.read(18) << 16;
-  rtc_time |= memory::cartrtc.read(19) << 24;
-
+  time_t rtc_time
+  = (memory::cartrtc.read(16) <<  0)
+  | (memory::cartrtc.read(17) <<  8)
+  | (memory::cartrtc.read(18) << 16)
+  | (memory::cartrtc.read(19) << 24);
   time_t current_time = time(0);
-  if(current_time > rtc_time) {
+
+  //sizeof(time_t) is platform-dependent; though memory::cartrtc needs to be platform-agnostic.
+  //yet platforms with 32-bit signed time_t will overflow every ~68 years. handle this by
+  //accounting for overflow at the cost of 1-bit precision (to catch underflow). this will allow
+  //memory::cartrtc timestamp to remain valid for up to ~34 years from the last update, even if
+  //time_t overflows. calculation should be valid regardless of number representation, time_t size,
+  //or whether time_t is signed or unsigned.
+  time_t diff
+  = (current_time >= rtc_time)
+  ? (current_time - rtc_time)
+  : (std::numeric_limits<time_t>::max() - rtc_time + current_time + 1);  //compensate for overflow
+  if(diff > std::numeric_limits<time_t>::max() / 2) diff = 0;            //compensate for underflow
+
+  if(diff > 0) {
     unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
     unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
     unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
@@ -41,8 +58,7 @@ void SRTC::update_time() {
     month--;
     year += 1000;
 
-    second += (unsigned)(current_time - rtc_time);
-
+    second += diff;
     while(second >= 60) {
       second -= 60;
 
@@ -94,7 +110,7 @@ void SRTC::update_time() {
     memory::cartrtc.write(12, weekday % 7);
   }
 
-  memory::cartrtc.write(16, current_time);
+  memory::cartrtc.write(16, current_time >>  0);
   memory::cartrtc.write(17, current_time >>  8);
   memory::cartrtc.write(18, current_time >> 16);
   memory::cartrtc.write(19, current_time >> 24);
@@ -211,3 +227,5 @@ void SRTC::mmio_write(unsigned addr, uint8 data) {
 
 SRTC::SRTC() {
 }
+
+};

src/chip/st010/st010.cpp

@@ -1,7 +1,11 @@
-#include "../../base.h"
-#define ST010_CPP
+#include <../base.hpp>
 
-#include "st010_data.h"
+#define ST010_CPP
+namespace SNES {
+
+ST010 st010;
+
+#include "st010_data.hpp"
 #include "st010_op.cpp"
 
 int16 ST010::sin(int16 theta) {
@@ -62,11 +66,11 @@ void ST010::reset() {
 
 //
 
-uint8 ST010::read(uint addr) {
+uint8 ST010::read(unsigned addr) {
   return readb(addr);
 }
 
-void ST010::write(uint addr, uint8 data) {
+void ST010::write(unsigned addr, uint8 data) {
   writeb(addr, data);
 
   if((addr & 0xfff) == 0x0021 && (data & 0x80)) {
@@ -84,3 +88,5 @@ void ST010::write(uint addr, uint8 data) {
     ram[0x0021] &= ~0x80;
   }
 }
+
+};

src/chip/st010/st010.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
 
 private:
   uint8 ram[0x1000];

src/chip/st010/st010_op.cpp

@@ -258,4 +258,4 @@ int16 x1, y1;
   writew(0x0012, y1);
 }
 
-#endif //ifdef ST010_CPP
+#endif

src/chip/superfx/bus/bus.cpp

@@ -0,0 +1,92 @@
+#ifdef SUPERFX_CPP
+
+SuperFXBus superfxbus;
+
+namespace memory {
+  static SuperFXGSUROM gsurom;
+  static SuperFXGSURAM gsuram;
+  static SuperFXCPUROM fxrom;
+  static SuperFXCPURAM fxram;
+};
+
+void SuperFXBus::init() {
+  map(MapDirect, 0x00, 0xff, 0x0000, 0xffff, memory::memory_unmapped);
+
+  map(MapLinear, 0x00, 0x3f, 0x0000, 0x7fff, memory::gsurom);
+  map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::gsurom);
+  map(MapLinear, 0x40, 0x5f, 0x0000, 0xffff, memory::gsurom);
+  map(MapLinear, 0x60, 0x7f, 0x0000, 0xffff, memory::gsuram);
+
+  bus.map(MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::fxram, 0x0000, 0x2000);
+  bus.map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::fxrom);
+  bus.map(MapLinear, 0x40, 0x5f, 0x0000, 0xffff, memory::fxrom);
+  bus.map(MapLinear, 0x60, 0x7d, 0x0000, 0xffff, memory::fxram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::fxram, 0x0000, 0x2000);
+  bus.map(MapLinear, 0x80, 0xbf, 0x8000, 0xffff, memory::fxrom);
+  bus.map(MapLinear, 0xc0, 0xdf, 0x0000, 0xffff, memory::fxrom);
+  bus.map(MapLinear, 0xe0, 0xff, 0x0000, 0xffff, memory::fxram);
+}
+
+//ROM / RAM access from the SuperFX CPU
+
+unsigned SuperFXGSUROM::size() const {
+  return memory::cartrom.size();
+}
+
+uint8_t SuperFXGSUROM::read(unsigned addr) {
+  while(!superfx.regs.scmr.ron) superfx.add_clocks(2);
+  return memory::cartrom.read(addr);
+}
+
+void SuperFXGSUROM::write(unsigned addr, uint8_t data) {
+}
+
+unsigned SuperFXGSURAM::size() const {
+  return memory::cartram.size();
+}
+
+uint8_t SuperFXGSURAM::read(unsigned addr) {
+  while(!superfx.regs.scmr.ran) superfx.add_clocks(2);
+  return memory::cartram.read(addr);
+}
+
+void SuperFXGSURAM::write(unsigned addr, uint8_t data) {
+  while(!superfx.regs.scmr.ran) superfx.add_clocks(2);
+  memory::cartram.write(addr, data);
+}
+
+//ROM / RAM access from the S-CPU
+
+unsigned SuperFXCPUROM::size() const {
+  return memory::cartrom.size();
+}
+
+uint8_t SuperFXCPUROM::read(unsigned addr) {
+  if(superfx.regs.sfr.g && superfx.regs.scmr.ron) {
+    static const uint8_t data[16] = {
+      0x00, 0x01, 0x00, 0x01, 0x04, 0x01, 0x00, 0x01,
+      0x00, 0x01, 0x08, 0x01, 0x00, 0x01, 0x0c, 0x01,
+    };
+    return data[addr & 15];
+  }
+  return memory::cartrom.read(addr);
+}
+
+void SuperFXCPUROM::write(unsigned addr, uint8_t data) {
+  memory::cartrom.write(addr, data);
+}
+
+unsigned SuperFXCPURAM::size() const {
+  return memory::cartram.size();
+}
+
+uint8_t SuperFXCPURAM::read(unsigned addr) {
+  if(superfx.regs.sfr.g && superfx.regs.scmr.ran) return cpu.regs.mdr;
+  return memory::cartram.read(addr);
+}
+
+void SuperFXCPURAM::write(unsigned addr, uint8_t data) {
+  memory::cartram.write(addr, data);
+}
+
+#endif

src/chip/superfx/bus/bus.hpp

@@ -0,0 +1,27 @@
+struct SuperFXBus : Bus {
+  void init();
+};
+
+struct SuperFXGSUROM : Memory {
+  unsigned size() const;
+  uint8_t read(unsigned);
+  void write(unsigned, uint8_t);
+};
+
+struct SuperFXGSURAM : Memory {
+  unsigned size() const;
+  uint8_t read(unsigned);
+  void write(unsigned, uint8_t);
+};
+
+struct SuperFXCPUROM : Memory {
+  unsigned size() const;
+  uint8_t read(unsigned);
+  void write(unsigned, uint8_t);
+};
+
+struct SuperFXCPURAM : Memory {
+  unsigned size() const;
+  uint8_t read(unsigned);
+  void write(unsigned, uint8_t);
+};

src/chip/superfx/core/core.cpp

@@ -0,0 +1,121 @@
+#ifdef SUPERFX_CPP
+
+#include "opcodes.cpp"
+#include "opcode_table.cpp"
+
+void SuperFX::exec_opcode() {
+  #if 0
+  if(!fp) fp = fopen("sfxtrace.log", "wb");
+  char t[4096];
+  disassemble_opcode(t);
+  fprintf(fp, "%s ", t);
+  for(unsigned i = 0; i < 16; i++) fprintf(fp, "r%u:%.4x ", i, (uint16_t)regs.r[i]);
+  fprintf(fp, "\n");
+  #endif
+
+  (this->*opcode_table[(regs.sfr & 0x0300) + peekpipe()])();
+  if(r15_modified == false) regs.r[15]++;
+}
+
+uint8_t SuperFX::color(uint8_t source) {
+  if(regs.por.highnibble) return (regs.colr & 0xf0) | (source >> 4);
+  if(regs.por.freezehigh) return (regs.colr & 0xf0) | (source & 0x0f);
+  return source;
+}
+
+void SuperFX::plot(uint8_t x, uint8_t y) {
+  uint8_t color = regs.colr;
+
+  if(regs.por.dither && regs.scmr.md != 3) {
+    if((x ^ y) & 1) color >>= 4;
+    color &= 0x0f;
+  }
+
+  if(!regs.por.transparent) {
+    if(regs.scmr.md == 3) {
+      if(regs.por.freezehigh) {
+        if((color & 0x0f) == 0) return;
+      } else {
+        if(color == 0) return;
+      }
+    } else {
+      if((color & 0x0f) == 0) return;
+    }
+  }
+
+  uint16_t offset = (y << 5) + (x >> 3);
+  if(offset != pixelcache[0].offset) {
+    pixelcache_flush(pixelcache[1]);
+    pixelcache[1] = pixelcache[0];
+    pixelcache[0].bitpend = 0x00;
+    pixelcache[0].offset = offset;
+  }
+
+  x = (x & 7) ^ 7;
+  pixelcache[0].data[x] = color;
+  pixelcache[0].bitpend |= 1 << x;
+  if(pixelcache[0].bitpend == 0xff) {
+    pixelcache_flush(pixelcache[1]);
+    pixelcache[1] = pixelcache[0];
+    pixelcache[0].bitpend = 0x00;
+  }
+}
+
+uint8_t SuperFX::rpix(uint8_t x, uint8_t y) {
+  pixelcache_flush(pixelcache[1]);
+  pixelcache_flush(pixelcache[0]);
+
+  unsigned cn;  //character number
+  switch(regs.por.obj ? 3 : regs.scmr.ht) {
+    case 0: cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 3); break;
+    case 1: cn = ((x & 0xf8) << 1) + ((x & 0xf8) >> 1) + ((y & 0xf8) >> 3); break;
+    case 2: cn = ((x & 0xf8) << 1) + ((x & 0xf8) << 0) + ((y & 0xf8) >> 3); break;
+    case 3: cn = ((y & 0x80) << 2) + ((x & 0x80) << 1) + ((y & 0x78) << 1) + ((x & 0x78) >> 3); break;
+  }
+  unsigned bpp = 2 << (regs.scmr.md - (regs.scmr.md >> 1));  // = [regs.scmr.md]{ 2, 4, 4, 8 };
+  unsigned addr = 0x700000 + (cn * (bpp << 3)) + (regs.scbr << 10) + ((y & 0x07) * 2);
+  uint8_t data = 0x00;
+  x = (x & 7) ^ 7;
+
+  for(unsigned n = 0; n < bpp; n++) {
+    unsigned byte = ((n >> 1) << 4) + (n & 1);  // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
+    add_clocks(memory_access_speed);
+    data |= ((superfxbus.read(addr + byte) >> x) & 1) << n;
+  }
+
+  return data;
+}
+
+void SuperFX::pixelcache_flush(pixelcache_t &cache) {
+  if(cache.bitpend == 0x00) return;
+
+  uint8_t x = cache.offset << 3;
+  uint8_t y = cache.offset >> 5;
+
+  unsigned cn;  //character number
+  switch(regs.por.obj ? 3 : regs.scmr.ht) {
+    case 0: cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 3); break;
+    case 1: cn = ((x & 0xf8) << 1) + ((x & 0xf8) >> 1) + ((y & 0xf8) >> 3); break;
+    case 2: cn = ((x & 0xf8) << 1) + ((x & 0xf8) << 0) + ((y & 0xf8) >> 3); break;
+    case 3: cn = ((y & 0x80) << 2) + ((x & 0x80) << 1) + ((y & 0x78) << 1) + ((x & 0x78) >> 3); break;
+  }
+  unsigned bpp = 2 << (regs.scmr.md - (regs.scmr.md >> 1));  // = [regs.scmr.md]{ 2, 4, 4, 8 };
+  unsigned addr = 0x700000 + (cn * (bpp << 3)) + (regs.scbr << 10) + ((y & 0x07) * 2);
+
+  for(unsigned n = 0; n < bpp; n++) {
+    unsigned byte = ((n >> 1) << 4) + (n & 1);  // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
+    uint8_t data = 0x00;
+    for(unsigned x = 0; x < 8; x++) data |= ((cache.data[x] >> n) & 1) << x;
+    if(cache.bitpend != 0xff) {
+      add_clocks(memory_access_speed);
+      data &= cache.bitpend;
+      data |= superfxbus.read(addr + byte) & ~cache.bitpend;
+    }
+    add_clocks(memory_access_speed);
+    superfxbus.write(addr + byte, data);
+  }
+
+  cache.bitpend = 0x00;
+}
+
+#endif

src/chip/superfx/core/core.hpp

@@ -0,0 +1,93 @@
+#include "registers.hpp"
+
+void exec_opcode();
+uint8_t color(uint8_t source);
+void plot(uint8_t x, uint8_t y);
+uint8_t rpix(uint8_t x, uint8_t y);
+void pixelcache_flush(pixelcache_t &cache);
+
+void (SuperFX::*opcode_table[1024])();
+void initialize_opcode_table();
+
+//opcodes.cpp
+template<int> void op_adc_i();
+template<int> void op_adc_r();
+template<int> void op_add_i();
+template<int> void op_add_r();
+void op_alt1();
+void op_alt2();
+void op_alt3();
+template<int> void op_and_i();
+template<int> void op_and_r();
+void op_asr();
+void op_bge();
+void op_bcc();
+void op_bcs();
+void op_beq();
+template<int> void op_bic_i();
+template<int> void op_bic_r();
+void op_blt();
+void op_bmi();
+void op_bne();
+void op_bpl();
+void op_bra();
+void op_bvc();
+void op_bvs();
+void op_cache();
+void op_cmode();
+template<int> void op_cmp_r();
+void op_color();
+template<int> void op_dec_r();
+void op_div2();
+void op_fmult();
+template<int> void op_from_r();
+void op_getb();
+void op_getbl();
+void op_getbh();
+void op_getbs();
+void op_getc();
+void op_hib();
+template<int> void op_ibt_r();
+template<int> void op_inc_r();
+template<int> void op_iwt_r();
+template<int> void op_jmp_r();
+template<int> void op_ldb_ir();
+template<int> void op_ldw_ir();
+template<int> void op_link();
+template<int> void op_ljmp_r();
+template<int> void op_lm_r();
+template<int> void op_lms_r();
+void op_lmult();
+void op_lob();
+void op_loop();
+void op_lsr();
+void op_merge();
+template<int> void op_mult_i();
+template<int> void op_mult_r();
+void op_nop();
+void op_not();
+template<int> void op_or_i();
+template<int> void op_or_r();
+void op_plot();
+void op_ramb();
+void op_rol();
+void op_romb();
+void op_ror();
+void op_rpix();
+template<int> void op_sbc_r();
+void op_sbk();
+void op_sex();
+template<int> void op_sm_r();
+template<int> void op_sms_r();
+template<int> void op_stb_ir();
+void op_stop();
+template<int> void op_stw_ir();
+template<int> void op_sub_i();
+template<int> void op_sub_r();
+void op_swap();
+template<int> void op_to_r();
+template<int> void op_umult_i();
+template<int> void op_umult_r();
+template<int> void op_with_r();
+template<int> void op_xor_i();
+template<int> void op_xor_r();

src/chip/superfx/core/opcode_table.cpp

@@ -0,0 +1,270 @@
+#ifdef SUPERFX_CPP
+
+void SuperFX::initialize_opcode_table() {
+  #define op4(id, name) \
+    op(id+ 0, name< 1>) op(id+ 1, name< 2>) op(id+ 2, name< 3>) op(id+ 3, name< 4>)
+
+  #define op6(id, name) \
+    op(id+ 0, name< 8>) op(id+ 1, name< 9>) op(id+ 2, name<10>) op(id+ 3, name<11>) \
+    op(id+ 4, name<12>) op(id+ 5, name<13>)
+
+  #define op12(id, name) \
+    op(id+ 0, name< 0>) op(id+ 1, name< 1>) op(id+ 2, name< 2>) op(id+ 3, name< 3>) \
+    op(id+ 4, name< 4>) op(id+ 5, name< 5>) op(id+ 6, name< 6>) op(id+ 7, name< 7>) \
+    op(id+ 8, name< 8>) op(id+ 9, name< 9>) op(id+10, name<10>) op(id+11, name<11>)
+
+  #define op15l(id, name) \
+    op(id+ 0, name< 0>) op(id+ 1, name< 1>) op(id+ 2, name< 2>) op(id+ 3, name< 3>) \
+    op(id+ 4, name< 4>) op(id+ 5, name< 5>) op(id+ 6, name< 6>) op(id+ 7, name< 7>) \
+    op(id+ 8, name< 8>) op(id+ 9, name< 9>) op(id+10, name<10>) op(id+11, name<11>) \
+    op(id+12, name<12>) op(id+13, name<13>) op(id+14, name<14>)
+
+  #define op15h(id, name) \
+    op(id+ 0, name< 1>) op(id+ 1, name< 2>) op(id+ 2, name< 3>) op(id+ 3, name< 4>) \
+    op(id+ 4, name< 5>) op(id+ 5, name< 6>) op(id+ 6, name< 7>) op(id+ 7, name< 8>) \
+    op(id+ 8, name< 9>) op(id+ 9, name<10>) op(id+10, name<11>) op(id+11, name<12>) \
+    op(id+12, name<13>) op(id+13, name<14>) op(id+14, name<15>)
+
+  #define op16(id, name) \
+    op(id+ 0, name< 0>) op(id+ 1, name< 1>) op(id+ 2, name< 2>) op(id+ 3, name< 3>) \
+    op(id+ 4, name< 4>) op(id+ 5, name< 5>) op(id+ 6, name< 6>) op(id+ 7, name< 7>) \
+    op(id+ 8, name< 8>) op(id+ 9, name< 9>) op(id+10, name<10>) op(id+11, name<11>) \
+    op(id+12, name<12>) op(id+13, name<13>) op(id+14, name<14>) op(id+15, name<15>)
+
+  //======
+  // ALT0
+  //======
+
+  #define op(id, name) opcode_table[  0 + id] = &SuperFX::op_##name;
+  op   (0x00, stop)
+  op   (0x01, nop)
+  op   (0x02, cache)
+  op   (0x03, lsr)
+  op   (0x04, rol)
+  op   (0x05, bra)
+  op   (0x06, blt)
+  op   (0x07, bge)
+  op   (0x08, bne)
+  op   (0x09, beq)
+  op   (0x0a, bpl)
+  op   (0x0b, bmi)
+  op   (0x0c, bcc)
+  op   (0x0d, bcs)
+  op   (0x0e, bvc)
+  op   (0x0f, bvs)
+  op16 (0x10, to_r)
+  op16 (0x20, with_r)
+  op12 (0x30, stw_ir)
+  op   (0x3c, loop)
+  op   (0x3d, alt1)
+  op   (0x3e, alt2)
+  op   (0x3f, alt3)
+  op12 (0x40, ldw_ir)
+  op   (0x4c, plot)
+  op   (0x4d, swap)
+  op   (0x4e, color)
+  op   (0x4f, not)
+  op16 (0x50, add_r)
+  op16 (0x60, sub_r)
+  op   (0x70, merge)
+  op15h(0x71, and_r)
+  op16 (0x80, mult_r)
+  op   (0x90, sbk)
+  op4  (0x91, link)
+  op   (0x95, sex)
+  op   (0x96, asr)
+  op   (0x97, ror)
+  op6  (0x98, jmp_r)
+  op   (0x9e, lob)
+  op   (0x9f, fmult)
+  op16 (0xa0, ibt_r)
+  op16 (0xb0, from_r)
+  op   (0xc0, hib)
+  op15h(0xc1, or_r)
+  op15l(0xd0, inc_r)
+  op   (0xdf, getc)
+  op15l(0xe0, dec_r)
+  op   (0xef, getb)
+  op16 (0xf0, iwt_r)
+  #undef op
+
+  //======
+  // ALT1
+  //======
+
+  #define op(id, name) opcode_table[256 + id] = &SuperFX::op_##name;
+  op   (0x00, stop)
+  op   (0x01, nop)
+  op   (0x02, cache)
+  op   (0x03, lsr)
+  op   (0x04, rol)
+  op   (0x05, bra)
+  op   (0x06, blt)
+  op   (0x07, bge)
+  op   (0x08, bne)
+  op   (0x09, beq)
+  op   (0x0a, bpl)
+  op   (0x0b, bmi)
+  op   (0x0c, bcc)
+  op   (0x0d, bcs)
+  op   (0x0e, bvc)
+  op   (0x0f, bvs)
+  op16 (0x10, to_r)
+  op16 (0x20, with_r)
+  op12 (0x30, stb_ir)
+  op   (0x3c, loop)
+  op   (0x3d, alt1)
+  op   (0x3e, alt2)
+  op   (0x3f, alt3)
+  op12 (0x40, ldb_ir)
+  op   (0x4c, rpix)
+  op   (0x4d, swap)
+  op   (0x4e, cmode)
+  op   (0x4f, not)
+  op16 (0x50, adc_r)
+  op16 (0x60, sbc_r)
+  op   (0x70, merge)
+  op15h(0x71, bic_r)
+  op16 (0x80, umult_r)
+  op   (0x90, sbk)
+  op4  (0x91, link)
+  op   (0x95, sex)
+  op   (0x96, div2)
+  op   (0x97, ror)
+  op6  (0x98, ljmp_r)
+  op   (0x9e, lob)
+  op   (0x9f, lmult)
+  op16 (0xa0, lms_r)
+  op16 (0xb0, from_r)
+  op   (0xc0, hib)
+  op15h(0xc1, xor_r)
+  op15l(0xd0, inc_r)
+  op   (0xdf, getc)
+  op15l(0xe0, dec_r)
+  op   (0xef, getbh)
+  op16 (0xf0, lm_r)
+  #undef op
+
+  //======
+  // ALT2
+  //======
+
+  #define op(id, name) opcode_table[512 + id] = &SuperFX::op_##name;
+  op   (0x00, stop)
+  op   (0x01, nop)
+  op   (0x02, cache)
+  op   (0x03, lsr)
+  op   (0x04, rol)
+  op   (0x05, bra)
+  op   (0x06, blt)
+  op   (0x07, bge)
+  op   (0x08, bne)
+  op   (0x09, beq)
+  op   (0x0a, bpl)
+  op   (0x0b, bmi)
+  op   (0x0c, bcc)
+  op   (0x0d, bcs)
+  op   (0x0e, bvc)
+  op   (0x0f, bvs)
+  op16 (0x10, to_r)
+  op16 (0x20, with_r)
+  op12 (0x30, stw_ir)
+  op   (0x3c, loop)
+  op   (0x3d, alt1)
+  op   (0x3e, alt2)
+  op   (0x3f, alt3)
+  op12 (0x40, ldw_ir)
+  op   (0x4c, plot)
+  op   (0x4d, swap)
+  op   (0x4e, color)
+  op   (0x4f, not)
+  op16 (0x50, add_i)
+  op16 (0x60, sub_i)
+  op   (0x70, merge)
+  op15h(0x71, and_i)
+  op16 (0x80, mult_i)
+  op   (0x90, sbk)
+  op4  (0x91, link)
+  op   (0x95, sex)
+  op   (0x96, asr)
+  op   (0x97, ror)
+  op6  (0x98, jmp_r)
+  op   (0x9e, lob)
+  op   (0x9f, fmult)
+  op16 (0xa0, sms_r)
+  op16 (0xb0, from_r)
+  op   (0xc0, hib)
+  op15h(0xc1, or_i)
+  op15l(0xd0, inc_r)
+  op   (0xdf, ramb)
+  op15l(0xe0, dec_r)
+  op   (0xef, getbl)
+  op16 (0xf0, sm_r)
+  #undef op
+
+  //======
+  // ALT3
+  //======
+
+  #define op(id, name) opcode_table[768 + id] = &SuperFX::op_##name;
+  op   (0x00, stop)
+  op   (0x01, nop)
+  op   (0x02, cache)
+  op   (0x03, lsr)
+  op   (0x04, rol)
+  op   (0x05, bra)
+  op   (0x06, blt)
+  op   (0x07, bge)
+  op   (0x08, bne)
+  op   (0x09, beq)
+  op   (0x0a, bpl)
+  op   (0x0b, bmi)
+  op   (0x0c, bcc)
+  op   (0x0d, bcs)
+  op   (0x0e, bvc)
+  op   (0x0f, bvs)
+  op16 (0x10, to_r)
+  op16 (0x20, with_r)
+  op12 (0x30, stb_ir)
+  op   (0x3c, loop)
+  op   (0x3d, alt1)
+  op   (0x3e, alt2)
+  op   (0x3f, alt3)
+  op12 (0x40, ldb_ir)
+  op   (0x4c, rpix)
+  op   (0x4d, swap)
+  op   (0x4e, cmode)
+  op   (0x4f, not)
+  op16 (0x50, adc_i)
+  op16 (0x60, cmp_r)
+  op   (0x70, merge)
+  op15h(0x71, bic_i)
+  op16 (0x80, umult_i)
+  op   (0x90, sbk)
+  op4  (0x91, link)
+  op   (0x95, sex)
+  op   (0x96, div2)
+  op   (0x97, ror)
+  op6  (0x98, ljmp_r)
+  op   (0x9e, lob)
+  op   (0x9f, lmult)
+  op16 (0xa0, lms_r)
+  op16 (0xb0, from_r)
+  op   (0xc0, hib)
+  op15h(0xc1, xor_i)
+  op15l(0xd0, inc_r)
+  op   (0xdf, romb)
+  op15l(0xe0, dec_r)
+  op   (0xef, getbs)
+  op16 (0xf0, lm_r)
+  #undef op
+
+  #undef op4
+  #undef op6
+  #undef op12
+  #undef op15l
+  #undef op15h
+  #undef op16
+}
+
+#endif

src/chip/superfx/core/opcodes.cpp

@@ -0,0 +1,661 @@
+#ifdef SUPERFX_CPP
+
+//$00 stop
+void SuperFX::op_stop() {
+  if(regs.cfgr.irq == 0) {
+    regs.sfr.irq = 1;
+    cpu.regs.irq = 1;
+  }
+
+  regs.sfr.g = 0;
+  regs.pipeline = 0x01;
+  regs.reset();
+}
+
+//$01 nop
+void SuperFX::op_nop() {
+  regs.reset();
+}
+
+//$02 cache
+void SuperFX::op_cache() {
+  if(regs.cbr != (regs.r[15] & 0xfff0)) {
+    regs.cbr = regs.r[15] & 0xfff0;
+    cache_flush();
+  }
+  regs.reset();
+}
+
+//$03 lsr
+void SuperFX::op_lsr() {
+  regs.sfr.cy = (regs.sr() & 1);
+  regs.dr() = regs.sr() >> 1;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$04 rol
+void SuperFX::op_rol() {
+  bool carry = (regs.sr() & 0x8000);
+  regs.dr() = (regs.sr() << 1) | regs.sfr.cy;
+  regs.sfr.s  = (regs.dr() & 0x8000);
+  regs.sfr.cy = carry;
+  regs.sfr.z  = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$05 bra e
+void SuperFX::op_bra() {
+  regs.r[15] += (int8_t)pipe();
+}
+
+//$06 blt e
+void SuperFX::op_blt() {
+  int e = (int8_t)pipe();
+  if((regs.sfr.s ^ regs.sfr.ov) == 0) regs.r[15] += e;
+}
+
+//$07 bge e
+void SuperFX::op_bge() {
+  int e = (int8_t)pipe();
+  if((regs.sfr.s ^ regs.sfr.ov) == 1) regs.r[15] += e;
+}
+
+//$08 bne e
+void SuperFX::op_bne() {
+  int e = (int8_t)pipe();
+  if(regs.sfr.z == 0) regs.r[15] += e;
+}
+
+//$09 beq e
+void SuperFX::op_beq() {
+  int e = (int8_t)pipe();
+  if(regs.sfr.z == 1) regs.r[15] += e;
+}
+
+//$0a bpl e
+void SuperFX::op_bpl() {
+  int e = (int8_t)pipe();
+  if(regs.sfr.s == 0) regs.r[15] += e;
+}
+
+//$0b bmi e
+void SuperFX::op_bmi() {
+  int e = (int8_t)pipe();
+  if(regs.sfr.s == 1) regs.r[15] += e;
+}
+
+//$0c bcc e
+void SuperFX::op_bcc() {
+  int e = (int8_t)pipe();
+  if(regs.sfr.cy == 0) regs.r[15] += e;
+}
+
+//$0d bcs e
+void SuperFX::op_bcs() {
+  int e = (int8_t)pipe();
+  if(regs.sfr.cy == 1) regs.r[15] += e;
+}
+
+//$0e bvc e
+void SuperFX::op_bvc() {
+  int e = (int8_t)pipe();
+  if(regs.sfr.ov == 0) regs.r[15] += e;
+}
+
+//$0f bvs e
+void SuperFX::op_bvs() {
+  int e = (int8_t)pipe();
+  if(regs.sfr.ov == 1) regs.r[15] += e;
+}
+
+//$10-1f(b0): to rN
+//$10-1f(b1): move rN
+template<int n> void SuperFX::op_to_r() {
+  if(regs.sfr.b == 0) {
+    regs.dreg = &regs.r[n];
+  } else {
+    regs.r[n] = regs.sr();
+    regs.reset();
+  }
+}
+
+//$20-2f: with rN
+template<int n> void SuperFX::op_with_r() {
+  regs.sreg = &regs.r[n];
+  regs.dreg = &regs.r[n];
+  regs.sfr.b = 1;
+}
+
+//$30-3b(alt0): stw (rN)
+template<int n> void SuperFX::op_stw_ir() {
+  regs.ramaddr = regs.r[n];
+  rambuffer_write(regs.ramaddr ^ 0, regs.sr() >> 0);
+  rambuffer_write(regs.ramaddr ^ 1, regs.sr() >> 8);
+  regs.reset();
+}
+
+//$30-3b(alt1): stb (rN)
+template<int n> void SuperFX::op_stb_ir() {
+  regs.ramaddr = regs.r[n];
+  rambuffer_write(regs.ramaddr, regs.sr());
+  regs.reset();
+}
+
+//$3c loop
+void SuperFX::op_loop() {
+  regs.r[12]--;
+  regs.sfr.s = (regs.r[12] & 0x8000);
+  regs.sfr.z = (regs.r[12] == 0);
+  if(!regs.sfr.z) regs.r[15] = regs.r[13];
+  regs.reset();
+}
+
+//$3d alt1
+void SuperFX::op_alt1() {
+  regs.sfr.b = 0;
+  regs.sfr.alt1 = 1;
+}
+
+//$3e alt2
+void SuperFX::op_alt2() {
+  regs.sfr.b = 0;
+  regs.sfr.alt2 = 1;
+}
+
+//$3f alt3
+void SuperFX::op_alt3() {
+  regs.sfr.b = 0;
+  regs.sfr.alt1 = 1;
+  regs.sfr.alt2 = 1;
+}
+
+//$40-4b(alt0): ldw (rN)
+template<int n> void SuperFX::op_ldw_ir() {
+  regs.ramaddr = regs.r[n];
+  uint16_t data;
+  data  = rambuffer_read(regs.ramaddr ^ 0) << 0;
+  data |= rambuffer_read(regs.ramaddr ^ 1) << 8;
+  regs.dr() = data;
+  regs.reset();
+}
+
+//$40-4b(alt1): ldb (rN)
+template<int n> void SuperFX::op_ldb_ir() {
+  regs.ramaddr = regs.r[n];
+  regs.dr() = rambuffer_read(regs.ramaddr);
+  regs.reset();
+}
+
+//$4c(alt0): plot
+void SuperFX::op_plot() {
+  plot(regs.r[1], regs.r[2]);
+  regs.r[1]++;
+  regs.reset();
+}
+
+//$4c(alt1): rpix
+void SuperFX::op_rpix() {
+  regs.dr() = rpix(regs.r[1], regs.r[2]);
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$4d: swap
+void SuperFX::op_swap() {
+  regs.dr() = (regs.sr() >> 8) | (regs.sr() << 8);
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$4e(alt0): color
+void SuperFX::op_color() {
+  regs.colr = color(regs.sr());
+  regs.reset();
+}
+
+//$4e(alt1): cmode
+void SuperFX::op_cmode() {
+  regs.por = regs.sr();
+  regs.reset();
+}
+
+//$4f: not
+void SuperFX::op_not() {
+  regs.dr() = ~regs.sr();
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$50-5f(alt0): add rN
+template<int n> void SuperFX::op_add_r() {
+  int r = regs.sr() + regs.r[n];
+  regs.sfr.ov = ~(regs.sr() ^ regs.r[n]) & (regs.r[n] ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0x10000);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$50-5f(alt1): adc rN
+template<int n> void SuperFX::op_adc_r() {
+  int r = regs.sr() + regs.r[n] + regs.sfr.cy;
+  regs.sfr.ov = ~(regs.sr() ^ regs.r[n]) & (regs.r[n] ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0x10000);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$50-5f(alt2): add #N
+template<int n> void SuperFX::op_add_i() {
+  int r = regs.sr() + n;
+  regs.sfr.ov = ~(regs.sr() ^ n) & (n ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0x10000);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$50-5f(alt3): adc #N
+template<int n> void SuperFX::op_adc_i() {
+  int r = regs.sr() + n + regs.sfr.cy;
+  regs.sfr.ov = ~(regs.sr() ^ n) & (n ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0x10000);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$60-6f(alt0): sub rN
+template<int n> void SuperFX::op_sub_r() {
+  int r = regs.sr() - regs.r[n];
+  regs.sfr.ov = (regs.sr() ^ regs.r[n]) & (regs.sr() ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$60-6f(alt1): sbc rN
+template<int n> void SuperFX::op_sbc_r() {
+  int r = regs.sr() - regs.r[n] - !regs.sfr.cy;
+  regs.sfr.ov = (regs.sr() ^ regs.r[n]) & (regs.sr() ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$60-6f(alt2): sub #N
+template<int n> void SuperFX::op_sub_i() {
+  int r = regs.sr() - n;
+  regs.sfr.ov = (regs.sr() ^ n) & (regs.sr() ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.dr() = r;
+  regs.reset();
+}
+
+//$60-6f(alt3): cmp rN
+template<int n> void SuperFX::op_cmp_r() {
+  int r = regs.sr() - regs.r[n];
+  regs.sfr.ov = (regs.sr() ^ regs.r[n]) & (regs.sr() ^ r) & 0x8000;
+  regs.sfr.s  = (r & 0x8000);
+  regs.sfr.cy = (r >= 0);
+  regs.sfr.z  = ((uint16_t)r == 0);
+  regs.reset();
+}
+
+//$70: merge
+void SuperFX::op_merge() {
+  regs.dr() = (regs.r[7] & 0xff00) | (regs.r[8] >> 8);
+  regs.sfr.ov = (regs.dr() & 0xc0c0);
+  regs.sfr.s  = (regs.dr() & 0x8080);
+  regs.sfr.cy = (regs.dr() & 0xe0e0);
+  regs.sfr.z  = (regs.dr() & 0xf0f0);
+  regs.reset();
+}
+
+//$71-7f(alt0): and rN
+template<int n> void SuperFX::op_and_r() {
+  regs.dr() = regs.sr() & regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$71-7f(alt1): bic rN
+template<int n> void SuperFX::op_bic_r() {
+  regs.dr() = regs.sr() & ~regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$71-7f(alt2): and #N
+template<int n> void SuperFX::op_and_i() {
+  regs.dr() = regs.sr() & n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$71-7f(alt3): bic #N
+template<int n> void SuperFX::op_bic_i() {
+  regs.dr() = regs.sr() & ~n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$80-8f(alt0): mult rN
+template<int n> void SuperFX::op_mult_r() {
+  regs.dr() = (int8_t)regs.sr() * (int8_t)regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+  if(!regs.cfgr.ms0) add_clocks(2);
+}
+
+//$80-8f(alt1): umult rN
+template<int n> void SuperFX::op_umult_r() {
+  regs.dr() = (uint8_t)regs.sr() * (uint8_t)regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+  if(!regs.cfgr.ms0) add_clocks(2);
+}
+
+//$80-8f(alt2): mult #N
+template<int n> void SuperFX::op_mult_i() {
+  regs.dr() = (int8_t)regs.sr() * (int8_t)n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+  if(!regs.cfgr.ms0) add_clocks(2);
+}
+
+//$80-8f(alt3): umult #N
+template<int n> void SuperFX::op_umult_i() {
+  regs.dr() = (uint8_t)regs.sr() * (uint8_t)n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+  if(!regs.cfgr.ms0) add_clocks(2);
+}
+
+//$90: sbk
+void SuperFX::op_sbk() {
+  rambuffer_write(regs.ramaddr ^ 0, regs.sr() >> 0);
+  rambuffer_write(regs.ramaddr ^ 1, regs.sr() >> 8);
+  regs.reset();
+}
+
+//$91-94: link #N
+template<int n> void SuperFX::op_link() {
+  regs.r[11] = regs.r[15] + n;
+  regs.reset();
+}
+
+//$95: sex
+void SuperFX::op_sex() {
+  regs.dr() = (int8_t)regs.sr();
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$96(alt0): asr
+void SuperFX::op_asr() {
+  regs.sfr.cy = (regs.sr() & 1);
+  regs.dr() = (int16_t)regs.sr() >> 1;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$96(alt1): div2
+void SuperFX::op_div2() {
+  regs.sfr.cy = (regs.sr() & 1);
+  regs.dr() = ((int16_t)regs.sr() >> 1) + ((regs.sr() + 1) >> 16);
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$97: ror
+void SuperFX::op_ror() {
+  bool carry = (regs.sr() & 1);
+  regs.dr() = (regs.sfr.cy << 15) | (regs.sr() >> 1);
+  regs.sfr.s  = (regs.dr() & 0x8000);
+  regs.sfr.cy = carry;
+  regs.sfr.z  = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$98-9d(alt0): jmp rN
+template<int n> void SuperFX::op_jmp_r() {
+  regs.r[15] = regs.r[n];
+  regs.reset();
+}
+
+//$98-9d(alt1): ljmp rN
+template<int n> void SuperFX::op_ljmp_r() {
+  regs.pbr = regs.r[n];
+  regs.r[15] = regs.sr();
+  regs.cbr = regs.r[15] & 0xfff0;
+  cache_flush();
+  regs.reset();
+}
+
+//$9e: lob
+void SuperFX::op_lob() {
+  regs.dr() = regs.sr() & 0xff;
+  regs.sfr.s = (regs.dr() & 0x80);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$9f(alt0): fmult
+void SuperFX::op_fmult() {
+  uint32_t result = (int16_t)regs.sr() * (int16_t)regs.r[6];
+  regs.dr() = result >> 16;
+  regs.sfr.s  = (regs.dr() & 0x8000);
+  regs.sfr.cy = (result & 0x8000);
+  regs.sfr.z  = (regs.dr() == 0);
+  regs.reset();
+  add_clocks(4 + (regs.cfgr.ms0 << 2));
+}
+
+//$9f(alt1): lmult
+void SuperFX::op_lmult() {
+  uint32_t result = (int16_t)regs.sr() * (int16_t)regs.r[6];
+  regs.r[4] = result;
+  regs.dr() = result >> 16;
+  regs.sfr.s  = (regs.dr() & 0x8000);
+  regs.sfr.cy = (result & 0x8000);
+  regs.sfr.z  = (regs.dr() == 0);
+  regs.reset();
+  add_clocks(4 + (regs.cfgr.ms0 << 2));
+}
+
+//$a0-af(alt0): ibt rN,#pp
+template<int n> void SuperFX::op_ibt_r() {
+  regs.r[n] = (int8_t)pipe();
+  regs.reset();
+}
+
+//$a0-af(alt1): lms rN,(yy)
+template<int n> void SuperFX::op_lms_r() {
+  regs.ramaddr = pipe() << 1;
+  uint16_t data;
+  data  = rambuffer_read(regs.ramaddr ^ 0) << 0;
+  data |= rambuffer_read(regs.ramaddr ^ 1) << 8;
+  regs.r[n] = data;
+  regs.reset();
+}
+
+//$a0-af(alt2): sms (yy),rN
+template<int n> void SuperFX::op_sms_r() {
+  regs.ramaddr = pipe() << 1;
+  rambuffer_write(regs.ramaddr ^ 0, regs.r[n] >> 0);
+  rambuffer_write(regs.ramaddr ^ 1, regs.r[n] >> 8);
+  regs.reset();
+}
+
+//$b0-bf(b0): from rN
+//$b0-bf(b1): moves rN
+template<int n> void SuperFX::op_from_r() {
+  if(regs.sfr.b == 0) {
+    regs.sreg = &regs.r[n];
+  } else {
+    regs.dr() = regs.r[n];
+    regs.sfr.ov = (regs.dr() & 0x80);
+    regs.sfr.s  = (regs.dr() & 0x8000);
+    regs.sfr.z  = (regs.dr() == 0);
+    regs.reset();
+  }
+}
+
+//$c0: hib
+void SuperFX::op_hib() {
+  regs.dr() = regs.sr() >> 8;
+  regs.sfr.s = (regs.dr() & 0x80);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$c1-cf(alt0): or rN
+template<int n> void SuperFX::op_or_r() {
+  regs.dr() = regs.sr() | regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$c1-cf(alt1): xor rN
+template<int n> void SuperFX::op_xor_r() {
+  regs.dr() = regs.sr() ^ regs.r[n];
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$c1-cf(alt2): or #N
+template<int n> void SuperFX::op_or_i() {
+  regs.dr() = regs.sr() | n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$c1-cf(alt3): xor #N
+template<int n> void SuperFX::op_xor_i() {
+  regs.dr() = regs.sr() ^ n;
+  regs.sfr.s = (regs.dr() & 0x8000);
+  regs.sfr.z = (regs.dr() == 0);
+  regs.reset();
+}
+
+//$d0-de: inc rN
+template<int n> void SuperFX::op_inc_r() {
+  regs.r[n]++;
+  regs.sfr.s = (regs.r[n] & 0x8000);
+  regs.sfr.z = (regs.r[n] == 0);
+  regs.reset();
+}
+
+//$df(alt0): getc
+void SuperFX::op_getc() {
+  regs.colr = color(rombuffer_read());
+  regs.reset();
+}
+
+//$df(alt2): ramb
+void SuperFX::op_ramb() {
+  rambuffer_sync();
+  regs.rambr = regs.sr();
+  regs.reset();
+}
+
+//$df(alt3): romb
+void SuperFX::op_romb() {
+  rombuffer_sync();
+  regs.rombr = regs.sr();
+  regs.reset();
+}
+
+//$e0-ee: dec rN
+template<int n> void SuperFX::op_dec_r() {
+  regs.r[n]--;
+  regs.sfr.s = (regs.r[n] & 0x8000);
+  regs.sfr.z = (regs.r[n] == 0);
+  regs.reset();
+}
+
+//$ef(alt0): getb
+void SuperFX::op_getb() {
+  regs.dr() = rombuffer_read();
+  regs.reset();
+}
+
+//$ef(alt1): getbh
+void SuperFX::op_getbh() {
+  regs.dr() = (rombuffer_read() << 8) | (regs.sr() & 0x00ff);
+  regs.reset();
+}
+
+//$ef(alt2): getbl
+void SuperFX::op_getbl() {
+  regs.dr() = (regs.sr() & 0xff00) | (rombuffer_read() << 0);
+  regs.reset();
+}
+
+//$ef(alt3): getbs
+void SuperFX::op_getbs() {
+  regs.dr() = (int8_t)rombuffer_read();
+  regs.reset();
+}
+
+//$f0-ff(alt0): iwt rN,#xx
+template<int n> void SuperFX::op_iwt_r() {
+  uint16_t data;
+  data  = pipe() << 0;
+  data |= pipe() << 8;
+  regs.r[n] = data;
+  regs.reset();
+}
+
+//$f0-ff(alt1): lm rN,(xx)
+template<int n> void SuperFX::op_lm_r() {
+  regs.ramaddr  = pipe() << 0;
+  regs.ramaddr |= pipe() << 8;
+  uint16_t data;
+  data  = rambuffer_read(regs.ramaddr ^ 0) << 0;
+  data |= rambuffer_read(regs.ramaddr ^ 1) << 8;
+  regs.r[n] = data;
+  regs.reset();
+}
+
+//$f0-ff(alt2): sm (xx),rN
+template<int n> void SuperFX::op_sm_r() {
+  regs.ramaddr  = pipe() << 0;
+  regs.ramaddr |= pipe() << 8;
+  rambuffer_write(regs.ramaddr ^ 0, regs.r[n] >> 0);
+  rambuffer_write(regs.ramaddr ^ 1, regs.r[n] >> 8);
+  regs.reset();
+}
+
+#endif

src/chip/superfx/core/registers.hpp

@@ -0,0 +1,177 @@
+
+
+//accepts a callback binding so r14 writes can trigger ROM buffering transparently
+struct reg16_t : noncopyable {
+  uint16_t data;
+  function<void (uint16_t)> on_modify;
+
+  inline operator unsigned() const { return data; }
+  inline uint16_t assign(uint16_t i) {
+    if(on_modify) on_modify(i);
+    else data = i;
+    return data;
+  }
+
+  inline unsigned operator++() { return assign(data + 1); }
+  inline unsigned operator--() { return assign(data - 1); }
+  inline unsigned operator++(int) { unsigned r = data; assign(data + 1); return r; }
+  inline unsigned operator--(int) { unsigned r = data; assign(data - 1); return r; }
+  inline unsigned operator   = (unsigned i) { return assign(i); }
+  inline unsigned operator  |= (unsigned i) { return assign(data | i); }
+  inline unsigned operator  ^= (unsigned i) { return assign(data ^ i); }
+  inline unsigned operator  &= (unsigned i) { return assign(data & i); }
+  inline unsigned operator <<= (unsigned i) { return assign(data << i); }
+  inline unsigned operator >>= (unsigned i) { return assign(data >> i); }
+  inline unsigned operator  += (unsigned i) { return assign(data + i); }
+  inline unsigned operator  -= (unsigned i) { return assign(data - i); }
+  inline unsigned operator  *= (unsigned i) { return assign(data * i); }
+  inline unsigned operator  /= (unsigned i) { return assign(data / i); }
+  inline unsigned operator  %= (unsigned i) { return assign(data % i); }
+
+  inline unsigned operator   = (const reg16_t& i) { return assign(i); }
+
+  reg16_t() : data(0) {}
+};
+
+struct sfr_t {
+  bool irq;   //interrupt flag
+  bool b;     //WITH flag
+  bool ih;    //immediate higher 8-bit flag
+  bool il;    //immediate lower 8-bit flag
+  bool alt2;  //ALT2 mode
+  bool alt1;  //ALT2 instruction mode
+  bool r;     //ROM r14 read flag
+  bool g;     //GO flag
+  bool ov;    //overflow flag
+  bool s;     //sign flag
+  bool cy;    //carry flag
+  bool z;     //zero flag
+
+  operator uint16_t() const {
+    return (irq << 15) | (b << 12) | (ih << 11) | (il << 10) | (alt2 << 9) | (alt1 << 8)
+         | (r << 6) | (g << 5) | (ov << 4) | (s << 3) | (cy << 2) | (z << 1);
+  }
+
+  sfr_t& operator=(uint16_t data) {
+    irq  = data & 0x8000;
+    b    = data & 0x1000;
+    ih   = data & 0x0800;
+    il   = data & 0x0400;
+    alt2 = data & 0x0200;
+    alt1 = data & 0x0100;
+    r    = data & 0x0040;
+    g    = data & 0x0020;
+    ov   = data & 0x0010;
+    s    = data & 0x0008;
+    cy   = data & 0x0004;
+    z    = data & 0x0002;
+    return *this;
+  }
+};
+
+struct scmr_t {
+  unsigned ht;
+  bool ron;
+  bool ran;
+  unsigned md;
+
+  operator uint8_t() const {
+    return ((ht >> 1) << 5) | (ron << 4) | (ran << 3) | ((ht & 1) << 2) | (md);
+  }
+
+  scmr_t& operator=(uint8_t data) {
+    ht  = (bool)(data & 0x20) << 1;
+    ht |= (bool)(data & 0x04) << 0;
+    ron = data & 0x10;
+    ran = data & 0x08;
+    md  = data & 0x03;
+    return *this;
+  }
+};
+
+struct por_t {
+  bool obj;
+  bool freezehigh;
+  bool highnibble;
+  bool dither;
+  bool transparent;
+
+  operator uint8_t() const {
+    return (obj << 4) | (freezehigh << 3) | (highnibble << 2) | (dither << 1) | (transparent);
+  }
+
+  por_t& operator=(uint8_t data) {
+    obj         = data & 0x10;
+    freezehigh  = data & 0x08;
+    highnibble  = data & 0x04;
+    dither      = data & 0x02;
+    transparent = data & 0x01;
+    return *this;
+  }
+};
+
+struct cfgr_t {
+  bool irq;
+  bool ms0;
+
+  operator uint8_t() const {
+    return (irq << 7) | (ms0 << 5);
+  }
+
+  cfgr_t& operator=(uint8_t data) {
+    irq = data & 0x80;
+    ms0 = data & 0x20;
+    return *this;
+  }
+};
+
+struct regs_t {
+  uint8_t pipeline;
+  uint16_t ramaddr;
+
+  reg16_t r[16];    //general purpose registers
+  sfr_t sfr;        //status flag register
+  uint8_t pbr;      //program bank register
+  uint8_t rombr;    //game pack ROM bank register
+  bool rambr;       //game pack RAM bank register
+  uint16_t cbr;     //cache base register
+  uint8_t scbr;     //screen base register
+  scmr_t scmr;      //screen mode register
+  uint8_t colr;     //color register
+  por_t por;        //plot option register
+  bool bramr;       //back-up RAM register
+  uint8_t vcr;      //version code register
+  cfgr_t cfgr;      //config register
+  bool clsr;        //clock select register
+
+  unsigned romcl;   //clock ticks until romdr is valid
+  uint8_t romdr;    //ROM buffer data register
+
+  unsigned ramcl;   //clock ticks until ramdr is valid
+  uint16_t ramar;   //RAM buffer address register
+  uint8_t ramdr;    //RAM buffer data register
+
+  reg16_t *sreg, *dreg;
+  reg16_t& sr() { return *sreg; }  //source register (from)
+  reg16_t& dr() { return *dreg; }  //destination register (to)
+
+  void reset() {
+    sfr.b    = 0;
+    sfr.alt1 = 0;
+    sfr.alt2 = 0;
+
+    sreg = &r[0];
+    dreg = &r[0];
+  }
+} regs;
+
+struct cache_t {
+  uint8_t buffer[512];
+  bool valid[32];
+} cache;
+
+struct pixelcache_t {
+  uint16_t offset;
+  uint8_t bitpend;
+  uint8_t data[8];
+} pixelcache[2];

src/chip/superfx/disasm/disasm.cpp

@@ -0,0 +1,275 @@
+void SuperFX::disassemble_opcode(char *output) {
+  *output = 0;
+
+  if(!regs.sfr.alt2) {
+    if(!regs.sfr.alt1) {
+      disassemble_alt0(output);
+    } else {
+      disassemble_alt1(output);
+    }
+  } else {
+    if(!regs.sfr.alt1) {
+      disassemble_alt2(output);
+    } else {
+      disassemble_alt3(output);
+    }
+  }
+
+  unsigned length = strlen(output);
+  while(length++ < 20) strcat(output, " ");
+}
+
+#define case4(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3
+#define case6(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5
+#define case12(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
+  case id+ 8: case id+ 9: case id+10: case id+11
+#define case15(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
+  case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14
+#define case16(id) \
+  case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
+  case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14: case id+15
+
+#define op0 regs.pipeline
+#define op1 superfxbus.read((regs.pbr << 16) + regs.r[15] + 0)
+#define op2 superfxbus.read((regs.pbr << 16) + regs.r[15] + 1)
+
+void SuperFX::disassemble_alt0(char *output) {
+  char t[256] = "";
+  switch(op0) {
+    case  (0x00): sprintf(t, "stop"); break;
+    case  (0x01): sprintf(t, "nop"); break;
+    case  (0x02): sprintf(t, "cache"); break;
+    case  (0x03): sprintf(t, "lsr"); break;
+    case  (0x04): sprintf(t, "rol"); break;
+    case  (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
+    case  (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
+    case  (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
+    case  (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
+    case  (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
+    case  (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
+    case  (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
+    case  (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
+    case  (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
+    case  (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
+    case  (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
+    case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
+    case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
+    case12(0x30): sprintf(t, "stw (r%u)", op0 & 15); break;
+    case  (0x3c): sprintf(t, "loop"); break;
+    case  (0x3d): sprintf(t, "alt1"); break;
+    case  (0x3e): sprintf(t, "alt2"); break;
+    case  (0x3f): sprintf(t, "alt3"); break;
+    case12(0x40): sprintf(t, "ldw (r%u)", op0 & 15); break;
+    case  (0x4c): sprintf(t, "plot"); break;
+    case  (0x4d): sprintf(t, "swap"); break;
+    case  (0x4e): sprintf(t, "color"); break;
+    case  (0x4f): sprintf(t, "not"); break;
+    case16(0x50): sprintf(t, "add r%u", op0 & 15); break;
+    case16(0x60): sprintf(t, "sub r%u", op0 & 15); break;
+    case  (0x70): sprintf(t, "merge"); break;
+    case15(0x71): sprintf(t, "and r%u", op0 & 15); break;
+    case16(0x80): sprintf(t, "mult r%u", op0 & 15); break;
+    case  (0x90): sprintf(t, "sbk"); break;
+    case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
+    case  (0x95): sprintf(t, "sex"); break;
+    case  (0x96): sprintf(t, "asr"); break;
+    case  (0x97): sprintf(t, "ror"); break;
+    case6 (0x98): sprintf(t, "jmp r%u", op0 & 15); break;
+    case  (0x9e): sprintf(t, "lob"); break;
+    case  (0x9f): sprintf(t, "fmult"); break;
+    case16(0xa0): sprintf(t, "ibt r%u,#$%.2x", op0 & 15, op1); break;
+    case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
+    case  (0xc0): sprintf(t, "hib");
+    case15(0xc1): sprintf(t, "or r%u", op0 & 15); break;
+    case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
+    case  (0xdf): sprintf(t, "getc"); break;
+    case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
+    case  (0xef): sprintf(t, "getb"); break;
+    case16(0xf0): sprintf(t, "iwt r%u,#$%.2x%.2x", op0 & 15, op2, op1); break;
+  }
+  strcat(output, t);
+}
+
+void SuperFX::disassemble_alt1(char *output) {
+  char t[256] = "";
+  switch(op0) {
+    case  (0x00): sprintf(t, "stop"); break;
+    case  (0x01): sprintf(t, "nop"); break;
+    case  (0x02): sprintf(t, "cache"); break;
+    case  (0x03): sprintf(t, "lsr"); break;
+    case  (0x04): sprintf(t, "rol"); break;
+    case  (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
+    case  (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
+    case  (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
+    case  (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
+    case  (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
+    case  (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
+    case  (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
+    case  (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
+    case  (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
+    case  (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
+    case  (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
+    case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
+    case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
+    case12(0x30): sprintf(t, "stb (r%u)", op0 & 15); break;
+    case  (0x3c): sprintf(t, "loop"); break;
+    case  (0x3d): sprintf(t, "alt1"); break;
+    case  (0x3e): sprintf(t, "alt2"); break;
+    case  (0x3f): sprintf(t, "alt3"); break;
+    case12(0x40): sprintf(t, "ldb (r%u)", op0 & 15); break;
+    case  (0x4c): sprintf(t, "rpix"); break;
+    case  (0x4d): sprintf(t, "swap"); break;
+    case  (0x4e): sprintf(t, "cmode"); break;
+    case  (0x4f): sprintf(t, "not"); break;
+    case16(0x50): sprintf(t, "adc r%u", op0 & 15); break;
+    case16(0x60): sprintf(t, "sbc r%u", op0 & 15); break;
+    case  (0x70): sprintf(t, "merge"); break;
+    case15(0x71): sprintf(t, "bic r%u", op0 & 15); break;
+    case16(0x80): sprintf(t, "umult r%u", op0 & 15); break;
+    case  (0x90): sprintf(t, "sbk"); break;
+    case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
+    case  (0x95): sprintf(t, "sex"); break;
+    case  (0x96): sprintf(t, "div2"); break;
+    case  (0x97): sprintf(t, "ror"); break;
+    case6 (0x98): sprintf(t, "ljmp r%u", op0 & 15); break;
+    case  (0x9e): sprintf(t, "lob"); break;
+    case  (0x9f): sprintf(t, "lmult"); break;
+    case16(0xa0): sprintf(t, "lms r%u,(#$%.4x)", op0 & 15, op1 << 1); break;
+    case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
+    case  (0xc0): sprintf(t, "hib"); break;
+    case15(0xc1): sprintf(t, "xor r%u", op0 & 15); break;
+    case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
+    case  (0xdf): sprintf(t, "getc"); break;
+    case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
+    case  (0xef): sprintf(t, "getbh"); break;
+    case16(0xf0): sprintf(t, "lm r%u", op0 & 15); break;
+  }
+  strcat(output, t);
+}
+
+void SuperFX::disassemble_alt2(char *output) {
+  char t[256] = "";
+  switch(op0) {
+    case  (0x00): sprintf(t, "stop"); break;
+    case  (0x01): sprintf(t, "nop"); break;
+    case  (0x02): sprintf(t, "cache"); break;
+    case  (0x03): sprintf(t, "lsr"); break;
+    case  (0x04): sprintf(t, "rol"); break;
+    case  (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
+    case  (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
+    case  (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
+    case  (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
+    case  (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
+    case  (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
+    case  (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
+    case  (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
+    case  (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
+    case  (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
+    case  (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
+    case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
+    case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
+    case12(0x30): sprintf(t, "stw (r%u)", op0 & 15); break;
+    case  (0x3c): sprintf(t, "loop"); break;
+    case  (0x3d): sprintf(t, "alt1"); break;
+    case  (0x3e): sprintf(t, "alt2"); break;
+    case  (0x3f): sprintf(t, "alt3"); break;
+    case12(0x40): sprintf(t, "ldw (r%u)", op0 & 15); break;
+    case  (0x4c): sprintf(t, "plot"); break;
+    case  (0x4d): sprintf(t, "swap"); break;
+    case  (0x4e): sprintf(t, "color"); break;
+    case  (0x4f): sprintf(t, "not"); break;
+    case16(0x50): sprintf(t, "add #%u", op0 & 15); break;
+    case16(0x60): sprintf(t, "sub #%u", op0 & 15); break;
+    case  (0x70): sprintf(t, "merge"); break;
+    case15(0x71): sprintf(t, "and #%u", op0 & 15); break;
+    case16(0x80): sprintf(t, "mult #%u", op0 & 15); break;
+    case  (0x90): sprintf(t, "sbk"); break;
+    case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
+    case  (0x95): sprintf(t, "sex"); break;
+    case  (0x96): sprintf(t, "asr"); break;
+    case  (0x97): sprintf(t, "ror"); break;
+    case6 (0x98): sprintf(t, "jmp r%u", op0 & 15); break;
+    case  (0x9e): sprintf(t, "lob"); break;
+    case  (0x9f): sprintf(t, "fmult"); break;
+    case16(0xa0): sprintf(t, "sms r%u,(#$%.4x)", op0 & 15, op1 << 1); break;
+    case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
+    case  (0xc0): sprintf(t, "hib"); break;
+    case15(0xc1): sprintf(t, "or #%u", op0 & 15); break;
+    case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
+    case  (0xdf): sprintf(t, "ramb"); break;
+    case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
+    case  (0xef): sprintf(t, "getbl"); break;
+    case16(0xf0): sprintf(t, "sm r%u", op0 & 15); break;
+  }
+  strcat(output, t);
+}
+
+void SuperFX::disassemble_alt3(char *output) {
+  char t[256] = "";
+  switch(op0) {
+    case  (0x00): sprintf(t, "stop"); break;
+    case  (0x01): sprintf(t, "nop"); break;
+    case  (0x02): sprintf(t, "cache"); break;
+    case  (0x03): sprintf(t, "lsr"); break;
+    case  (0x04): sprintf(t, "rol"); break;
+    case  (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
+    case  (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
+    case  (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
+    case  (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
+    case  (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
+    case  (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
+    case  (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
+    case  (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
+    case  (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
+    case  (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
+    case  (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
+    case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
+    case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
+    case12(0x30): sprintf(t, "stb (r%u)", op0 & 15); break;
+    case  (0x3c): sprintf(t, "loop"); break;
+    case  (0x3d): sprintf(t, "alt1"); break;
+    case  (0x3e): sprintf(t, "alt2"); break;
+    case  (0x3f): sprintf(t, "alt3"); break;
+    case12(0x40): sprintf(t, "ldb (r%u)", op0 & 15); break;
+    case  (0x4c): sprintf(t, "rpix"); break;
+    case  (0x4d): sprintf(t, "swap"); break;
+    case  (0x4e): sprintf(t, "cmode"); break;
+    case  (0x4f): sprintf(t, "not"); break;
+    case16(0x50): sprintf(t, "adc #%u", op0 & 15); break;
+    case16(0x60): sprintf(t, "cmp r%u", op0 & 15); break;
+    case  (0x70): sprintf(t, "merge"); break;
+    case15(0x71): sprintf(t, "bic #%u", op0 & 15); break;
+    case16(0x80): sprintf(t, "umult #%u", op0 & 15); break;
+    case  (0x90): sprintf(t, "sbk"); break;
+    case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
+    case  (0x95): sprintf(t, "sex"); break;
+    case  (0x96): sprintf(t, "div2"); break;
+    case  (0x97): sprintf(t, "ror"); break;
+    case6 (0x98): sprintf(t, "ljmp r%u", op0 & 15); break;
+    case  (0x9e): sprintf(t, "lob"); break;
+    case  (0x9f): sprintf(t, "lmult"); break;
+    case16(0xa0): sprintf(t, "lms r%u", op0 & 15); break;
+    case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
+    case  (0xc0): sprintf(t, "hib"); break;
+    case15(0xc1): sprintf(t, "xor #%u", op0 & 15); break;
+    case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
+    case  (0xdf): sprintf(t, "romb"); break;
+    case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
+    case  (0xef): sprintf(t, "getbs"); break;
+    case16(0xf0): sprintf(t, "lm r%u", op0 & 15); break;
+  }
+  strcat(output, t);
+}
+
+#undef case4
+#undef case6
+#undef case12
+#undef case15
+#undef case16
+#undef op0
+#undef op1
+#undef op2

src/chip/superfx/disasm/disasm.hpp

@@ -0,0 +1,5 @@
+void disassemble_opcode(char *output);
+void disassemble_alt0(char *output);
+void disassemble_alt1(char *output);
+void disassemble_alt2(char *output);
+void disassemble_alt3(char *output);

src/chip/superfx/memory/memory.cpp

@@ -0,0 +1,67 @@
+uint8_t SuperFX::op_read(uint16_t addr) {
+  uint16_t offset = addr - regs.cbr;
+  if(offset < 512) {
+    if(cache.valid[offset >> 4] == false) {
+      unsigned dp = offset & 0xfff0;
+      unsigned sp = (regs.pbr << 16) + ((regs.cbr + dp) & 0xfff0);
+      for(unsigned n = 0; n < 16; n++) {
+        add_clocks(memory_access_speed);
+        cache.buffer[dp++] = superfxbus.read(sp++);
+      }
+      cache.valid[offset >> 4] = true;
+    } else {
+      add_clocks(cache_access_speed);
+    }
+    return cache.buffer[offset];
+  }
+
+  if(regs.pbr <= 0x5f) {
+    //$[00-5f]:[0000-ffff] ROM
+    rombuffer_sync();
+    add_clocks(memory_access_speed);
+    return superfxbus.read((regs.pbr << 16) + addr);
+  } else {
+    //$[60-7f]:[0000-ffff] RAM
+    rambuffer_sync();
+    add_clocks(memory_access_speed);
+    return superfxbus.read((regs.pbr << 16) + addr);
+  }
+}
+
+uint8_t SuperFX::peekpipe() {
+  uint8_t result = regs.pipeline;
+  regs.pipeline = op_read(regs.r[15]);
+  r15_modified = false;
+  return result;
+}
+
+uint8_t SuperFX::pipe() {
+  uint8_t result = regs.pipeline;
+  regs.pipeline = op_read(++regs.r[15]);
+  r15_modified = false;
+  return result;
+}
+
+void SuperFX::cache_flush() {
+  for(unsigned n = 0; n < 32; n++) cache.valid[n] = false;
+}
+
+uint8_t SuperFX::cache_mmio_read(uint16_t addr) {
+  addr = (addr + regs.cbr) & 511;
+  return cache.buffer[addr];
+}
+
+void SuperFX::cache_mmio_write(uint16_t addr, uint8_t data) {
+  addr = (addr + regs.cbr) & 511;
+  cache.buffer[addr] = data;
+  if((addr & 15) == 15) cache.valid[addr >> 4] = true;
+}
+
+void SuperFX::memory_reset() {
+  for(unsigned n = 0; n < 512; n++) cache.buffer[n] = 0x00;
+  for(unsigned n = 0; n < 32; n++) cache.valid[n] = false;
+  for(unsigned n = 0; n < 2; n++) {
+    pixelcache[n].offset = ~0;
+    pixelcache[n].bitpend = 0x00;
+  }
+}

src/chip/superfx/memory/memory.hpp

@@ -0,0 +1,9 @@
+uint8_t op_read(uint16_t addr);
+alwaysinline uint8_t peekpipe();
+alwaysinline uint8_t pipe();
+
+void cache_flush();
+uint8_t cache_mmio_read(uint16_t addr);
+void cache_mmio_write(uint16_t addr, uint8_t data);
+
+void memory_reset();

src/chip/superfx/mmio/mmio.cpp

@@ -0,0 +1,118 @@
+#ifdef SUPERFX_CPP
+
+uint8_t SuperFX::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+
+  if(addr >= 0x3100 && addr <= 0x32ff) {
+    return cache_mmio_read(addr - 0x3100);
+  }
+
+  if(addr >= 0x3000 && addr <= 0x301f) {
+    return regs.r[(addr >> 1) & 15] >> ((addr & 1) << 3);
+  }
+
+  switch(addr) {
+    case 0x3030: {
+      return regs.sfr >> 0;
+    }
+
+    case 0x3031: {
+      uint8_t r = regs.sfr >> 8;
+      regs.sfr.irq = 0;
+      cpu.regs.irq = 0;
+      return r;
+    }
+
+    case 0x3034: {
+      return regs.pbr;
+    }
+
+    case 0x3036: {
+      return regs.rombr;
+    }
+
+    case 0x303b: {
+      return regs.vcr;
+    }
+
+    case 0x303c: {
+      return regs.rambr;
+    }
+
+    case 0x303e: {
+      return regs.cbr >> 0;
+    }
+
+    case 0x303f: {
+      return regs.cbr >> 8;
+    }
+  }
+
+  return 0x00;
+}
+
+void SuperFX::mmio_write(unsigned addr, uint8_t data) {
+  addr &= 0xffff;
+
+  if(addr >= 0x3100 && addr <= 0x32ff) {
+    return cache_mmio_write(addr - 0x3100, data);
+  }
+
+  if(addr >= 0x3000 && addr <= 0x301f) {
+    unsigned n = (addr >> 1) & 15;
+    if((addr & 1) == 0) {
+      regs.r[n] = (regs.r[n] & 0xff00) | data;
+    } else {
+      regs.r[n] = (data << 8) | (regs.r[n] & 0xff);
+    }
+
+    if(addr == 0x301f) regs.sfr.g = 1;
+    return;
+  }
+
+  switch(addr) {
+    case 0x3030: {
+      bool g = regs.sfr.g;
+      regs.sfr = (regs.sfr & 0xff00) | (data << 0);
+      if(g == 1 && regs.sfr.g == 0) {
+        regs.cbr = 0x0000;
+        cache_flush();
+      }
+    } break;
+
+    case 0x3031: {
+      regs.sfr = (data << 8) | (regs.sfr & 0x00ff);
+    } break;
+
+    case 0x3033: {
+      regs.bramr = data;
+    } break;
+
+    case 0x3034: {
+      regs.pbr = data;
+      cache_flush();
+    } break;
+
+    case 0x3037: {
+      regs.cfgr = data;
+      if(regs.clsr) regs.cfgr.ms0 = 0;  //cannot use high-speed multiplication in 21MHz mode
+    } break;
+
+    case 0x3038: {
+      regs.scbr = data;
+    } break;
+
+    case 0x3039: {
+      regs.clsr = data;
+      if(regs.clsr) regs.cfgr.ms0 = 0;  //cannot use high-speed multiplication in 21MHz mode
+      cache_access_speed  = (regs.clsr ? config.superfx.fast_cache_speed  : config.superfx.slow_cache_speed );
+      memory_access_speed = (regs.clsr ? config.superfx.fast_memory_speed : config.superfx.slow_memory_speed);
+    } break;
+
+    case 0x303a: {
+      regs.scmr = data;
+    } break;
+  }
+}
+
+#endif

src/chip/superfx/mmio/mmio.hpp

@@ -0,0 +1,2 @@
+uint8_t mmio_read(unsigned addr);
+void mmio_write(unsigned addr, uint8_t data);

src/chip/superfx/superfx.cpp

@@ -0,0 +1,61 @@
+#include <../base.hpp>
+
+#define SUPERFX_CPP
+namespace SNES {
+
+#include "bus/bus.cpp"
+#include "core/core.cpp"
+#include "memory/memory.cpp"
+#include "mmio/mmio.cpp"
+#include "timing/timing.cpp"
+#include "disasm/disasm.cpp"
+
+SuperFX superfx;
+
+void SuperFX::enter() {
+  while(true) {
+    while(regs.sfr.g == 0) add_clocks(2);
+    exec_opcode();
+  }
+}
+
+void SuperFX::init() {
+  initialize_opcode_table();
+  regs.r[14].on_modify = bind(&SuperFX::r14_modify, this);
+  regs.r[15].on_modify = bind(&SuperFX::r15_modify, this);
+}
+
+void SuperFX::enable() {
+  for(uint16_t i = 0x3000; i <= 0x32ff; i++) memory::mmio.map(i, *this);
+}
+
+void SuperFX::power() {
+  reset();
+}
+
+void SuperFX::reset() {
+  superfxbus.init();
+
+  for(unsigned n = 0; n < 16; n++) regs.r[n] = 0x0000;
+  regs.sfr   = 0x0000;
+  regs.pbr   = 0x00;
+  regs.rombr = 0x00;
+  regs.rambr = 0;
+  regs.cbr   = 0x0000;
+  regs.scbr  = 0x00;
+  regs.scmr  = 0x00;
+  regs.colr  = 0x00;
+  regs.por   = 0x00;
+  regs.bramr = 0;
+  regs.vcr   = 0x04;
+  regs.cfgr  = 0x00;
+  regs.clsr  = 0;
+  regs.pipeline = 0x01;  //nop
+  regs.ramaddr = 0x0000;
+  regs.reset();
+
+  memory_reset();
+  timing_reset();
+}
+
+};

src/chip/superfx/superfx.hpp

@@ -0,0 +1,20 @@
+#include "bus/bus.hpp"
+
+class SuperFX : public MMIO {
+public:
+  #include "core/core.hpp"
+  #include "memory/memory.hpp"
+  #include "mmio/mmio.hpp"
+  #include "timing/timing.hpp"
+  #include "disasm/disasm.hpp"
+
+  void enter();
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+};
+
+extern SuperFX superfx;
+extern SuperFXBus superfxbus;

src/chip/superfx/timing/timing.cpp

@@ -0,0 +1,72 @@
+void SuperFX::add_clocks(unsigned clocks) {
+  if(regs.romcl) {
+    regs.romcl -= min(clocks, regs.romcl);
+    if(regs.romcl == 0) {
+      regs.sfr.r = 0;
+      regs.romdr = superfxbus.read((regs.rombr << 16) + regs.r[14]);
+    }
+  }
+
+  if(regs.ramcl) {
+    regs.ramcl -= min(clocks, regs.ramcl);
+    if(regs.ramcl == 0) {
+      superfxbus.write(0x700000 + (regs.rambr << 16) + regs.ramar, regs.ramdr);
+    }
+  }
+
+  scheduler.addclocks_cop(clocks);
+  scheduler.sync_copcpu();
+}
+
+void SuperFX::rombuffer_sync() {
+  if(regs.romcl) add_clocks(regs.romcl);
+}
+
+void SuperFX::rombuffer_update() {
+  regs.sfr.r = 1;
+  regs.romcl = memory_access_speed;
+}
+
+uint8_t SuperFX::rombuffer_read() {
+  rombuffer_sync();
+  return regs.romdr;
+}
+
+void SuperFX::rambuffer_sync() {
+  if(regs.ramcl) add_clocks(regs.ramcl);
+}
+
+uint8_t SuperFX::rambuffer_read(uint16_t addr) {
+  rambuffer_sync();
+  return superfxbus.read(0x700000 + (regs.rambr << 16) + addr);
+}
+
+void SuperFX::rambuffer_write(uint16_t addr, uint8_t data) {
+  rambuffer_sync();
+  regs.ramcl = memory_access_speed;
+  regs.ramar = addr;
+  regs.ramdr = data;
+}
+
+void SuperFX::r14_modify(uint16_t data) {
+  regs.r[14].data = data;
+  rombuffer_update();
+}
+
+void SuperFX::r15_modify(uint16_t data) {
+  regs.r[15].data = data;
+  r15_modified = true;
+}
+
+void SuperFX::timing_reset() {
+  cache_access_speed  = config.superfx.slow_cache_speed;
+  memory_access_speed = config.superfx.slow_memory_speed;
+  r15_modified = false;
+
+  regs.romcl = 0;
+  regs.romdr = 0;
+
+  regs.ramcl = 0;
+  regs.ramar = 0;
+  regs.ramdr = 0;
+}

src/chip/superfx/timing/timing.hpp

@@ -0,0 +1,18 @@
+unsigned cache_access_speed;
+unsigned memory_access_speed;
+bool r15_modified;
+
+void add_clocks(unsigned clocks);
+
+void rombuffer_sync();
+void rombuffer_update();
+uint8_t rombuffer_read();
+
+void rambuffer_sync();
+uint8_t rambuffer_read(uint16_t addr);
+void rambuffer_write(uint16_t addr, uint8_t data);
+
+void r14_modify(uint16_t);
+void r15_modify(uint16_t);
+
+void timing_reset();

src/clean.bat

@@ -1 +1 @@
-@make platform=win compiler=mingw32-gcc clean
+@mingw32-make clean

src/clean.sh

@@ -1 +0,0 @@
-make platform=x compiler=gcc clean

src/config/config.cpp

@@ -1,138 +0,0 @@
-namespace config {
-
-configuration& config() {
-  static configuration config;
-  return config;
-}
-
-integral_setting File::autodetect_type(config(), "file.autodetect_type",
-  "Auto-detect file type by inspecting file header, rather than by file extension.\n"
-  "In other words, if a .zip file is renamed to .smc, it will still be correctly\n"
-  "identified as a .zip file. However, there is an infinitesimal (1:~500,000,000)\n"
-  "chance of a false detection when loading an uncompressed image file, if this\n"
-  "option is enabled.",
-  integral_setting::boolean, false);
-
-integral_setting File::bypass_patch_crc32(config(), "file.bypass_patch_crc32",
-  "UPS patches contain CRC32s to validate that a patch was applied successfully.\n"
-  "By default, if this validation fails, said patch will not be applied.\n"
-  "Setting this option to true will bypass the validation,\n"
-  "which may or may not result in a working image.\n"
-  "Enabling this option is strongly discouraged.",
-  integral_setting::boolean, false);
-
-string file_updatepath(const char *req_file, const char *req_path) {
-  string file(req_file);
-  replace(file, "\\", "/");
-  if(!req_path || strlen(req_path) == 0) { return file; }
-
-  string path(req_path);
-  replace(path, "\\", "/");
-  if(!strend(path, "/")) { strcat(path, "/"); }
-
-  if(strbegin(path, "./")) {
-    ltrim(path(), "./");
-    string temp;
-    strcpy(temp, config::path.base);
-    strcat(temp, path);
-    strcpy(path, temp);
-  }
-
-  lstring part;
-  split(part, "/", file);
-  strcat(path, part[count(part) - 1]);
-  return path;
-}
-
-string_setting Path::base("path.base", "Path that bsnes resides in", "");
-string_setting Path::user("path.user", "Path to user folder", "");
-
-string_setting Path::rom(config(), "path.rom",
-  "Default path to look for ROM files in (\"\" = use default directory)", "");
-string_setting Path::patch(config(), "path.patch",
-  "Default path for all UPS patch files (\"\" = use current directory)", "");
-string_setting Path::save(config(), "path.save",
-  "Default path for all save RAM files (\"\" = use current directory)", "");
-string_setting Path::cheat(config(), "path.cheat",
-  "Default path for all cheat files (\"\" = use current directory)", "");
-string_setting Path::bsx(config(), "path.bsx", "", "");
-string_setting Path::st(config(), "path.st", "", "");
-
-integral_setting SNES::controller_port1(config(), "snes.controller_port1",
-  "Controller attached to SNES port 1", integral_setting::decimal, ::SNES::Input::DeviceJoypad);
-integral_setting SNES::controller_port2(config(), "snes.controller_port2",
-  "Controller attached to SNES port 2", integral_setting::decimal, ::SNES::Input::DeviceJoypad);
-integral_setting SNES::expansion_port(config(), "snes.expansion_port",
-  "Device attached to SNES expansion port\n"
-  "0 = None\n"
-  "1 = Satellaview BS-X\n"
-  "", integral_setting::decimal, ::SNES::ExpansionBSX);
-integral_setting SNES::region(config(), "snes.region",
-  "SNES regional model\n"
-  "0 = Auto-detect based on cartridge\n"
-  "1 = NTSC\n"
-  "2 = PAL\n"
-  "", integral_setting::decimal, ::SNES::Autodetect);
-
-integral_setting CPU::ntsc_clock_rate(config(), "cpu.ntsc_clock_rate",
-  "NTSC S-CPU clock rate (in hz)", integral_setting::decimal, 21477272);
-integral_setting CPU::pal_clock_rate(config(), "cpu.pal_clock_rate",
-  "PAL S-CPU clock rate (in hz)", integral_setting::decimal,  21281370);
-integral_setting CPU::wram_init_value(config(), "cpu.wram_init_value",
-  "Value to initialize 128k WRAM to upon power cycle.\n"
-  "Note that on real hardware, this value is undefined; meaning it can vary\n"
-  "per power-on, and per SNES unit. Such randomness is undesirable for an\n"
-  "emulator, so a static value is needed. There is also some form of pattern\n"
-  "to the randomness that has yet to be determined, which some games rely upon.\n"
-  "A value of 0x55 is safe for all known commercial software, and should be used.\n"
-  "However, some software written for SNES copiers, or backup units, relies on\n"
-  "WRAM being initialized to 0x00; which was a side-effect of the BIOS program\n"
-  "which executed on these copiers. Using 0x00 will therefore fix many homebrew\n"
-  "programs, but *will* break some poorly programmed commercial software titles,\n"
-  "which do not properly initialize WRAM upon power cycle.\n",
-  integral_setting::hex, 0x55);
-
-integral_setting SMP::ntsc_clock_rate(config(), "smp.ntsc_clock_rate",
-  "NTSC S-SMP clock rate (in hz)", integral_setting::decimal, 32041 * 768);
-integral_setting SMP::pal_clock_rate(config(), "smp.pal_clock_rate",
-  "PAL S-SMP clock rate (in hz)", integral_setting::decimal,  32041 * 768);
-
-integral_setting PPU::Hack::render_scanline_position(config(), "ppu.hack.render_scanline_position",
-  "Approximate HCLOCK position to render at for scanline-based renderers",
-  integral_setting::decimal, 512);
-integral_setting PPU::Hack::obj_cache(config(), "ppu.hack.obj_cache",
-  "Cache OAM OBJ attributes one scanline before rendering\n"
-  "This is technically closer to the actual operation of the SNES,\n"
-  "but can cause problems in some games if enabled",
-  integral_setting::boolean, false);
-integral_setting PPU::Hack::oam_address_invalidation(config(), "ppu.hack.oam_address_invalidation",
-  "OAM access address changes during active display, as the S-PPU reads\n"
-  "data to render the display. Thusly, the address retrieved when accessing\n"
-  "OAM during active display is unpredictable. Unfortunately, the exact\n"
-  "algorithm for this is completely unknown at this time. It is more hardware\n"
-  "accurate to enable this setting, but one must *not* rely on the actual\n"
-  "address to match hardware under emulation.",
-  integral_setting::boolean, true);
-integral_setting PPU::Hack::cgram_address_invalidation(config(), "ppu.hack.cgram_address_invalidation",
-  "CGRAM access address changes during active display (excluding hblank), as\n"
-  "the S-PPU reads data to render the display. Thusly, as with OAM, the access\n"
-  "address is unpredictable. Again, enabling this setting is more hardware\n"
-  "accurate, but one must *not* rely on the actual address to match hardware\n"
-  "under emulation.",
-  integral_setting::boolean, true);
-
-integral_setting PPU::opt_enable("ppu.opt_enable", "Enable offset-per-tile effects", integral_setting::boolean, true);
-integral_setting PPU::bg1_pri0_enable("ppu.bg1_pri0_enable", "Enable BG1 Priority 0", integral_setting::boolean, true);
-integral_setting PPU::bg1_pri1_enable("ppu.bg1_pri1_enable", "Enable BG1 Priority 1", integral_setting::boolean, true);
-integral_setting PPU::bg2_pri0_enable("ppu.bg2_pri0_enable", "Enable BG2 Priority 0", integral_setting::boolean, true);
-integral_setting PPU::bg2_pri1_enable("ppu.bg2_pri1_enable", "Enable BG2 Priority 1", integral_setting::boolean, true);
-integral_setting PPU::bg3_pri0_enable("ppu.bg3_pri0_enable", "Enable BG3 Priority 0", integral_setting::boolean, true);
-integral_setting PPU::bg3_pri1_enable("ppu.bg3_pri1_enable", "Enable BG3 Priority 1", integral_setting::boolean, true);
-integral_setting PPU::bg4_pri0_enable("ppu.bg4_pri0_enable", "Enable BG4 Priority 0", integral_setting::boolean, true);
-integral_setting PPU::bg4_pri1_enable("ppu.bg4_pri1_enable", "Enable BG4 Priority 1", integral_setting::boolean, true);
-integral_setting PPU::oam_pri0_enable("ppu.oam_pri0_enable", "Enable OAM Priority 0", integral_setting::boolean, true);
-integral_setting PPU::oam_pri1_enable("ppu.oam_pri1_enable", "Enable OAM Priority 1", integral_setting::boolean, true);
-integral_setting PPU::oam_pri2_enable("ppu.oam_pri2_enable", "Enable OAM Priority 2", integral_setting::boolean, true);
-integral_setting PPU::oam_pri3_enable("ppu.oam_pri3_enable", "Enable OAM Priority 3", integral_setting::boolean, true);
-
-} //namespace config

src/config/config.h

@@ -1,50 +0,0 @@
-namespace config {
-
-extern configuration& config();
-
-string file_updatepath(const char*, const char*);
-
-extern struct File {
-  static integral_setting autodetect_type;
-  static integral_setting bypass_patch_crc32;
-} file;
-
-extern struct Path {
-  static string_setting base, user, rom, patch, save, cheat;
-  static string_setting bsx, st;
-} path;
-
-extern struct SNES {
-  static integral_setting controller_port1;
-  static integral_setting controller_port2;
-  static integral_setting expansion_port;
-  static integral_setting region;
-} snes;
-
-extern struct CPU {
-  static integral_setting ntsc_clock_rate, pal_clock_rate;
-  static integral_setting wram_init_value;
-} cpu;
-
-extern struct SMP {
-  static integral_setting ntsc_clock_rate, pal_clock_rate;
-} smp;
-
-extern struct PPU {
-  struct Hack {
-    static integral_setting render_scanline_position;
-    static integral_setting obj_cache;
-    static integral_setting oam_address_invalidation;
-    static integral_setting cgram_address_invalidation;
-  } hack;
-
-  static integral_setting opt_enable;
-  static integral_setting bg1_pri0_enable, bg1_pri1_enable;
-  static integral_setting bg2_pri0_enable, bg2_pri1_enable;
-  static integral_setting bg3_pri0_enable, bg3_pri1_enable;
-  static integral_setting bg4_pri0_enable, bg4_pri1_enable;
-  static integral_setting oam_pri0_enable, oam_pri1_enable;
-  static integral_setting oam_pri2_enable, oam_pri3_enable;
-} ppu;
-
-};

src/cpu/core/bpp.sh

@@ -0,0 +1,3 @@
+clear
+bpp opcode_functions.cpp opcode_functions.bpp
+bpp opcode_headers.hpp opcode_headers.bpp

src/cpu/core/core.cpp

@@ -0,0 +1,50 @@
+#include <../base.hpp>
+
+#define CPUCORE_CPP
+namespace SNES {
+
+#include "opcode_algorithms.cpp"
+#include "opcode_functions.cpp"
+#include "opcode_tables.cpp"
+#include "disasm/disasm.cpp"
+
+//immediate, 2-cycle opcodes with I/O cycle will become bus read
+//when an IRQ is to be triggered immediately after opcode completion.
+//this affects the following opcodes:
+//  clc, cld, cli, clv, sec, sed, sei,
+//  tax, tay, txa, txy, tya, tyx,
+//  tcd, tcs, tdc, tsc, tsx, txs,
+//  inc, inx, iny, dec, dex, dey,
+//  asl, lsr, rol, ror, nop, xce.
+alwaysinline void CPUcore::op_io_irq() {
+  if(interrupt_pending()) {
+    //modify I/O cycle to bus read cycle, do not increment PC
+    op_read(regs.pc.d);
+  } else {
+    op_io();
+  }
+}
+
+alwaysinline void CPUcore::op_io_cond2() {
+  if(regs.d.l != 0x00) {
+    op_io();
+  }
+}
+
+alwaysinline void CPUcore::op_io_cond4(uint16 x, uint16 y) {
+  if(!regs.p.x || (x & 0xff00) != (y & 0xff00)) {
+    op_io();
+  }
+}
+
+alwaysinline void CPUcore::op_io_cond6(uint16 addr) {
+  if(regs.e && (regs.pc.w & 0xff00) != (addr & 0xff00)) {
+    op_io();
+  }
+}
+
+CPUcore::CPUcore() {
+  initialize_opcode_table();
+}
+
+};

src/cpu/core/core.hpp

@@ -1,11 +1,25 @@
-  CPUReg24 aa, rd;
-  uint8_t dp, sp;
+class CPUcore {
+public:
+  #include "registers.hpp"
+  #include "memory.hpp"
+  #include "opcode_headers.hpp"
+  #include "disasm/disasm.hpp"
 
-  void op_irq();
+  regs_t regs;
+  reg24_t aa, rd;
+  uint8_t sp, dp;
 
-  inline bool in_opcode() { return status.in_opcode; }
+  virtual void op_io() = 0;
+  virtual uint8_t op_read(uint32_t addr) = 0;
+  virtual void op_write(uint32_t addr, uint8_t data) = 0;
+  virtual void last_cycle() = 0;
+  virtual bool interrupt_pending() = 0;
+
+  void op_io_irq();
+  void op_io_cond2();
+  void op_io_cond4(uint16 x, uint16 y);
+  void op_io_cond6(uint16 addr);
 
-  //op_read
   void op_adc_b();
   void op_adc_w();
   void op_and_b();
@@ -30,7 +44,7 @@
   void op_ora_w();
   void op_sbc_b();
   void op_sbc_w();
-  //op_rmw
+
   void op_inc_b();
   void op_inc_w();
   void op_dec_b();
@@ -48,7 +62,18 @@
   void op_tsb_b();
   void op_tsb_w();
 
-  void op_io_irq();
-  void op_io_cond2();
-  void op_io_cond4(uint16 x, uint16 y);
-  void op_io_cond6(uint16 addr);
+  void (CPUcore::**opcode_table)();
+  void (CPUcore::*op_table[256 * 5])();
+  void initialize_opcode_table();
+  void update_table();
+
+  enum {
+    table_EM =    0,  // 8-bit accumulator,  8-bit index (emulation mode)
+    table_MX =  256,  // 8-bit accumulator,  8-bit index
+    table_Mx =  512,  // 8-bit accumulator, 16-bit index
+    table_mX =  768,  //16-bit accumulator,  8-bit index
+    table_mx = 1024,  //16-bit accumulator, 16-bit index
+  };
+
+  CPUcore();
+};

src/cpu/core/disasm/disasm.cpp

@@ -0,0 +1,479 @@
+uint8 CPUcore::dreadb(uint32 addr) {
+  if((addr & 0x40ffff) >= 0x2000 && (addr & 0x40ffff) <= 0x5fff) {
+    //$[00-3f|80-bf]:[2000-5fff]
+    //do not read MMIO registers within debugger
+    return 0x00;
+  }
+  return bus.read(addr);
+}
+
+uint16 CPUcore::dreadw(uint32 addr) {
+  uint16 r;
+  r  = dreadb((addr + 0) & 0xffffff) <<  0;
+  r |= dreadb((addr + 1) & 0xffffff) <<  8;
+  return r;
+}
+
+uint32 CPUcore::dreadl(uint32 addr) {
+  uint32 r;
+  r  = dreadb((addr + 0) & 0xffffff) <<  0;
+  r |= dreadb((addr + 1) & 0xffffff) <<  8;
+  r |= dreadb((addr + 2) & 0xffffff) << 16;
+  return r;
+}
+
+uint32 CPUcore::decode(uint8 offset_type, uint32 addr) {
+  uint32 r = 0;
+
+  switch(offset_type) {
+    case OPTYPE_DP:
+      r = (regs.d + (addr & 0xffff)) & 0xffff;
+      break;
+    case OPTYPE_DPX:
+      r = (regs.d + regs.x + (addr & 0xffff)) & 0xffff;
+      break;
+    case OPTYPE_DPY:
+      r = (regs.d + regs.y + (addr & 0xffff)) & 0xffff;
+      break;
+    case OPTYPE_IDP:
+      addr = (regs.d + (addr & 0xffff)) & 0xffff;
+      r = (regs.db << 16) + dreadw(addr);
+      break;
+    case OPTYPE_IDPX:
+      addr = (regs.d + regs.x + (addr & 0xffff)) & 0xffff;
+      r = (regs.db << 16) + dreadw(addr);
+      break;
+    case OPTYPE_IDPY:
+      addr = (regs.d + (addr & 0xffff)) & 0xffff;
+      r = (regs.db << 16) + dreadw(addr) + regs.y;
+      break;
+    case OPTYPE_ILDP:
+      addr = (regs.d + (addr & 0xffff)) & 0xffff;
+      r = dreadl(addr);
+      break;
+    case OPTYPE_ILDPY:
+      addr = (regs.d + (addr & 0xffff)) & 0xffff;
+      r = dreadl(addr) + regs.y;
+      break;
+    case OPTYPE_ADDR:
+      r = (regs.db << 16) + (addr & 0xffff);
+      break;
+    case OPTYPE_ADDR_PC:
+      r = (regs.pc.b << 16) + (addr & 0xffff);
+      break;
+    case OPTYPE_ADDRX:
+      r = (regs.db << 16) + (addr & 0xffff) + regs.x;
+      break;
+    case OPTYPE_ADDRY:
+      r = (regs.db << 16) + (addr & 0xffff) + regs.y;
+      break;
+    case OPTYPE_IADDR_PC:
+      r = (regs.pc.b << 16) + (addr & 0xffff);
+      break;
+    case OPTYPE_IADDRX:
+      r = (regs.pc.b << 16) + ((addr + regs.x) & 0xffff);
+      break;
+    case OPTYPE_ILADDR:
+      r = addr;
+      break;
+    case OPTYPE_LONG:
+      r = addr;
+      break;
+    case OPTYPE_LONGX:
+      r = (addr + regs.x);
+      break;
+    case OPTYPE_SR:
+      r = (regs.s + (addr & 0xff)) & 0xffff;
+      break;
+    case OPTYPE_ISRY:
+      addr = (regs.s + (addr & 0xff)) & 0xffff;
+      r = (regs.db << 16) + dreadw(addr) + regs.y;
+      break;
+    case OPTYPE_RELB:
+      r  = (regs.pc.b << 16) + ((regs.pc.w + 2) & 0xffff);
+      r += int8(addr);
+      break;
+    case OPTYPE_RELW:
+      r  = (regs.pc.b << 16) + ((regs.pc.w + 3) & 0xffff);
+      r += int16(addr);
+      break;
+  }
+
+  return(r & 0xffffff);
+}
+
+void CPUcore::disassemble_opcode(char *output) {
+  static reg24_t pc;
+  char t[256];
+  char *s = output;
+
+  if(false /* in_opcode() == true */) {
+    strcpy(s, "?????? <CPU within opcode>");
+    return;
+  }
+
+  pc.d = regs.pc.d;
+  sprintf(s, "%.6x ", (uint32)pc.d);
+
+  uint8 op  = dreadb(pc.d); pc.w++;
+  uint8 op0 = dreadb(pc.d); pc.w++;
+  uint8 op1 = dreadb(pc.d); pc.w++;
+  uint8 op2 = dreadb(pc.d);
+
+  #define op8  ((op0))
+  #define op16 ((op0) | (op1 << 8))
+  #define op24 ((op0) | (op1 << 8) | (op2 << 16))
+  #define a8   (regs.e || regs.p.m)
+  #define x8   (regs.e || regs.p.x)
+
+  switch(op) {
+    case 0x00: sprintf(t, "brk #$%.2x               ", op8); break;
+    case 0x01: sprintf(t, "ora ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x02: sprintf(t, "cop #$%.2x               ", op8); break;
+    case 0x03: sprintf(t, "ora $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x04: sprintf(t, "tsb $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x05: sprintf(t, "ora $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x06: sprintf(t, "asl $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x07: sprintf(t, "ora [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x08: sprintf(t, "php                    "); break;
+    case 0x09: if(a8)sprintf(t, "ora #$%.2x               ", op8);
+               else  sprintf(t, "ora #$%.4x             ", op16); break;
+    case 0x0a: sprintf(t, "asl a                  "); break;
+    case 0x0b: sprintf(t, "phd                    "); break;
+    case 0x0c: sprintf(t, "tsb $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x0d: sprintf(t, "ora $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x0e: sprintf(t, "asl $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x0f: sprintf(t, "ora $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x10: sprintf(t, "bpl $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x11: sprintf(t, "ora ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x12: sprintf(t, "ora ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x13: sprintf(t, "ora ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x14: sprintf(t, "trb $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x15: sprintf(t, "ora $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x16: sprintf(t, "asl $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x17: sprintf(t, "ora [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x18: sprintf(t, "clc                    "); break;
+    case 0x19: sprintf(t, "ora $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x1a: sprintf(t, "inc                    "); break;
+    case 0x1b: sprintf(t, "tcs                    "); break;
+    case 0x1c: sprintf(t, "trb $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x1d: sprintf(t, "ora $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x1e: sprintf(t, "asl $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x1f: sprintf(t, "ora $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0x20: sprintf(t, "jsr $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR_PC, op16)); break;
+    case 0x21: sprintf(t, "and ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x22: sprintf(t, "jsl $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x23: sprintf(t, "and $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x24: sprintf(t, "bit $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x25: sprintf(t, "and $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x26: sprintf(t, "rol $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x27: sprintf(t, "and [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x28: sprintf(t, "plp                    "); break;
+    case 0x29: if(a8)sprintf(t, "and #$%.2x               ", op8);
+               else  sprintf(t, "and #$%.4x             ", op16); break;
+    case 0x2a: sprintf(t, "rol a                  "); break;
+    case 0x2b: sprintf(t, "pld                    "); break;
+    case 0x2c: sprintf(t, "bit $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x2d: sprintf(t, "and $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x2e: sprintf(t, "rol $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x2f: sprintf(t, "and $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x30: sprintf(t, "bmi $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x31: sprintf(t, "and ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x32: sprintf(t, "and ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x33: sprintf(t, "and ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x34: sprintf(t, "bit $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x35: sprintf(t, "and $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x36: sprintf(t, "rol $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x37: sprintf(t, "and [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x38: sprintf(t, "sec                    "); break;
+    case 0x39: sprintf(t, "and $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x3a: sprintf(t, "dec                    "); break;
+    case 0x3b: sprintf(t, "tsc                    "); break;
+    case 0x3c: sprintf(t, "bit $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x3d: sprintf(t, "and $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x3e: sprintf(t, "rol $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x3f: sprintf(t, "and $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0x40: sprintf(t, "rti                    "); break;
+    case 0x41: sprintf(t, "eor ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x42: sprintf(t, "wdm                    "); break;
+    case 0x43: sprintf(t, "eor $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x44: sprintf(t, "mvp $%.2x,$%.2x            ", op1, op8); break;
+    case 0x45: sprintf(t, "eor $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x46: sprintf(t, "lsr $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x47: sprintf(t, "eor [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x48: sprintf(t, "pha                    "); break;
+    case 0x49: if(a8)sprintf(t, "eor #$%.2x               ", op8);
+               else  sprintf(t, "eor #$%.4x             ", op16); break;
+    case 0x4a: sprintf(t, "lsr a                  "); break;
+    case 0x4b: sprintf(t, "phk                    "); break;
+    case 0x4c: sprintf(t, "jmp $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR_PC, op16)); break;
+    case 0x4d: sprintf(t, "eor $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x4e: sprintf(t, "lsr $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x4f: sprintf(t, "eor $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x50: sprintf(t, "bvc $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x51: sprintf(t, "eor ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x52: sprintf(t, "eor ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x53: sprintf(t, "eor ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x54: sprintf(t, "mvn $%.2x,$%.2x            ", op1, op8); break;
+    case 0x55: sprintf(t, "eor $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x56: sprintf(t, "lsr $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x57: sprintf(t, "eor [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x58: sprintf(t, "cli                    "); break;
+    case 0x59: sprintf(t, "eor $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x5a: sprintf(t, "phy                    "); break;
+    case 0x5b: sprintf(t, "tcd                    "); break;
+    case 0x5c: sprintf(t, "jml $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x5d: sprintf(t, "eor $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x5e: sprintf(t, "lsr $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x5f: sprintf(t, "eor $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0x60: sprintf(t, "rts                    "); break;
+    case 0x61: sprintf(t, "adc ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x62: sprintf(t, "per $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x63: sprintf(t, "adc $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x64: sprintf(t, "stz $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x65: sprintf(t, "adc $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x66: sprintf(t, "ror $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x67: sprintf(t, "adc [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x68: sprintf(t, "pla                    "); break;
+    case 0x69: if(a8)sprintf(t, "adc #$%.2x               ", op8);
+               else  sprintf(t, "adc #$%.4x             ", op16); break;
+    case 0x6a: sprintf(t, "ror a                  "); break;
+    case 0x6b: sprintf(t, "rtl                    "); break;
+    case 0x6c: sprintf(t, "jmp ($%.4x)   [$%.6x]", op16, decode(OPTYPE_IADDR_PC, op16)); break;
+    case 0x6d: sprintf(t, "adc $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x6e: sprintf(t, "ror $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x6f: sprintf(t, "adc $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x70: sprintf(t, "bvs $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x71: sprintf(t, "adc ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x72: sprintf(t, "adc ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x73: sprintf(t, "adc ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x74: sprintf(t, "stz $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x75: sprintf(t, "adc $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x76: sprintf(t, "ror $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x77: sprintf(t, "adc [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x78: sprintf(t, "sei                    "); break;
+    case 0x79: sprintf(t, "adc $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x7a: sprintf(t, "ply                    "); break;
+    case 0x7b: sprintf(t, "tdc                    "); break;
+    case 0x7c: sprintf(t, "jmp ($%.4x,x) [$%.6x]", op16, decode(OPTYPE_IADDRX, op16)); break;
+    case 0x7d: sprintf(t, "adc $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x7e: sprintf(t, "ror $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x7f: sprintf(t, "adc $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0x80: sprintf(t, "bra $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x81: sprintf(t, "sta ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x82: sprintf(t, "brl $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELW, op16)), decode(OPTYPE_RELW, op16)); break;
+    case 0x83: sprintf(t, "sta $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x84: sprintf(t, "sty $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x85: sprintf(t, "sta $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x86: sprintf(t, "stx $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x87: sprintf(t, "sta [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x88: sprintf(t, "dey                    "); break;
+    case 0x89: if(a8)sprintf(t, "bit #$%.2x               ", op8);
+               else  sprintf(t, "bit #$%.4x             ", op16); break;
+    case 0x8a: sprintf(t, "txa                    "); break;
+    case 0x8b: sprintf(t, "phb                    "); break;
+    case 0x8c: sprintf(t, "sty $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x8d: sprintf(t, "sta $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x8e: sprintf(t, "stx $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x8f: sprintf(t, "sta $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x90: sprintf(t, "bcc $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x91: sprintf(t, "sta ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x92: sprintf(t, "sta ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x93: sprintf(t, "sta ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x94: sprintf(t, "sty $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x95: sprintf(t, "sta $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x96: sprintf(t, "stx $%.2x,y     [$%.6x]", op8, decode(OPTYPE_DPY, op8)); break;
+    case 0x97: sprintf(t, "sta [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x98: sprintf(t, "tya                    "); break;
+    case 0x99: sprintf(t, "sta $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x9a: sprintf(t, "txs                    "); break;
+    case 0x9b: sprintf(t, "txy                    "); break;
+    case 0x9c: sprintf(t, "stz $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x9d: sprintf(t, "sta $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x9e: sprintf(t, "stz $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x9f: sprintf(t, "sta $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0xa0: if(x8)sprintf(t, "ldy #$%.2x               ", op8);
+               else  sprintf(t, "ldy #$%.4x             ", op16); break;
+    case 0xa1: sprintf(t, "lda ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0xa2: if(x8)sprintf(t, "ldx #$%.2x               ", op8);
+               else  sprintf(t, "ldx #$%.4x             ", op16); break;
+    case 0xa3: sprintf(t, "lda $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0xa4: sprintf(t, "ldy $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xa5: sprintf(t, "lda $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xa6: sprintf(t, "ldx $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xa7: sprintf(t, "lda [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0xa8: sprintf(t, "tay                    "); break;
+    case 0xa9: if(a8)sprintf(t, "lda #$%.2x               ", op8);
+               else  sprintf(t, "lda #$%.4x             ", op16); break;
+    case 0xaa: sprintf(t, "tax                    "); break;
+    case 0xab: sprintf(t, "plb                    "); break;
+    case 0xac: sprintf(t, "ldy $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xad: sprintf(t, "lda $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xae: sprintf(t, "ldx $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xaf: sprintf(t, "lda $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0xb0: sprintf(t, "bcs $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0xb1: sprintf(t, "lda ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0xb2: sprintf(t, "lda ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0xb3: sprintf(t, "lda ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0xb4: sprintf(t, "ldy $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xb5: sprintf(t, "lda $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xb6: sprintf(t, "ldx $%.2x,y     [$%.6x]", op8, decode(OPTYPE_DPY, op8)); break;
+    case 0xb7: sprintf(t, "lda [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0xb8: sprintf(t, "clv                    "); break;
+    case 0xb9: sprintf(t, "lda $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0xba: sprintf(t, "tsx                    "); break;
+    case 0xbb: sprintf(t, "tyx                    "); break;
+    case 0xbc: sprintf(t, "ldy $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xbd: sprintf(t, "lda $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xbe: sprintf(t, "ldx $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0xbf: sprintf(t, "lda $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0xc0: if(x8)sprintf(t, "cpy #$%.2x               ", op8);
+               else  sprintf(t, "cpy #$%.4x             ", op16); break;
+    case 0xc1: sprintf(t, "cmp ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0xc2: sprintf(t, "rep #$%.2x               ", op8); break;
+    case 0xc3: sprintf(t, "cmp $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0xc4: sprintf(t, "cpy $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xc5: sprintf(t, "cmp $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xc6: sprintf(t, "dec $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xc7: sprintf(t, "cmp [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0xc8: sprintf(t, "iny                    "); break;
+    case 0xc9: if(a8)sprintf(t, "cmp #$%.2x               ", op8);
+               else  sprintf(t, "cmp #$%.4x             ", op16); break;
+    case 0xca: sprintf(t, "dex                    "); break;
+    case 0xcb: sprintf(t, "wai                    "); break;
+    case 0xcc: sprintf(t, "cpy $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xcd: sprintf(t, "cmp $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xce: sprintf(t, "dec $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xcf: sprintf(t, "cmp $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0xd0: sprintf(t, "bne $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0xd1: sprintf(t, "cmp ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0xd2: sprintf(t, "cmp ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0xd3: sprintf(t, "cmp ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0xd4: sprintf(t, "pei ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0xd5: sprintf(t, "cmp $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xd6: sprintf(t, "dec $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xd7: sprintf(t, "cmp [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0xd8: sprintf(t, "cld                    "); break;
+    case 0xd9: sprintf(t, "cmp $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0xda: sprintf(t, "phx                    "); break;
+    case 0xdb: sprintf(t, "stp                    "); break;
+    case 0xdc: sprintf(t, "jmp [$%.4x]   [$%.6x]", op16, decode(OPTYPE_ILADDR, op16)); break;
+    case 0xdd: sprintf(t, "cmp $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xde: sprintf(t, "dec $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xdf: sprintf(t, "cmp $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0xe0: if(x8)sprintf(t, "cpx #$%.2x               ", op8);
+               else  sprintf(t, "cpx #$%.4x             ", op16); break;
+    case 0xe1: sprintf(t, "sbc ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0xe2: sprintf(t, "sep #$%.2x               ", op8); break;
+    case 0xe3: sprintf(t, "sbc $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0xe4: sprintf(t, "cpx $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xe5: sprintf(t, "sbc $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xe6: sprintf(t, "inc $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xe7: sprintf(t, "sbc [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0xe8: sprintf(t, "inx                    "); break;
+    case 0xe9: if(a8)sprintf(t, "sbc #$%.2x               ", op8);
+               else  sprintf(t, "sbc #$%.4x             ", op16); break;
+    case 0xea: sprintf(t, "nop                    "); break;
+    case 0xeb: sprintf(t, "xba                    "); break;
+    case 0xec: sprintf(t, "cpx $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xed: sprintf(t, "sbc $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xee: sprintf(t, "inc $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xef: sprintf(t, "sbc $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0xf0: sprintf(t, "beq $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0xf1: sprintf(t, "sbc ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0xf2: sprintf(t, "sbc ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0xf3: sprintf(t, "sbc ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0xf4: sprintf(t, "pea $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xf5: sprintf(t, "sbc $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xf6: sprintf(t, "inc $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xf7: sprintf(t, "sbc [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0xf8: sprintf(t, "sed                    "); break;
+    case 0xf9: sprintf(t, "sbc $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0xfa: sprintf(t, "plx                    "); break;
+    case 0xfb: sprintf(t, "xce                    "); break;
+    case 0xfc: sprintf(t, "jsr ($%.4x,x) [$%.6x]", op16, decode(OPTYPE_IADDRX, op16)); break;
+    case 0xfd: sprintf(t, "sbc $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xfe: sprintf(t, "inc $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xff: sprintf(t, "sbc $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+  }
+
+  #undef op8
+  #undef op16
+  #undef op24
+  #undef a8
+  #undef x8
+
+  strcat(s, t);
+  strcat(s, " ");
+
+  sprintf(t, "A:%.4x X:%.4x Y:%.4x S:%.4x D:%.4x DB:%.2x ",
+    regs.a.w, regs.x.w, regs.y.w, regs.s.w, regs.d.w, regs.db);
+  strcat(s, t);
+
+  if(regs.e) {
+    sprintf(t, "%c%c%c%c%c%c%c%c",
+      regs.p.n ? 'N' : 'n', regs.p.v ? 'V' : 'v',
+      regs.p.m ? '1' : '0', regs.p.x ? 'B' : 'b',
+      regs.p.d ? 'D' : 'd', regs.p.i ? 'I' : 'i',
+      regs.p.z ? 'Z' : 'z', regs.p.c ? 'C' : 'c');
+  } else {
+    sprintf(t, "%c%c%c%c%c%c%c%c",
+      regs.p.n ? 'N' : 'n', regs.p.v ? 'V' : 'v',
+      regs.p.m ? 'M' : 'm', regs.p.x ? 'X' : 'x',
+      regs.p.d ? 'D' : 'd', regs.p.i ? 'I' : 'i',
+      regs.p.z ? 'Z' : 'z', regs.p.c ? 'C' : 'c');
+  }
+
+  strcat(s, t);
+  strcat(s, " ");
+
+  sprintf(t, "V:%3d H:%4d", ppu.vcounter(), ppu.hcounter());
+  strcat(s, t);
+}
+
+//opcode_length() retrieves the length of the next opcode
+//to be executed. It is used by the debugger to step over,
+//disable and proceed cpu opcodes.
+//
+//5 and 6 are special cases, 5 is used for #consts based on
+//the A register size, 6 for the X/Y register size. the
+//rest are literal sizes. There's no need to test for
+//emulation mode, as regs.p.m/regs.p.x should *always* be
+//set in emulation mode.
+
+uint8 CPUcore::opcode_length() {
+  uint8 op, len;
+  static uint8 op_len_tbl[256] = {
+  //0,1,2,3,  4,5,6,7,  8,9,a,b,  c,d,e,f
+
+    2,2,2,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x0n
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0x1n
+    3,2,4,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x2n
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0x3n
+
+    1,2,2,2,  3,2,2,2,  1,5,1,1,  3,3,3,4, //0x4n
+    2,2,2,2,  3,2,2,2,  1,3,1,1,  4,3,3,4, //0x5n
+    1,2,3,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x6n
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0x7n
+
+    2,2,3,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x8n
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0x9n
+    6,2,6,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0xan
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0xbn
+
+    6,2,2,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0xcn
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0xdn
+    6,2,2,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0xen
+    2,2,2,2,  3,2,2,2,  1,3,1,1,  3,3,3,4  //0xfn
+  };
+
+  if(false /* in_opcode() == true */) {
+    return 0;
+  }
+
+  op  = dreadb(regs.pc.d);
+  len = op_len_tbl[op];
+  if(len == 5) return (regs.e || regs.p.m) ? 2 : 3;
+  if(len == 6) return (regs.e || regs.p.x) ? 2 : 3;
+  return len;
+}