mirror of
https://github.com/bsnes-emu/bsnes.git
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ba384a7c48
byuu says:
Changelog:
- emulator/interface: removed unused Region struct
- gba/cpu: optimized CPU::step() as much as I could for a slight
speedup¹
- gba/cpu: synchronize the APU better during FIFO updates
- higan/md, icarus: add automatic region detection; make it the
default option [hex\_usr]
- picks NTSC-J if there's more than one match ... eventually, this
will be a setting
- higan/md, icarus: support all three combinations of SRAM (8-bit low,
8-bit high, 16-bit)
- processor/arm7tdmi: fix bug when changing to THUMB mode via MSR
[MerryMage]
- tomoko: redesigned crash detector to only occur once for all three
ruby drivers
- this will reduce disk thrashing since the configuration file
only needs to be written out one extra time
- technically, it's twice ... but we should've always been writing
one out on first run in case it crashes then
- tomoko: defaulted back to the safest ruby drivers, given the optimal
drivers have some stability concerns
¹: minor errata: spotted a typo saying `synchronize(cpu)` when the CPU
is stopped, instead of `synchronize(ppu)`. This will be fixed in the v104
official 7zip archives.
I'm kind of rushing here but, it's really good timing for me to push out
a new official release. The blocking issues are resolved or close to it,
and we need lots of testing of the new major changes.
I'm going to consider this a semi-stable testing release and leave links
to v103 just in case.
77 lines
1.8 KiB
C++
77 lines
1.8 KiB
C++
auto CPU::DMA::run() -> bool {
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if(!active || waiting) return false;
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transfer();
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if(irq) cpu.irq.flag |= CPU::Interrupt::DMA0 << id;
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if(drq && id == 3) cpu.irq.flag |= CPU::Interrupt::Cartridge;
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return true;
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}
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auto CPU::DMA::transfer() -> void {
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uint seek = size ? 4 : 2;
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uint mode = size ? Word : Half;
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mode |= latch.length == length ? Nonsequential : Sequential;
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if(mode & Nonsequential) {
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if((source & 0x0800'0000) && (target & 0x0800'0000)) {
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//ROM -> ROM transfer
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} else {
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cpu.idle();
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cpu.idle();
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}
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}
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if(latch.source < 0x0200'0000) {
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cpu.idle(); //cannot access BIOS
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} else {
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uint32 addr = latch.source;
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if(mode & Word) addr &= ~3;
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if(mode & Half) addr &= ~1;
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data = cpu.get(mode, addr);
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}
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if(latch.target < 0x0200'0000) {
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cpu.idle(); //cannot access BIOS
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} else {
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uint32 addr = latch.target;
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if(mode & Word) addr &= ~3;
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if(mode & Half) addr &= ~1;
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cpu.set(mode, addr, data);
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}
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switch(sourceMode) {
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case 0: latch.source += seek; break;
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case 1: latch.source -= seek; break;
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}
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switch(targetMode) {
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case 0: latch.target += seek; break;
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case 1: latch.target -= seek; break;
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case 3: latch.target += seek; break;
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}
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if(--latch.length == 0) {
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active = false;
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if(targetMode == 3) latch.target = target;
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if(repeat == 1) latch.length = length;
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if(repeat == 0) enable = false;
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}
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}
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auto CPU::dmaVblank() -> void {
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for(auto& dma : this->dma) {
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if(dma.enable && dma.timingMode == 1) dma.active = true;
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}
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}
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auto CPU::dmaHblank() -> void {
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for(auto& dma : this->dma) {
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if(dma.enable && dma.timingMode == 2) dma.active = true;
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}
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}
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auto CPU::dmaHDMA() -> void {
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auto& dma = this->dma[3];
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if(dma.enable && dma.timingMode == 3) dma.active = true;
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}
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