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16f736307e
byuu says:
Changelog:
- processor/spc700: restored fetch/load/store/pull/push shorthand
functions
- processor/spc700: split functions that tested the algorithm used (`op
!= &SPC700:...`) to separate instructions
- mostly for code clarity over code size: it was awkward having
cycle counts change based on a function parameter
- processor/spc700: implemented Overload's new findings on which
cycles are truly internal (no bus reads)
- sfc/smp: TEST register emulation has been vastly improved¹
¹: it turns out that TEST.d4,d5 is the external clock divider (used
when accessing RAM through the DSP), and TEST.d6,d7 is the internal
clock divider (used when accessing IPLROM, IO registers, or during idle
cycles.)
The DSP (24576khz) feeds its clock / 12 through to the SMP (2048khz).
The clock divider setting further divides the clock by 2, 4, 8, or 16.
Since 8 and 16 are not cleanly divislbe by 12, the SMP cycle count
glitches out and seems to take 10 and 2 clocks instead of 8 or 16. This
can on real hardware either cause the SMP to run very slowly, or more
likely, crash the SMP completely until reset.
What's even stranger is the timers aren't affected by this. They still
clock by 2, 4, 8, or 16.
Note that technically I could divide my own clock counters by 24 and
reduce these to {1,2,5,10} and {1,2,4,8}, I instead chose to divide by
12 to better illustrate this hardware issue and better model that the
SMP clock runs at 2048khz and not 1024khz.
Further, note that things aren't 100% perfect yet. This seems to throw
off some tests, such as blargg's `test_timer_speed`. I can't tell how
far off I am because blargg's test tragically doesn't print out fail
values. But you can see the improvements in that higan is now passing
all of Revenant's tests that were obviously completely wrong before.
95 lines
1.8 KiB
C++
95 lines
1.8 KiB
C++
//Sony CXP1100Q-1
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struct SMP : Processor::SPC700, Thread {
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uint8 iplrom[64];
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//smp.cpp
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auto synchronizing() const -> bool override;
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auto portRead(uint2 port) const -> uint8;
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auto portWrite(uint2 port, uint8 data) -> void;
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auto main() -> void;
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auto load(Markup::Node) -> bool;
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auto power() -> void;
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//serialization.cpp
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auto serialize(serializer&) -> void;
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private:
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struct IO {
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//timing
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uint clockCounter;
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uint dspCounter;
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//external
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uint8 apu0;
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uint8 apu1;
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uint8 apu2;
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uint8 apu3;
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//$00f0
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uint1 timersDisable;
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uint1 ramWritable;
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uint1 ramDisable;
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uint1 timersEnable;
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uint2 externalWaitStates;
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uint2 internalWaitStates;
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//$00f1
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bool iplromEnable;
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//$00f2
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uint8 dspAddr;
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//$00f4-00f7
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uint8 cpu0;
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uint8 cpu1;
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uint8 cpu2;
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uint8 cpu3;
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//$00f8-00f9
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uint8 aux4;
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uint8 aux5;
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} io;
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static auto Enter() -> void;
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//memory.cpp
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auto ramRead(uint16 addr) -> uint8;
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auto ramWrite(uint16 addr, uint8 data) -> void;
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auto busRead(uint16 addr) -> uint8;
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auto busWrite(uint16 addr, uint8 data) -> void;
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auto idle() -> void override;
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auto read(uint16 addr) -> uint8 override;
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auto write(uint16 addr, uint8 data) -> void override;
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auto readDisassembler(uint16 addr) -> uint8 override;
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//timing.cpp
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template<uint Frequency> struct Timer {
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uint8 stage0;
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uint8 stage1;
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uint8 stage2;
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uint4 stage3;
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bool line;
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bool enable;
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uint8 target;
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auto step(uint clocks) -> void;
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auto synchronizeStage1() -> void;
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};
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Timer<128> timer0;
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Timer<128> timer1;
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Timer< 16> timer2;
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inline auto wait(maybe<uint16> address = nothing) -> void;
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inline auto step(uint clocks) -> void;
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inline auto stepTimers(uint clocks) -> void;
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};
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extern SMP smp;
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