mirror of
https://github.com/bsnes-emu/bsnes.git
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310ff4fa3b
byuu says: This WIP does substantially better on endrift's GBA timing tests. Still not perfect, though. But hopefully enough to get me out of dead last place. I also finally fixed the THUMB-mode ldmia bug that jchadwick reported. So, GBA emulation should be improved quite a bit, hopefully.
117 lines
3.4 KiB
C++
117 lines
3.4 KiB
C++
#include <gba/gba.hpp>
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namespace GameBoyAdvance {
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#include "mmio.cpp"
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#include "serialization.cpp"
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Bus bus;
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struct UnmappedMemory : Memory {
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auto read(uint32 addr, uint32 size) -> uint32 { return 0; }
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auto write(uint32 addr, uint32 size, uint32 word) -> void {}
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};
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static UnmappedMemory unmappedMemory;
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auto Bus::mirror(uint32 addr, uint32 size) -> uint32 {
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uint32 base = 0;
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if(size) {
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uint32 mask = 1 << 27; //28-bit bus
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while(addr >= size) {
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while(!(addr & mask)) mask >>= 1;
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addr -= mask;
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if(size > mask) {
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size -= mask;
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base += mask;
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}
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mask >>= 1;
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}
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base += addr;
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}
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return base;
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}
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auto Bus::wait(uint32 addr, uint32 size) -> unsigned {
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switch(addr & 0x0f000000) {
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case 0x00000000: return 1;
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case 0x01000000: return 1;
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case 0x02000000: return (16 - cpu.regs.memory.control.ewramwait) * (size == Word ? 2 : 1);
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case 0x03000000: return 1;
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case 0x04000000: return 2;
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case 0x05000000: return 1 + (size == Word);
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case 0x06000000: return 1 + (size == Word);
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case 0x07000000: return 1;
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default: {
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unsigned n = cpu.regs.wait.control.nwait[addr >> 25 & 3];
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unsigned s = cpu.regs.wait.control.swait[addr >> 25 & 3];
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static unsigned timing[] = {5, 4, 3, 9};
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n = timing[n];
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switch(addr & 0x0e000000) {
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case 0x08000000: s = s ? 2 : 3; break;
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case 0x0a000000: s = s ? 2 : 5; break;
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case 0x0c000000: s = s ? 2 : 9; break;
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case 0x0e000000: s = n; break;
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}
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bool sequential = cpu.sequential();
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if((addr & 0x1fffe) == 0) sequential = false; //N cycle on 16-bit ROM crossing 128KB page boundary (RAM S==N)
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if(idleflag) sequential = false; //LDR/LDM interrupts instruction fetches
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unsigned clocks = sequential ? s : n;
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if(size == Word) clocks += s; //16-bit bus requires two transfers for words
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return clocks;
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}
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}
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}
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auto Bus::idle(uint32 addr) -> void {
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if(addr & 0x08000000) idleflag = true;
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}
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auto Bus::read(uint32 addr, uint32 size) -> uint32 {
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idleflag = false;
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if(addr & 0x08000000) return cartridge.read(addr, size);
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switch(addr >> 24 & 7) {
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case 0: return bios.read(addr, size);
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case 1: return bios.read(addr, size);
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case 2: return cpu.ewram_read(addr, size);
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case 3: return cpu.iwram_read(addr, size);
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case 4:
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if((addr & 0xfffffc00) == 0x04000000) return mmio[addr & 0x3ff]->read(addr, size);
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if((addr & 0xff00ffff) == 0x04000800) return ((MMIO&)cpu).read(0x04000800 | (addr & 3), size);
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return cpu.pipeline.fetch.instruction;
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case 5: return ppu.pram_read(addr, size);
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case 6: return ppu.vram_read(addr, size);
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case 7: return ppu.oam_read(addr, size);
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}
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}
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auto Bus::write(uint32 addr, uint32 size, uint32 word) -> void {
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idleflag = false;
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if(addr & 0x08000000) return cartridge.write(addr, size, word);
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switch(addr >> 24 & 7) {
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case 0: return;
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case 1: return;
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case 2: return cpu.ewram_write(addr, size, word);
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case 3: return cpu.iwram_write(addr, size, word);
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case 4:
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if((addr & 0xfffffc00) == 0x04000000) return mmio[addr & 0x3ff]->write(addr, size, word);
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if((addr & 0xff00ffff) == 0x04000800) return ((MMIO&)cpu).write(0x04000800 | (addr & 3), size, word);
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return;
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case 5: return ppu.pram_write(addr, size, word);
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case 6: return ppu.vram_write(addr, size, word);
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case 7: return ppu.oam_write(addr, size, word);
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}
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}
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auto Bus::power() -> void {
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for(unsigned n = 0; n < 0x400; n++) mmio[n] = &unmappedMemory;
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idleflag = false;
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}
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}
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