mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-02-23 22:52:34 +01:00
0b6f1df987
byuu says:
Changelog:
- hiro/windows: set dpiAware=false, fixes icarus window sizes relative
to higan window sizes
- higan, icarus, hiro, ruby: add support for high resolution displays
on macOS [ncbncb]
- processor/lr35902-legacy: removed
- processor/arm7tdmi: new processor core started; intended to one day
be a replacement for processor/arm
It will probably take several WIPs to get the new ARM core up and
running. It's the last processor rewrite. After this, all processor
cores will be up to date with all my current programming conventions.
86 lines
3.0 KiB
C++
86 lines
3.0 KiB
C++
auto CPU::sleep() -> void {
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prefetchStep(1);
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}
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auto CPU::get(uint mode, uint32 addr) -> uint32 {
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uint clocks = _wait(mode, addr);
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uint word = pipeline.fetch.instruction;
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if(addr >= 0x1000'0000) {
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prefetchStep(clocks);
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} else if(addr & 0x0800'0000) {
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if(mode & Prefetch && wait.prefetch) {
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prefetchSync(addr);
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word = prefetchRead();
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if(mode & Word) word |= prefetchRead() << 16;
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} else {
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if(!context.dmaActive) prefetchWait();
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step(clocks - 1);
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word = cartridge.read(mode, addr);
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step(1);
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}
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} else {
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prefetchStep(clocks - 1);
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if(addr < 0x0200'0000) word = bios.read(mode, addr);
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else if(addr < 0x0300'0000) word = readEWRAM(mode, addr);
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else if(addr < 0x0400'0000) word = readIWRAM(mode, addr);
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else if(addr >= 0x0700'0000) word = ppu.readOAM(mode, addr);
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else if(addr >= 0x0600'0000) word = ppu.readVRAM(mode, addr);
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else if(addr >= 0x0500'0000) word = ppu.readPRAM(mode, addr);
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else if((addr & 0xffff'fc00) == 0x0400'0000) word = bus.io[addr & 0x3ff]->readIO(mode, addr);
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else if((addr & 0xff00'ffff) == 0x0400'0800) word = ((IO*)this)->readIO(mode, 0x0400'0800 | (addr & 3));
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prefetchStep(1);
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}
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return word;
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}
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auto CPU::set(uint mode, uint32 addr, uint32 word) -> void {
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uint clocks = _wait(mode, addr);
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if(addr >= 0x1000'0000) {
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prefetchStep(clocks);
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} else if(addr & 0x0800'0000) {
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if(!context.dmaActive) prefetchWait();
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step(clocks);
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cartridge.write(mode, addr, word);
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} else {
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prefetchStep(clocks);
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if(addr < 0x0200'0000);
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else if(addr < 0x0300'0000) writeEWRAM(mode, addr, word);
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else if(addr < 0x0400'0000) writeIWRAM(mode, addr, word);
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else if(addr >= 0x0700'0000) ppu.writeOAM(mode, addr, word);
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else if(addr >= 0x0600'0000) ppu.writeVRAM(mode, addr, word);
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else if(addr >= 0x0500'0000) ppu.writePRAM(mode, addr, word);
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else if((addr & 0xffff'fc00) == 0x0400'0000) bus.io[addr & 0x3ff]->writeIO(mode, addr, word);
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else if((addr & 0xff00'ffff) == 0x0400'0800) ((IO*)this)->writeIO(mode, 0x0400'0800 | (addr & 3), word);
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}
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}
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auto CPU::_wait(uint mode, uint32 addr) -> uint {
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if(addr >= 0x1000'0000) return 1; //unmapped
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if(addr < 0x0200'0000) return 1;
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if(addr < 0x0300'0000) return (16 - memory.ewramWait) * (mode & Word ? 2 : 1);
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if(addr < 0x0500'0000) return 1;
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if(addr < 0x0700'0000) return mode & Word ? 2 : 1;
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if(addr < 0x0800'0000) return 1;
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static uint timings[] = {5, 4, 3, 9};
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uint n = timings[wait.nwait[addr >> 25 & 3]];
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uint s = wait.swait[addr >> 25 & 3];
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switch(addr & 0x0e00'0000) {
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case 0x0800'0000: s = s ? 2 : 3; break;
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case 0x0a00'0000: s = s ? 2 : 5; break;
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case 0x0c00'0000: s = s ? 2 : 9; break;
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case 0x0e00'0000: s = n; break;
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}
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bool sequential = (mode & Sequential);
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if((addr & 0x1fffe) == 0) sequential = false; //N cycle on 16-bit ROM crossing 128KB page boundary (RAM S==N)
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uint clocks = sequential ? s : n;
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if(mode & Word) clocks += s; //16-bit bus requires two transfers for words
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return clocks;
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}
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