mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-02-24 07:02:27 +01:00
55f19c3e0d
byuu says:
Changelog:
- Master System: merged Bus into CPU
- Mega Drive: merged BusCPU into CPU; BusAPU into AU
- Mega Drive: added TMSS emulation; disabled by default [hex\_usr]
- VDP lockout not yet emulated
- processor/arm7tdmi: renamed interrupt() to exception()
- processor/arm7tdmi: CPSR.F (FIQ disable) flag is set on reset
- processor/arm7tdmi: pipeline decode stage caches CPSR.T (THUMB mode)
[MerryMage]
- fixes `msr_tests.gba` test F
- processor/arm7tdmi/disassembler: add PC address to left of currently
executing instruction
- processor/arm7tdmi: stop forcing CPSR.M (mode flags) bit 4 high (I
don't know what really happens here)
- processor/arm7tdmi: undefined instructions now generate Undefined
0x4 exception
- processor/arm7tdmi: thumbInstructionAddRegister masks PC by &~3
instead of &~2
- hopefully this is correct; &~2 felt very wrong
- processor/arm7tdmi: thumbInstructionStackMultiple can use sequential
timing for PC/LR PUSH/POP [Cydrak]
- systems/Mega Drive.sys: added tmss.rom; enable with cpu version=1
- tomoko: detect when a ruby video/audio/input driver crashes higan;
disable it on next program startup
v104 blockers:
- Mega Drive: support 8-bit SRAM (even if we don't support 16-bit;
don't force 8-bit to 16-bit)
- Mega Drive: add region detection support to icarus
- ruby: add default audio device information so certain drivers won't
default to silence out of the box
99 lines
2.3 KiB
C++
99 lines
2.3 KiB
C++
#include <md/md.hpp>
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namespace MegaDrive {
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CPU cpu;
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#include "bus.cpp"
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#include "serialization.cpp"
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auto CPU::Enter() -> void {
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while(true) scheduler.synchronize(), cpu.main();
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}
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auto CPU::main() -> void {
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if(state.interruptPending) {
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if(state.interruptPending.bit((uint)Interrupt::Reset)) {
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state.interruptPending.bit((uint)Interrupt::Reset) = 0;
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r.a[7] = bus->readWord(0) << 16 | bus->readWord(2) << 0;
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r.pc = bus->readWord(4) << 16 | bus->readWord(6) << 0;
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}
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if(state.interruptPending.bit((uint)Interrupt::HorizontalBlank)) {
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if(4 > r.i) {
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state.interruptPending.bit((uint)Interrupt::HorizontalBlank) = 0;
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return exception(Exception::Interrupt, Vector::HorizontalBlank, 4);
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}
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}
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if(state.interruptPending.bit((uint)Interrupt::VerticalBlank)) {
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if(6 > r.i) {
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state.interruptPending.bit((uint)Interrupt::VerticalBlank) = 0;
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return exception(Exception::Interrupt, Vector::VerticalBlank, 6);
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}
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}
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}
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instruction();
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}
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auto CPU::step(uint clocks) -> void {
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while(wait) {
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Thread::step(1);
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synchronize();
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}
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Thread::step(clocks);
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synchronize();
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}
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auto CPU::synchronize() -> void {
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synchronize(apu);
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synchronize(vdp);
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synchronize(psg);
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synchronize(ym2612);
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for(auto peripheral : peripherals) synchronize(*peripheral);
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}
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auto CPU::raise(Interrupt interrupt) -> void {
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if(!state.interruptLine.bit((uint)interrupt)) {
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state.interruptLine.bit((uint)interrupt) = 1;
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state.interruptPending.bit((uint)interrupt) = 1;
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}
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}
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auto CPU::lower(Interrupt interrupt) -> void {
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state.interruptLine.bit((uint)interrupt) = 0;
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state.interruptPending.bit((uint)interrupt) = 0;
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}
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auto CPU::load(Markup::Node node) -> bool {
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tmssEnable = false;
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if(node["cpu/version"].natural() == 1) {
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if(auto name = node["cpu/rom/name"].text()) {
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if(auto fp = platform->open(ID::System, name, File::Read, File::Required)) {
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fp->read(tmss, 2 * 1024);
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tmssEnable = true;
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}
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}
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}
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return true;
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}
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auto CPU::power() -> void {
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M68K::bus = this;
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M68K::power();
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create(CPU::Enter, system.frequency() / 7.0);
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io = {};
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io.version = tmssEnable;
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io.romEnable = !tmssEnable;
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io.vdpEnable[0] = !tmssEnable;
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io.vdpEnable[1] = !tmssEnable;
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state = {};
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state.interruptPending.bit((uint)Interrupt::Reset) = 1;
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}
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}
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