mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-02-24 15:12:23 +01:00
4c9266d18f
byuu says:
Small WIP, just fixes the timings for GSU multiply.
However, the actual product may still be wrong when CLSR and MS0 are
both set. Since I wasn't 'corrupting' the value in said case before,
then this behavior can only be better than before.
Turned the (cache,memory)_access_timing into functions that compute the
values; and pulled "clockspeed" into GSU.
Also, I'm thinking it might be kind of pointless to have clockspeed at
all. Supposedly even the Mario Chip can run at 21.48MHz anyway.
Enforcing 10.74MHz mode seems kind of silly. If we change it to just be
a "default value for CLSR", then we can just inline the memory access
tests without the need for the access_timing functions (literally just
clsr?2:1 then)
Slight compilation bug: go to processor/gsu/registers.hpp:33 and add
reg16_t() = default;
I missed it due to a partial recompile. Too lazy to upload another WIP
just for that.
Probably not worth doing much SuperFX testing just yet, as it looks like
they're doing some other tests at the moment on NESdev.
282 lines
12 KiB
C++
282 lines
12 KiB
C++
#ifdef SUPERFX_CPP
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//TODO: this belongs in processor/gsu
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auto SuperFX::disassemble_opcode(char* output) -> void {
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*output = 0;
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if(!regs.sfr.alt2) {
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if(!regs.sfr.alt1) {
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disassemble_alt0(output);
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} else {
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disassemble_alt1(output);
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}
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} else {
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if(!regs.sfr.alt1) {
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disassemble_alt2(output);
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} else {
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disassemble_alt3(output);
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}
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}
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unsigned length = strlen(output);
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while(length++ < 20) strcat(output, " ");
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}
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#define case4(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3
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#define case6(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5
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#define case12(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
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case id+ 8: case id+ 9: case id+10: case id+11
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#define case15(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
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case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14
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#define case16(id) \
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case id+ 0: case id+ 1: case id+ 2: case id+ 3: case id+ 4: case id+ 5: case id+ 6: case id+ 7: \
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case id+ 8: case id+ 9: case id+10: case id+11: case id+12: case id+13: case id+14: case id+15
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#define op0 regs.pipeline
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#define op1 bus_read((regs.pbr << 16) + regs.r[15] + 0)
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#define op2 bus_read((regs.pbr << 16) + regs.r[15] + 1)
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auto SuperFX::disassemble_alt0(char* output) -> void {
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char t[256] = "";
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switch(op0) {
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case (0x00): sprintf(t, "stop"); break;
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case (0x01): sprintf(t, "nop"); break;
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case (0x02): sprintf(t, "cache"); break;
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case (0x03): sprintf(t, "lsr"); break;
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case (0x04): sprintf(t, "rol"); break;
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case (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
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case (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
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case (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
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case (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
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case (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
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case (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
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case (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
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case (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
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case (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
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case (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
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case (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
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case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
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case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
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case12(0x30): sprintf(t, "stw (r%u)", op0 & 15); break;
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case (0x3c): sprintf(t, "loop"); break;
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case (0x3d): sprintf(t, "alt1"); break;
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case (0x3e): sprintf(t, "alt2"); break;
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case (0x3f): sprintf(t, "alt3"); break;
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case12(0x40): sprintf(t, "ldw (r%u)", op0 & 15); break;
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case (0x4c): sprintf(t, "plot"); break;
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case (0x4d): sprintf(t, "swap"); break;
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case (0x4e): sprintf(t, "color"); break;
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case (0x4f): sprintf(t, "not"); break;
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case16(0x50): sprintf(t, "add r%u", op0 & 15); break;
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case16(0x60): sprintf(t, "sub r%u", op0 & 15); break;
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case (0x70): sprintf(t, "merge"); break;
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case15(0x71): sprintf(t, "and r%u", op0 & 15); break;
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case16(0x80): sprintf(t, "mult r%u", op0 & 15); break;
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case (0x90): sprintf(t, "sbk"); break;
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case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
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case (0x95): sprintf(t, "sex"); break;
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case (0x96): sprintf(t, "asr"); break;
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case (0x97): sprintf(t, "ror"); break;
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case6 (0x98): sprintf(t, "jmp r%u", op0 & 15); break;
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case (0x9e): sprintf(t, "lob"); break;
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case (0x9f): sprintf(t, "fmult"); break;
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case16(0xa0): sprintf(t, "ibt r%u,#$%.2x", op0 & 15, op1); break;
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case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
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case (0xc0): sprintf(t, "hib"); break;
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case15(0xc1): sprintf(t, "or r%u", op0 & 15); break;
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case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
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case (0xdf): sprintf(t, "getc"); break;
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case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
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case (0xef): sprintf(t, "getb"); break;
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case16(0xf0): sprintf(t, "iwt r%u,#$%.2x%.2x", op0 & 15, op2, op1); break;
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}
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strcat(output, t);
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}
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auto SuperFX::disassemble_alt1(char* output) -> void {
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char t[256] = "";
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switch(op0) {
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case (0x00): sprintf(t, "stop"); break;
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case (0x01): sprintf(t, "nop"); break;
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case (0x02): sprintf(t, "cache"); break;
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case (0x03): sprintf(t, "lsr"); break;
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case (0x04): sprintf(t, "rol"); break;
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case (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
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case (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
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case (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
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case (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
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case (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
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case (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
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case (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
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case (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
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case (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
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case (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
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case (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
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case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
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case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
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case12(0x30): sprintf(t, "stb (r%u)", op0 & 15); break;
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case (0x3c): sprintf(t, "loop"); break;
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case (0x3d): sprintf(t, "alt1"); break;
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case (0x3e): sprintf(t, "alt2"); break;
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case (0x3f): sprintf(t, "alt3"); break;
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case12(0x40): sprintf(t, "ldb (r%u)", op0 & 15); break;
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case (0x4c): sprintf(t, "rpix"); break;
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case (0x4d): sprintf(t, "swap"); break;
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case (0x4e): sprintf(t, "cmode"); break;
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case (0x4f): sprintf(t, "not"); break;
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case16(0x50): sprintf(t, "adc r%u", op0 & 15); break;
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case16(0x60): sprintf(t, "sbc r%u", op0 & 15); break;
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case (0x70): sprintf(t, "merge"); break;
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case15(0x71): sprintf(t, "bic r%u", op0 & 15); break;
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case16(0x80): sprintf(t, "umult r%u", op0 & 15); break;
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case (0x90): sprintf(t, "sbk"); break;
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case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
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case (0x95): sprintf(t, "sex"); break;
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case (0x96): sprintf(t, "div2"); break;
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case (0x97): sprintf(t, "ror"); break;
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case6 (0x98): sprintf(t, "ljmp r%u", op0 & 15); break;
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case (0x9e): sprintf(t, "lob"); break;
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case (0x9f): sprintf(t, "lmult"); break;
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case16(0xa0): sprintf(t, "lms r%u,(#$%.4x)", op0 & 15, op1 << 1); break;
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case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
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case (0xc0): sprintf(t, "hib"); break;
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case15(0xc1): sprintf(t, "xor r%u", op0 & 15); break;
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case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
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case (0xdf): sprintf(t, "getc"); break;
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case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
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case (0xef): sprintf(t, "getbh"); break;
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case16(0xf0): sprintf(t, "lm r%u", op0 & 15); break;
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}
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strcat(output, t);
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}
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auto SuperFX::disassemble_alt2(char* output) -> void {
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char t[256] = "";
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switch(op0) {
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case (0x00): sprintf(t, "stop"); break;
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case (0x01): sprintf(t, "nop"); break;
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case (0x02): sprintf(t, "cache"); break;
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case (0x03): sprintf(t, "lsr"); break;
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case (0x04): sprintf(t, "rol"); break;
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case (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
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case (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
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case (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
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case (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
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case (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
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case (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
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case (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
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case (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
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case (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
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case (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
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case (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
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case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
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case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
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case12(0x30): sprintf(t, "stw (r%u)", op0 & 15); break;
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case (0x3c): sprintf(t, "loop"); break;
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case (0x3d): sprintf(t, "alt1"); break;
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case (0x3e): sprintf(t, "alt2"); break;
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case (0x3f): sprintf(t, "alt3"); break;
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case12(0x40): sprintf(t, "ldw (r%u)", op0 & 15); break;
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case (0x4c): sprintf(t, "plot"); break;
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case (0x4d): sprintf(t, "swap"); break;
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case (0x4e): sprintf(t, "color"); break;
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case (0x4f): sprintf(t, "not"); break;
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case16(0x50): sprintf(t, "add #%u", op0 & 15); break;
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case16(0x60): sprintf(t, "sub #%u", op0 & 15); break;
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case (0x70): sprintf(t, "merge"); break;
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case15(0x71): sprintf(t, "and #%u", op0 & 15); break;
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case16(0x80): sprintf(t, "mult #%u", op0 & 15); break;
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case (0x90): sprintf(t, "sbk"); break;
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case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
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case (0x95): sprintf(t, "sex"); break;
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case (0x96): sprintf(t, "asr"); break;
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case (0x97): sprintf(t, "ror"); break;
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case6 (0x98): sprintf(t, "jmp r%u", op0 & 15); break;
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case (0x9e): sprintf(t, "lob"); break;
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case (0x9f): sprintf(t, "fmult"); break;
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case16(0xa0): sprintf(t, "sms r%u,(#$%.4x)", op0 & 15, op1 << 1); break;
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case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
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case (0xc0): sprintf(t, "hib"); break;
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case15(0xc1): sprintf(t, "or #%u", op0 & 15); break;
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case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
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case (0xdf): sprintf(t, "ramb"); break;
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case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
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case (0xef): sprintf(t, "getbl"); break;
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case16(0xf0): sprintf(t, "sm r%u", op0 & 15); break;
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}
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strcat(output, t);
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}
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auto SuperFX::disassemble_alt3(char* output) -> void {
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char t[256] = "";
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switch(op0) {
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case (0x00): sprintf(t, "stop"); break;
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case (0x01): sprintf(t, "nop"); break;
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case (0x02): sprintf(t, "cache"); break;
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case (0x03): sprintf(t, "lsr"); break;
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case (0x04): sprintf(t, "rol"); break;
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case (0x05): sprintf(t, "bra %+d", (int8_t)op1); break;
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case (0x06): sprintf(t, "blt %+d", (int8_t)op1); break;
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case (0x07): sprintf(t, "bge %+d", (int8_t)op1); break;
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case (0x08): sprintf(t, "bne %+d", (int8_t)op1); break;
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case (0x09): sprintf(t, "beq %+d", (int8_t)op1); break;
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case (0x0a): sprintf(t, "bpl %+d", (int8_t)op1); break;
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case (0x0b): sprintf(t, "bmi %+d", (int8_t)op1); break;
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case (0x0c): sprintf(t, "bcc %+d", (int8_t)op1); break;
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case (0x0d): sprintf(t, "bcs %+d", (int8_t)op1); break;
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case (0x0e): sprintf(t, "bvc %+d", (int8_t)op1); break;
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case (0x0f): sprintf(t, "bvs %+d", (int8_t)op1); break;
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case16(0x10): sprintf(t, "to r%u", op0 & 15); break;
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case16(0x20): sprintf(t, "with r%u", op0 & 15); break;
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case12(0x30): sprintf(t, "stb (r%u)", op0 & 15); break;
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case (0x3c): sprintf(t, "loop"); break;
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case (0x3d): sprintf(t, "alt1"); break;
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case (0x3e): sprintf(t, "alt2"); break;
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case (0x3f): sprintf(t, "alt3"); break;
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case12(0x40): sprintf(t, "ldb (r%u)", op0 & 15); break;
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case (0x4c): sprintf(t, "rpix"); break;
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case (0x4d): sprintf(t, "swap"); break;
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case (0x4e): sprintf(t, "cmode"); break;
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case (0x4f): sprintf(t, "not"); break;
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case16(0x50): sprintf(t, "adc #%u", op0 & 15); break;
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case16(0x60): sprintf(t, "cmp r%u", op0 & 15); break;
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case (0x70): sprintf(t, "merge"); break;
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case15(0x71): sprintf(t, "bic #%u", op0 & 15); break;
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case16(0x80): sprintf(t, "umult #%u", op0 & 15); break;
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case (0x90): sprintf(t, "sbk"); break;
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case4 (0x91): sprintf(t, "link #%u", op0 & 15); break;
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case (0x95): sprintf(t, "sex"); break;
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case (0x96): sprintf(t, "div2"); break;
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case (0x97): sprintf(t, "ror"); break;
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case6 (0x98): sprintf(t, "ljmp r%u", op0 & 15); break;
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case (0x9e): sprintf(t, "lob"); break;
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case (0x9f): sprintf(t, "lmult"); break;
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case16(0xa0): sprintf(t, "lms r%u", op0 & 15); break;
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case16(0xb0): sprintf(t, "from r%u", op0 & 15); break;
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case (0xc0): sprintf(t, "hib"); break;
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case15(0xc1): sprintf(t, "xor #%u", op0 & 15); break;
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case15(0xd0): sprintf(t, "inc r%u", op0 & 15); break;
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case (0xdf): sprintf(t, "romb"); break;
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case15(0xe0): sprintf(t, "dec r%u", op0 & 15); break;
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case (0xef): sprintf(t, "getbs"); break;
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case16(0xf0): sprintf(t, "lm r%u", op0 & 15); break;
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}
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strcat(output, t);
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}
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#undef case4
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#undef case6
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#undef case12
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#undef case15
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#undef case16
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#undef op0
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#undef op1
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#undef op2
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#endif
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