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https://github.com/bsnes-emu/bsnes.git
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4c9266d18f
byuu says:
Small WIP, just fixes the timings for GSU multiply.
However, the actual product may still be wrong when CLSR and MS0 are
both set. Since I wasn't 'corrupting' the value in said case before,
then this behavior can only be better than before.
Turned the (cache,memory)_access_timing into functions that compute the
values; and pulled "clockspeed" into GSU.
Also, I'm thinking it might be kind of pointless to have clockspeed at
all. Supposedly even the Mario Chip can run at 21.48MHz anyway.
Enforcing 10.74MHz mode seems kind of silly. If we change it to just be
a "default value for CLSR", then we can just inline the memory access
tests without the need for the access_timing functions (literally just
clsr?2:1 then)
Slight compilation bug: go to processor/gsu/registers.hpp:33 and add
reg16_t() = default;
I missed it due to a partial recompile. Too lazy to upload another WIP
just for that.
Probably not worth doing much SuperFX testing just yet, as it looks like
they're doing some other tests at the moment on NESdev.
117 lines
1.9 KiB
C++
117 lines
1.9 KiB
C++
#ifdef SUPERFX_CPP
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auto SuperFX::mmio_read(unsigned addr) -> uint8 {
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cpu.synchronize_coprocessors();
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addr &= 0xffff;
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if(addr >= 0x3100 && addr <= 0x32ff) {
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return cache_mmio_read(addr - 0x3100);
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}
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if(addr >= 0x3000 && addr <= 0x301f) {
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return regs.r[(addr >> 1) & 15] >> ((addr & 1) << 3);
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}
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switch(addr) {
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case 0x3030: {
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return regs.sfr >> 0;
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}
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case 0x3031: {
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uint8 r = regs.sfr >> 8;
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regs.sfr.irq = 0;
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cpu.regs.irq = 0;
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return r;
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}
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case 0x3034: {
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return regs.pbr;
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}
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case 0x3036: {
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return regs.rombr;
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}
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case 0x303b: {
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return regs.vcr;
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}
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case 0x303c: {
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return regs.rambr;
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}
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case 0x303e: {
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return regs.cbr >> 0;
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}
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case 0x303f: {
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return regs.cbr >> 8;
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}
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}
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return 0x00;
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}
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auto SuperFX::mmio_write(unsigned addr, uint8 data) -> void {
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cpu.synchronize_coprocessors();
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addr &= 0xffff;
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if(addr >= 0x3100 && addr <= 0x32ff) {
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return cache_mmio_write(addr - 0x3100, data);
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}
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if(addr >= 0x3000 && addr <= 0x301f) {
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unsigned n = (addr >> 1) & 15;
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if((addr & 1) == 0) {
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regs.r[n] = (regs.r[n] & 0xff00) | data;
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} else {
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regs.r[n] = (data << 8) | (regs.r[n] & 0xff);
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}
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if(addr == 0x301f) regs.sfr.g = 1;
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return;
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}
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switch(addr) {
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case 0x3030: {
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bool g = regs.sfr.g;
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regs.sfr = (regs.sfr & 0xff00) | (data << 0);
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if(g == 1 && regs.sfr.g == 0) {
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regs.cbr = 0x0000;
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cache_flush();
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}
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} break;
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case 0x3031: {
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regs.sfr = (data << 8) | (regs.sfr & 0x00ff);
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} break;
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case 0x3033: {
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regs.bramr = data;
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} break;
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case 0x3034: {
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regs.pbr = data & 0x7f;
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cache_flush();
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} break;
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case 0x3037: {
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regs.cfgr = data;
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} break;
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case 0x3038: {
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regs.scbr = data;
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} break;
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case 0x3039: {
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regs.clsr = data;
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} break;
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case 0x303a: {
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regs.scmr = data;
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} break;
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}
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}
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#endif
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