mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-02-24 07:02:27 +01:00
4e2eb23835
byuu says: Changelog: - added Cocoa target: higan can now be compiled for OS X Lion [Cydrak, byuu] - SNES/accuracy profile hires color blending improvements - fixes Marvelous text [AWJ] - fixed a slight bug in SNES/SA-1 VBR support caused by a typo - added support for multi-pass shaders that can load external textures (requires OpenGL 3.2+) - added game library path (used by ananke->Import Game) to Settings->Advanced - system profiles, shaders and cheats database can be stored in "all users" shared folders now (eg /usr/share on Linux) - all configuration files are in BML format now, instead of XML (much easier to read and edit this way) - main window supports drag-and-drop of game folders (but not game files / ZIP archives) - audio buffer clears when entering a modal loop on Windows (prevents audio repetition with DirectSound driver) - a substantial amount of code clean-up (probably the biggest refactoring to date) One highly desired target for this release was to default to the optimal drivers instead of the safest drivers, but because AMD drivers don't seem to like my OpenGL 3.2 driver, I've decided to postpone that. AMD has too big a market share. Hopefully with v093 officially released, we can get some public input on what AMD doesn't like.
430 lines
11 KiB
C++
430 lines
11 KiB
C++
#ifdef PROCESSOR_ARM_HPP
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void ARM::thumb_step() {
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if(pipeline.reload) {
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pipeline.reload = false;
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r(15).data &= ~1;
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sequential() = false;
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pipeline.fetch.address = r(15) & ~1;
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pipeline.fetch.instruction = read(pipeline.fetch.address, Half);
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pipeline_step();
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}
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pipeline_step();
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if(processor.irqline && cpsr().i == 0) {
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vector(0x00000018, Processor::Mode::IRQ);
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r(14) += 2;
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return;
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}
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instructions++;
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if(trace) {
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print(disassemble_registers(), "\n");
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print(disassemble_thumb_instruction(pipeline.execute.address), "\n");
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}
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#define decode(pattern, execute) if( \
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(instruction() & std::integral_constant<uint32, bit::mask(pattern)>::value) \
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== std::integral_constant<uint32, bit::test(pattern)>::value \
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) return thumb_op_ ## execute()
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decode("0001 10?? ???? ????", adjust_register);
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decode("0001 11?? ???? ????", adjust_immediate);
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decode("000? ???? ???? ????", shift_immediate);
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decode("001? ???? ???? ????", immediate);
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decode("0100 00?? ???? ????", alu);
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decode("0100 0111 0??? ?---", branch_exchange);
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decode("0100 01?? ???? ????", alu_hi);
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decode("0100 1??? ???? ????", load_literal);
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decode("0101 ???? ???? ????", move_register_offset);
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decode("0110 ???? ???? ????", move_word_immediate);
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decode("0111 ???? ???? ????", move_byte_immediate);
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decode("1000 ???? ???? ????", move_half_immediate);
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decode("1001 ???? ???? ????", move_stack);
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decode("1010 ???? ???? ????", add_register_hi);
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decode("1011 0000 ???? ????", adjust_stack);
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decode("1011 ?10? ???? ????", stack_multiple);
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decode("1100 ???? ???? ????", move_multiple);
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decode("1101 1111 ???? ????", software_interrupt);
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decode("1101 ???? ???? ????", branch_conditional);
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decode("1110 0??? ???? ????", branch_short);
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decode("1111 0??? ???? ????", branch_long_prefix);
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decode("1111 1??? ???? ????", branch_long_suffix);
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#undef decode
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crash = true;
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}
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void ARM::thumb_opcode(uint4 opcode, uint4 d, uint4 m) {
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switch(opcode) {
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case 0: r(d) = bit(r(d) & r(m)); break; //AND
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case 1: r(d) = bit(r(d) ^ r(m)); break; //EOR
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case 2: r(d) = bit(lsl(r(d), r(m))); break; //LSL
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case 3: r(d) = bit(lsr(r(d), r(m))); break; //LSR
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case 4: r(d) = bit(asr(r(d), r(m))); break; //ASR
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case 5: r(d) = add(r(d), r(m), cpsr().c); break; //ADC
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case 6: r(d) = sub(r(d), r(m), cpsr().c); break; //SBC
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case 7: r(d) = bit(ror(r(d), r(m))); break; //ROR
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case 8: bit(r(d) & r(m)); break; //TST
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case 9: r(d) = sub(0, r(m), 1); break; //NEG
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case 10: sub(r(d), r(m), 1); break; //CMP
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case 11: add(r(d), r(m), 0); break; //CMN
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case 12: r(d) = bit(r(d) | r(m)); break; //ORR
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case 13: r(d) = mul(0, r(d), r(m)); break; //MUL
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case 14: r(d) = bit(r(d) & ~r(m)); break; //BIC
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case 15: r(d) = bit(~r(m)); break; //MVN
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}
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}
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//(add,sub) rd,rn,rm
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//0001 10om mmnn nddd
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//o = opcode
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//m = rm
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//n = rn
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//d = rd
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void ARM::thumb_op_adjust_register() {
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uint1 opcode = instruction() >> 9;
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uint3 m = instruction() >> 6;
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uint3 n = instruction() >> 3;
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uint3 d = instruction() >> 0;
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switch(opcode) {
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case 0: r(d) = add(r(n), r(m), 0); break;
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case 1: r(d) = sub(r(n), r(m), 1); break;
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}
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}
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//(add,sub) rd,rn,#immediate
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//0001 11oi iinn nddd
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//o = opcode
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//i = immediate
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//n = rn
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//d = rd
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void ARM::thumb_op_adjust_immediate() {
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uint1 opcode = instruction() >> 9;
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uint3 immediate = instruction() >> 6;
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uint3 n = instruction() >> 3;
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uint3 d = instruction() >> 0;
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switch(opcode) {
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case 0: r(d) = add(r(n), immediate, 0); break;
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case 1: r(d) = sub(r(n), immediate, 1); break;
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}
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}
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//(lsl,lsr,asr) rd,rm,#immediate
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//000o oiii iimm mddd
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//o = opcode
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//i = immediate
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//m = rm
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//d = rd
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void ARM::thumb_op_shift_immediate() {
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uint2 opcode = instruction() >> 11;
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uint5 immediate = instruction() >> 6;
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uint3 m = instruction() >> 3;
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uint3 d = instruction() >> 0;
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switch(opcode) {
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case 0: r(d) = bit(lsl(r(m), immediate)); break;
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case 1: r(d) = bit(lsr(r(m), immediate == 0 ? 32u : (unsigned)immediate)); break;
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case 2: r(d) = bit(asr(r(m), immediate == 0 ? 32u : (unsigned)immediate)); break;
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}
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}
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//(mov,cmp,add,sub) (rd,rn),#immediate
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//001o orrr iiii iiii
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//o = opcode
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//r = (rd,rn)
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//i = immediate
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void ARM::thumb_op_immediate() {
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uint2 opcode = instruction() >> 11;
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uint3 d = instruction() >> 8;
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uint8 immediate = instruction();
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switch(opcode) {
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case 0: r(d) = bit( immediate ); break;
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case 1: sub(r(d), immediate, 1); break;
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case 2: r(d) = add(r(d), immediate, 0); break;
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case 3: r(d) = sub(r(d), immediate, 1); break;
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}
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}
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//{opcode} rd,rm
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//0100 00oo oomm mddd
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//o = opcode
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//m = rm
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//d = rd
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void ARM::thumb_op_alu() {
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uint4 opcode = instruction() >> 6;
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uint3 m = instruction() >> 3;
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uint3 d = instruction();
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thumb_opcode(opcode, d, m);
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}
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//bx rm
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//0100 0111 0mmm m---
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//m = rm
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void ARM::thumb_op_branch_exchange() {
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uint4 m = instruction() >> 3;
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cpsr().t = r(m) & 1;
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r(15) = r(m);
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}
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//{opcode} rd,rm
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//0100 01oo DMmm mddd
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//o = opcode
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//M:m = rm
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//D:d = rd
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void ARM::thumb_op_alu_hi() {
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uint2 opcode = instruction() >> 8;
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uint4 m = instruction() >> 3;
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uint3 dl = instruction();
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uint1 dh = instruction() >> 7;
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uint4 d = (dh << 3) + (dl << 0);
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switch(opcode) {
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case 0: r(d) = r(d) + r(m); break; //ADD (does not modify flags)
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case 1: sub(r(d), r(m), 1); break; //SUB
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case 2: r(d) = r(m); break; //MOV (does not modify flags)
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}
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}
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//ldr rd,[pc,#+/-offset]
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//0100 1ddd oooo oooo
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//d = rd
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//o = offset
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void ARM::thumb_op_load_literal() {
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uint3 d = instruction() >> 8;
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uint8 displacement = instruction();
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unsigned rm = (r(15) & ~3) + displacement * 4;
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r(d) = load(rm, Word);
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}
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//(ld(r,s),str){b,h} rd,[rn,rm]
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//0101 ooom mmnn nddd
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//o = opcode
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//m = rm
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//n = rn
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//d = rd
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void ARM::thumb_op_move_register_offset() {
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uint3 opcode = instruction() >> 9;
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uint3 m = instruction() >> 6;
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uint3 n = instruction() >> 3;
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uint3 d = instruction() >> 0;
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switch(opcode) {
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case 0: store(r(n) + r(m), Word, r(d)); break; //STR
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case 1: store(r(n) + r(m), Half, r(d)); break; //STRH
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case 2: store(r(n) + r(m), Byte, r(d)); break; //STRB
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case 3: r(d) = (int8)load(r(n) + r(m), Byte); break; //LDSB
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case 4: r(d) = load(r(n) + r(m), Word); break; //LDR
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case 5: r(d) = load(r(n) + r(m), Half); break; //LDRH
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case 6: r(d) = load(r(n) + r(m), Byte); break; //LDRB
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case 7: r(d) = (int16)load(r(n) + r(m), Half); break; //LDSH
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}
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}
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//(ldr,str) rd,[rn,#offset]
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//0110 looo oonn nddd
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//l = load
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//o = offset
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//n = rn
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//d = rd
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void ARM::thumb_op_move_word_immediate() {
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uint1 l = instruction() >> 11;
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uint5 offset = instruction() >> 6;
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uint3 n = instruction() >> 3;
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uint3 d = instruction() >> 0;
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if(l == 1) r(d) = load(r(n) + offset * 4, Word);
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if(l == 0) store(r(n) + offset * 4, Word, r(d));
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}
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//(ldr,str)b rd,[rn,#offset]
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//0111 looo oonn nddd
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//l = load
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//o = offset
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//n = rn
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//d = rd
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void ARM::thumb_op_move_byte_immediate() {
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uint1 l = instruction() >> 11;
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uint5 offset = instruction() >> 6;
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uint3 n = instruction() >> 3;
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uint3 d = instruction() >> 0;
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if(l == 1) r(d) = load(r(n) + offset, Byte);
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if(l == 0) store(r(n) + offset, Byte, r(d));
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}
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//(ldr,str)h rd,[rn,#offset]
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//1000 looo oonn nddd
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//l = load
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//o = offset
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//n = rn
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//d = rd
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void ARM::thumb_op_move_half_immediate() {
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uint1 l = instruction() >> 11;
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uint5 offset = instruction() >> 6;
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uint3 n = instruction() >> 3;
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uint3 d = instruction() >> 0;
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if(l == 1) r(d) = load(r(n) + offset * 2, Half);
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if(l == 0) store(r(n) + offset * 2, Half, r(d));
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}
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//(ldr,str) rd,[sp,#immediate]
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//1001 oddd iiii iiii
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//l = load
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//d = rd
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//i = immediate
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void ARM::thumb_op_move_stack() {
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uint1 l = instruction() >> 11;
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uint3 d = instruction() >> 8;
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uint8 immediate = instruction();
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if(l == 1) r(d) = load(r(13) + immediate * 4, Word);
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if(l == 0) store(r(13) + immediate * 4, Word, r(d));
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}
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//add rd,{pc,sp},#immediate
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//1010 sddd iiii iiii
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//s = sp (0 = pc)
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//d = rd
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//i = immediate
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void ARM::thumb_op_add_register_hi() {
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uint1 sp = instruction() >> 11;
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uint3 d = instruction() >> 8;
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uint8 immediate = instruction();
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if(sp == 0) r(d) = (r(15) & ~2) + immediate * 4;
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if(sp == 1) r(d) = r(13) + immediate * 4;
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}
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//(add,sub) sp,#immediate
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//1011 0000 oiii iiii
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//o = opcode
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//i = immediate
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void ARM::thumb_op_adjust_stack() {
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uint1 opcode = instruction() >> 7;
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uint7 immediate = instruction();
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if(opcode == 0) r(13) += immediate * 4;
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if(opcode == 1) r(13) -= immediate * 4;
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}
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//push {r...{,lr}}
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//pop {r...{,pc}}
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//1011 o10r llll llll
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//o = opcode (0 = push, 1 = pop)
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//r = push lr -or- pop pc
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//l = register list
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void ARM::thumb_op_stack_multiple() {
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uint1 l = instruction() >> 11;
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uint1 branch = instruction() >> 8;
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uint8 list = instruction();
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uint32 sp = 0;
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if(l == 1) sp = r(13);
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if(l == 0) sp = r(13) - (bit::count(list) + branch) * 4;
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sequential() = false;
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for(unsigned m = 0; m < 8; m++) {
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if(list & (1 << m)) {
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if(l == 1) r(m) = read(sp, Word); //POP
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if(l == 0) write(sp, Word, r(m)); //PUSH
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sp += 4;
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}
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}
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if(branch) {
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//note: ARMv5+ POP sets cpsr().t
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if(l == 1) r(15) = read(sp, Word); //POP
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if(l == 0) write(sp, Word, r(14)); //PUSH
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sp += 4;
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}
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if(l == 1) idle();
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if(l == 1) r(13) += (bit::count(list) + branch) * 4;
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if(l == 0) r(13) -= (bit::count(list) + branch) * 4;
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}
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//(ldmia,stmia) rn!,{r...}
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//1100 lnnn llll llll
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//l = load (0 = save)
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//n = rn
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//l = register list
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void ARM::thumb_op_move_multiple() {
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uint1 l = instruction() >> 11;
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uint3 n = instruction() >> 8;
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uint8 list = instruction();
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sequential() = false;
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for(unsigned m = 0; m < 8; m++) {
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if(list & (1 << m)) {
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if(l == 1) r(m) = read(r(n), Word); //LDMIA
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if(l == 0) write(r(n), Word, r(m)); //STMIA
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r(n) += 4;
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}
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}
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if(l == 1) idle();
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}
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//swi #immediate
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//1101 1111 iiii iiii
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//i = immediate
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void ARM::thumb_op_software_interrupt() {
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uint8 immediate = instruction();
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vector(0x00000008, Processor::Mode::SVC);
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}
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//b{condition}
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//1101 cccc dddd dddd
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//c = condition
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//d = displacement
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void ARM::thumb_op_branch_conditional() {
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uint4 flagcondition = instruction() >> 8;
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int8 displacement = instruction();
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if(condition(flagcondition) == false) return;
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r(15) = r(15) + displacement * 2;
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}
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//b address
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//1110 0ooo oooo oooo
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//o = offset
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void ARM::thumb_op_branch_short() {
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int11 displacement = instruction();
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r(15) += displacement * 2;
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}
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//bl address
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//1111 0ooo oooo oooo
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//o = offset
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void ARM::thumb_op_branch_long_prefix() {
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int11 offsethi = instruction();
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r(14) = r(15) + ((offsethi * 2) << 11);
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}
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//bl address
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//1111 1ooo oooo oooo
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//o = offset
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void ARM::thumb_op_branch_long_suffix() {
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uint11 offsetlo = instruction();
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r(15) = r(14) + (offsetlo * 2);
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r(14) = pipeline.decode.address | 1;
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}
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#endif
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