mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-02-23 22:52:34 +01:00
83f684c66c
byuu says: Note: for Windows users, please go to nall/intrinsics.hpp line 60 and correct the typo from "DISPLAY_WINDOW" to "DISPLAY_WINDOWS" before compiling, otherwise things won't work at all. This will be a really major WIP for the core SNES emulation, so please test as thoroughly as possible. I rewrote the 65816 CPU core's dispatcher from a jump table to a switch table. This was so that I could pass class variables as parameters to opcodes without crazy theatrics. With that, I killed the regs.r[N] stuff, the flag_t operator|=, &=, ^= stuff, and all of the template versions of opcodes. I also removed some stupid pointless flag tests in xcn and pflag that would always be true. I sure hope that AWJ is happy with this; because this change was so that my flag assignments and branch tests won't need to build regs.P into a full 8-bit variable anymore. It does of course incur a slight performance hit when you pass in variables by-value to functions, but it should help with binary size (and thus cache) by reducing a lot of extra functions. (I know I could have used template parameters for some things even with a switch table, but chose not to for the aforementioned reasons.) Overall, it's about a ~1% speedup from the previous build. The CPU core instructions were never a bottleneck, but I did want to fix the P flag building stuff because that really was a dumb mistake v_v'
328 lines
7.0 KiB
C++
328 lines
7.0 KiB
C++
auto R65816::op_adc_b() {
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int result;
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if(!regs.p.d) {
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result = regs.a.l + rd.l + regs.p.c;
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} else {
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result = (regs.a.l & 0x0f) + (rd.l & 0x0f) + (regs.p.c << 0);
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if(result > 0x09) result += 0x06;
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regs.p.c = result > 0x0f;
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result = (regs.a.l & 0xf0) + (rd.l & 0xf0) + (regs.p.c << 4) + (result & 0x0f);
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}
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regs.p.v = ~(regs.a.l ^ rd.l) & (regs.a.l ^ result) & 0x80;
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if(regs.p.d && result > 0x9f) result += 0x60;
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regs.p.c = result > 0xff;
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regs.p.n = result & 0x80;
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regs.p.z = (uint8_t)result == 0;
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regs.a.l = result;
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}
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auto R65816::op_adc_w() {
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int result;
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if(!regs.p.d) {
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result = regs.a.w + rd.w + regs.p.c;
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} else {
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result = (regs.a.w & 0x000f) + (rd.w & 0x000f) + (regs.p.c << 0);
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if(result > 0x0009) result += 0x0006;
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regs.p.c = result > 0x000f;
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result = (regs.a.w & 0x00f0) + (rd.w & 0x00f0) + (regs.p.c << 4) + (result & 0x000f);
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if(result > 0x009f) result += 0x0060;
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regs.p.c = result > 0x00ff;
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result = (regs.a.w & 0x0f00) + (rd.w & 0x0f00) + (regs.p.c << 8) + (result & 0x00ff);
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if(result > 0x09ff) result += 0x0600;
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regs.p.c = result > 0x0fff;
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result = (regs.a.w & 0xf000) + (rd.w & 0xf000) + (regs.p.c << 12) + (result & 0x0fff);
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}
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regs.p.v = ~(regs.a.w ^ rd.w) & (regs.a.w ^ result) & 0x8000;
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if(regs.p.d && result > 0x9fff) result += 0x6000;
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regs.p.c = result > 0xffff;
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regs.p.n = result & 0x8000;
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regs.p.z = (uint16_t)result == 0;
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regs.a.w = result;
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}
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auto R65816::op_and_b() {
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regs.a.l &= rd.l;
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regs.p.n = regs.a.l & 0x80;
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regs.p.z = regs.a.l == 0;
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}
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auto R65816::op_and_w() {
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regs.a.w &= rd.w;
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regs.p.n = regs.a.w & 0x8000;
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regs.p.z = regs.a.w == 0;
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}
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auto R65816::op_bit_b() {
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regs.p.n = rd.l & 0x80;
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regs.p.v = rd.l & 0x40;
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regs.p.z = (rd.l & regs.a.l) == 0;
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}
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auto R65816::op_bit_w() {
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regs.p.n = rd.w & 0x8000;
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regs.p.v = rd.w & 0x4000;
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regs.p.z = (rd.w & regs.a.w) == 0;
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}
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auto R65816::op_cmp_b() {
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int r = regs.a.l - rd.l;
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regs.p.n = r & 0x80;
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regs.p.z = (uint8)r == 0;
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regs.p.c = r >= 0;
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}
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auto R65816::op_cmp_w() {
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int r = regs.a.w - rd.w;
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regs.p.n = r & 0x8000;
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regs.p.z = (uint16)r == 0;
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regs.p.c = r >= 0;
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}
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auto R65816::op_cpx_b() {
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int r = regs.x.l - rd.l;
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regs.p.n = r & 0x80;
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regs.p.z = (uint8)r == 0;
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regs.p.c = r >= 0;
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}
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auto R65816::op_cpx_w() {
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int r = regs.x.w - rd.w;
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regs.p.n = r & 0x8000;
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regs.p.z = (uint16)r == 0;
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regs.p.c = r >= 0;
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}
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auto R65816::op_cpy_b() {
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int r = regs.y.l - rd.l;
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regs.p.n = r & 0x80;
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regs.p.z = (uint8)r == 0;
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regs.p.c = r >= 0;
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}
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auto R65816::op_cpy_w() {
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int r = regs.y.w - rd.w;
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regs.p.n = r & 0x8000;
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regs.p.z = (uint16)r == 0;
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regs.p.c = r >= 0;
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}
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auto R65816::op_eor_b() {
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regs.a.l ^= rd.l;
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regs.p.n = regs.a.l & 0x80;
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regs.p.z = regs.a.l == 0;
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}
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auto R65816::op_eor_w() {
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regs.a.w ^= rd.w;
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regs.p.n = regs.a.w & 0x8000;
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regs.p.z = regs.a.w == 0;
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}
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auto R65816::op_lda_b() {
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regs.a.l = rd.l;
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regs.p.n = regs.a.l & 0x80;
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regs.p.z = regs.a.l == 0;
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}
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auto R65816::op_lda_w() {
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regs.a.w = rd.w;
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regs.p.n = regs.a.w & 0x8000;
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regs.p.z = regs.a.w == 0;
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}
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auto R65816::op_ldx_b() {
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regs.x.l = rd.l;
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regs.p.n = regs.x.l & 0x80;
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regs.p.z = regs.x.l == 0;
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}
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auto R65816::op_ldx_w() {
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regs.x.w = rd.w;
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regs.p.n = regs.x.w & 0x8000;
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regs.p.z = regs.x.w == 0;
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}
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auto R65816::op_ldy_b() {
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regs.y.l = rd.l;
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regs.p.n = regs.y.l & 0x80;
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regs.p.z = regs.y.l == 0;
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}
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auto R65816::op_ldy_w() {
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regs.y.w = rd.w;
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regs.p.n = regs.y.w & 0x8000;
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regs.p.z = regs.y.w == 0;
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}
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auto R65816::op_ora_b() {
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regs.a.l |= rd.l;
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regs.p.n = regs.a.l & 0x80;
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regs.p.z = regs.a.l == 0;
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}
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auto R65816::op_ora_w() {
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regs.a.w |= rd.w;
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regs.p.n = regs.a.w & 0x8000;
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regs.p.z = regs.a.w == 0;
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}
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auto R65816::op_sbc_b() {
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int result;
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rd.l ^= 0xff;
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if(!regs.p.d) {
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result = regs.a.l + rd.l + regs.p.c;
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} else {
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result = (regs.a.l & 0x0f) + (rd.l & 0x0f) + (regs.p.c << 0);
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if(result <= 0x0f) result -= 0x06;
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regs.p.c = result > 0x0f;
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result = (regs.a.l & 0xf0) + (rd.l & 0xf0) + (regs.p.c << 4) + (result & 0x0f);
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}
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regs.p.v = ~(regs.a.l ^ rd.l) & (regs.a.l ^ result) & 0x80;
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if(regs.p.d && result <= 0xff) result -= 0x60;
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regs.p.c = result > 0xff;
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regs.p.n = result & 0x80;
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regs.p.z = (uint8_t)result == 0;
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regs.a.l = result;
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}
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auto R65816::op_sbc_w() {
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int result;
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rd.w ^= 0xffff;
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if(!regs.p.d) {
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result = regs.a.w + rd.w + regs.p.c;
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} else {
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result = (regs.a.w & 0x000f) + (rd.w & 0x000f) + (regs.p.c << 0);
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if(result <= 0x000f) result -= 0x0006;
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regs.p.c = result > 0x000f;
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result = (regs.a.w & 0x00f0) + (rd.w & 0x00f0) + (regs.p.c << 4) + (result & 0x000f);
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if(result <= 0x00ff) result -= 0x0060;
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regs.p.c = result > 0x00ff;
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result = (regs.a.w & 0x0f00) + (rd.w & 0x0f00) + (regs.p.c << 8) + (result & 0x00ff);
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if(result <= 0x0fff) result -= 0x0600;
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regs.p.c = result > 0x0fff;
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result = (regs.a.w & 0xf000) + (rd.w & 0xf000) + (regs.p.c << 12) + (result & 0x0fff);
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}
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regs.p.v = ~(regs.a.w ^ rd.w) & (regs.a.w ^ result) & 0x8000;
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if(regs.p.d && result <= 0xffff) result -= 0x6000;
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regs.p.c = result > 0xffff;
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regs.p.n = result & 0x8000;
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regs.p.z = (uint16_t)result == 0;
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regs.a.w = result;
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}
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auto R65816::op_inc_b() {
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rd.l++;
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regs.p.n = rd.l & 0x80;
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regs.p.z = rd.l == 0;
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}
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auto R65816::op_inc_w() {
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rd.w++;
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regs.p.n = rd.w & 0x8000;
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regs.p.z = rd.w == 0;
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}
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auto R65816::op_dec_b() {
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rd.l--;
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regs.p.n = rd.l & 0x80;
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regs.p.z = rd.l == 0;
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}
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auto R65816::op_dec_w() {
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rd.w--;
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regs.p.n = rd.w & 0x8000;
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regs.p.z = rd.w == 0;
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}
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auto R65816::op_asl_b() {
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regs.p.c = rd.l & 0x80;
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rd.l <<= 1;
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regs.p.n = rd.l & 0x80;
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regs.p.z = rd.l == 0;
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}
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auto R65816::op_asl_w() {
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regs.p.c = rd.w & 0x8000;
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rd.w <<= 1;
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regs.p.n = rd.w & 0x8000;
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regs.p.z = rd.w == 0;
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}
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auto R65816::op_lsr_b() {
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regs.p.c = rd.l & 1;
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rd.l >>= 1;
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regs.p.n = rd.l & 0x80;
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regs.p.z = rd.l == 0;
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}
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auto R65816::op_lsr_w() {
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regs.p.c = rd.w & 1;
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rd.w >>= 1;
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regs.p.n = rd.w & 0x8000;
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regs.p.z = rd.w == 0;
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}
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auto R65816::op_rol_b() {
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unsigned carry = (unsigned)regs.p.c;
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regs.p.c = rd.l & 0x80;
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rd.l = (rd.l << 1) | carry;
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regs.p.n = rd.l & 0x80;
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regs.p.z = rd.l == 0;
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}
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auto R65816::op_rol_w() {
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unsigned carry = (unsigned)regs.p.c;
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regs.p.c = rd.w & 0x8000;
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rd.w = (rd.w << 1) | carry;
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regs.p.n = rd.w & 0x8000;
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regs.p.z = rd.w == 0;
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}
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auto R65816::op_ror_b() {
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unsigned carry = (unsigned)regs.p.c << 7;
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regs.p.c = rd.l & 1;
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rd.l = carry | (rd.l >> 1);
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regs.p.n = rd.l & 0x80;
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regs.p.z = rd.l == 0;
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}
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auto R65816::op_ror_w() {
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unsigned carry = (unsigned)regs.p.c << 15;
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regs.p.c = rd.w & 1;
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rd.w = carry | (rd.w >> 1);
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regs.p.n = rd.w & 0x8000;
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regs.p.z = rd.w == 0;
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}
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auto R65816::op_trb_b() {
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regs.p.z = (rd.l & regs.a.l) == 0;
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rd.l &= ~regs.a.l;
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}
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auto R65816::op_trb_w() {
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regs.p.z = (rd.w & regs.a.w) == 0;
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rd.w &= ~regs.a.w;
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}
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auto R65816::op_tsb_b() {
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regs.p.z = (rd.l & regs.a.l) == 0;
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rd.l |= regs.a.l;
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}
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auto R65816::op_tsb_w() {
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regs.p.z = (rd.w & regs.a.w) == 0;
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rd.w |= regs.a.w;
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}
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