mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-02-24 07:02:27 +01:00
4e2eb23835
byuu says: Changelog: - added Cocoa target: higan can now be compiled for OS X Lion [Cydrak, byuu] - SNES/accuracy profile hires color blending improvements - fixes Marvelous text [AWJ] - fixed a slight bug in SNES/SA-1 VBR support caused by a typo - added support for multi-pass shaders that can load external textures (requires OpenGL 3.2+) - added game library path (used by ananke->Import Game) to Settings->Advanced - system profiles, shaders and cheats database can be stored in "all users" shared folders now (eg /usr/share on Linux) - all configuration files are in BML format now, instead of XML (much easier to read and edit this way) - main window supports drag-and-drop of game folders (but not game files / ZIP archives) - audio buffer clears when entering a modal loop on Windows (prevents audio repetition with DirectSound driver) - a substantial amount of code clean-up (probably the biggest refactoring to date) One highly desired target for this release was to default to the optimal drivers instead of the safest drivers, but because AMD drivers don't seem to like my OpenGL 3.2 driver, I've decided to postpone that. AMD has too big a market share. Hopefully with v093 officially released, we can get some public input on what AMD doesn't like.
223 lines
7.4 KiB
C++
223 lines
7.4 KiB
C++
void uPD96050::exec() {
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uint24 opcode = programROM[regs.pc++];
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switch(opcode >> 22) {
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case 0: exec_op(opcode); break;
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case 1: exec_rt(opcode); break;
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case 2: exec_jp(opcode); break;
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case 3: exec_ld(opcode); break;
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}
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int32 result = (int32)regs.k * regs.l; //sign + 30-bit result
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regs.m = result >> 15; //store sign + top 15-bits
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regs.n = result << 1; //store low 15-bits + zero
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}
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void uPD96050::exec_op(uint24 opcode) {
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uint2 pselect = opcode >> 20; //P select
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uint4 alu = opcode >> 16; //ALU operation mode
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uint1 asl = opcode >> 15; //accumulator select
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uint2 dpl = opcode >> 13; //DP low modify
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uint4 dphm = opcode >> 9; //DP high XOR modify
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uint1 rpdcr = opcode >> 8; //RP decrement
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uint4 src = opcode >> 4; //move source
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uint4 dst = opcode >> 0; //move destination
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uint16 idb;
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switch(src) {
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case 0: idb = regs.trb; break;
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case 1: idb = regs.a; break;
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case 2: idb = regs.b; break;
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case 3: idb = regs.tr; break;
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case 4: idb = regs.dp; break;
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case 5: idb = regs.rp; break;
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case 6: idb = dataROM[regs.rp]; break;
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case 7: idb = 0x8000 - regs.flaga.s1; break;
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case 8: idb = regs.dr; regs.sr.rqm = 1; break;
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case 9: idb = regs.dr; break;
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case 10: idb = regs.sr; break;
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case 11: idb = regs.si; break; //MSB
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case 12: idb = regs.si; break; //LSB
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case 13: idb = regs.k; break;
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case 14: idb = regs.l; break;
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case 15: idb = dataRAM[regs.dp]; break;
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}
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if(alu) {
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uint16 p, q, r;
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Flag flag;
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bool c;
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switch(pselect) {
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case 0: p = dataRAM[regs.dp]; break;
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case 1: p = idb; break;
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case 2: p = regs.m; break;
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case 3: p = regs.n; break;
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}
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switch(asl) {
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case 0: q = regs.a; flag = regs.flaga; c = regs.flagb.c; break;
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case 1: q = regs.b; flag = regs.flagb; c = regs.flaga.c; break;
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}
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switch(alu) {
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case 1: r = q | p; break; //OR
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case 2: r = q & p; break; //AND
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case 3: r = q ^ p; break; //XOR
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case 4: r = q - p; break; //SUB
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case 5: r = q + p; break; //ADD
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case 6: r = q - p - c; break; //SBB
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case 7: r = q + p + c; break; //ADC
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case 8: r = q - 1; p = 1; break; //DEC
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case 9: r = q + 1; p = 1; break; //INC
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case 10: r = ~q; break; //CMP
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case 11: r = (q >> 1) | (q & 0x8000); break; //SHR1 (ASR)
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case 12: r = (q << 1) | c; break; //SHL1 (ROL)
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case 13: r = (q << 2) | 3; break; //SHL2
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case 14: r = (q << 4) | 15; break; //SHL4
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case 15: r = (q << 8) | (q >> 8); break; //XCHG
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}
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flag.s0 = (r & 0x8000);
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flag.z = (r == 0);
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switch(alu) {
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case 1: case 2: case 3: case 10: case 13: case 14: case 15: {
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flag.c = 0;
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flag.ov0 = 0;
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flag.ov1 = 0;
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break;
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}
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case 4: case 5: case 6: case 7: case 8: case 9: {
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if(alu & 1) {
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//addition
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flag.ov0 = (q ^ r) & ~(q ^ p) & 0x8000;
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flag.c = (r < q);
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} else {
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//subtraction
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flag.ov0 = (q ^ r) & (q ^ p) & 0x8000;
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flag.c = (r > q);
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}
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if(flag.ov0) {
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flag.s1 = flag.ov1 ^ !(r & 0x8000);
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flag.ov1 = !flag.ov1;
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}
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break;
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}
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case 11: {
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flag.c = q & 1;
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flag.ov0 = 0;
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flag.ov1 = 0;
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break;
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}
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case 12: {
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flag.c = q >> 15;
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flag.ov0 = 0;
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flag.ov1 = 0;
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break;
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}
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}
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switch(asl) {
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case 0: regs.a = r; regs.flaga = flag; break;
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case 1: regs.b = r; regs.flagb = flag; break;
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}
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}
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exec_ld((idb << 6) + dst);
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switch(dpl) {
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case 1: regs.dp = (regs.dp & 0xf0) + ((regs.dp + 1) & 0x0f); break; //DPINC
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case 2: regs.dp = (regs.dp & 0xf0) + ((regs.dp - 1) & 0x0f); break; //DPDEC
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case 3: regs.dp = (regs.dp & 0xf0); break; //DPCLR
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}
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regs.dp ^= dphm << 4;
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if(rpdcr) regs.rp--;
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}
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void uPD96050::exec_rt(uint24 opcode) {
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exec_op(opcode);
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regs.pc = regs.stack[--regs.sp];
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}
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void uPD96050::exec_jp(uint24 opcode) {
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uint9 brch = opcode >> 13; //branch
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uint11 na = opcode >> 2; //next address
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uint2 bank = opcode >> 0; //bank address
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uint14 jp = (regs.pc & 0x2000) | (bank << 11) | (na << 0);
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switch(brch) {
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case 0x000: regs.pc = regs.so; return; //JMPSO
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case 0x080: if(regs.flaga.c == 0) regs.pc = jp; return; //JNCA
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case 0x082: if(regs.flaga.c == 1) regs.pc = jp; return; //JCA
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case 0x084: if(regs.flagb.c == 0) regs.pc = jp; return; //JNCB
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case 0x086: if(regs.flagb.c == 1) regs.pc = jp; return; //JCB
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case 0x088: if(regs.flaga.z == 0) regs.pc = jp; return; //JNZA
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case 0x08a: if(regs.flaga.z == 1) regs.pc = jp; return; //JZA
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case 0x08c: if(regs.flagb.z == 0) regs.pc = jp; return; //JNZB
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case 0x08e: if(regs.flagb.z == 1) regs.pc = jp; return; //JZB
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case 0x090: if(regs.flaga.ov0 == 0) regs.pc = jp; return; //JNOVA0
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case 0x092: if(regs.flaga.ov0 == 1) regs.pc = jp; return; //JOVA0
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case 0x094: if(regs.flagb.ov0 == 0) regs.pc = jp; return; //JNOVB0
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case 0x096: if(regs.flagb.ov0 == 1) regs.pc = jp; return; //JOVB0
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case 0x098: if(regs.flaga.ov1 == 0) regs.pc = jp; return; //JNOVA1
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case 0x09a: if(regs.flaga.ov1 == 1) regs.pc = jp; return; //JOVA1
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case 0x09c: if(regs.flagb.ov1 == 0) regs.pc = jp; return; //JNOVB1
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case 0x09e: if(regs.flagb.ov1 == 1) regs.pc = jp; return; //JOVB1
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case 0x0a0: if(regs.flaga.s0 == 0) regs.pc = jp; return; //JNSA0
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case 0x0a2: if(regs.flaga.s0 == 1) regs.pc = jp; return; //JSA0
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case 0x0a4: if(regs.flagb.s0 == 0) regs.pc = jp; return; //JNSB0
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case 0x0a6: if(regs.flagb.s0 == 1) regs.pc = jp; return; //JSB0
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case 0x0a8: if(regs.flaga.s1 == 0) regs.pc = jp; return; //JNSA1
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case 0x0aa: if(regs.flaga.s1 == 1) regs.pc = jp; return; //JSA1
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case 0x0ac: if(regs.flagb.s1 == 0) regs.pc = jp; return; //JNSB1
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case 0x0ae: if(regs.flagb.s1 == 1) regs.pc = jp; return; //JSB1
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case 0x0b0: if((regs.dp & 0x0f) == 0x00) regs.pc = jp; return; //JDPL0
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case 0x0b1: if((regs.dp & 0x0f) != 0x00) regs.pc = jp; return; //JDPLN0
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case 0x0b2: if((regs.dp & 0x0f) == 0x0f) regs.pc = jp; return; //JDPLF
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case 0x0b3: if((regs.dp & 0x0f) != 0x0f) regs.pc = jp; return; //JDPLNF
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case 0x0bc: if(regs.sr.rqm == 0) regs.pc = jp; return; //JNRQM
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case 0x0be: if(regs.sr.rqm == 1) regs.pc = jp; return; //JRQM
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case 0x100: regs.pc = jp & ~0x2000; return; //LJMP
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case 0x101: regs.pc = jp | 0x2000; return; //HJMP
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case 0x140: regs.stack[regs.sp++] = regs.pc; regs.pc = jp & ~0x2000; return; //LCALL
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case 0x141: regs.stack[regs.sp++] = regs.pc; regs.pc = jp | 0x2000; return; //HCALL
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}
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}
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void uPD96050::exec_ld(uint24 opcode) {
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uint16 id = opcode >> 6; //immediate data
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uint4 dst = opcode >> 0; //destination
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switch(dst) {
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case 0: break;
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case 1: regs.a = id; break;
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case 2: regs.b = id; break;
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case 3: regs.tr = id; break;
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case 4: regs.dp = id; break;
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case 5: regs.rp = id; break;
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case 6: regs.dr = id; regs.sr.rqm = 1; break;
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case 7: regs.sr = (regs.sr & 0x907c) | (id & ~0x907c); break;
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case 8: regs.so = id; break; //LSB
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case 9: regs.so = id; break; //MSB
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case 10: regs.k = id; break;
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case 11: regs.k = id; regs.l = dataROM[regs.rp]; break;
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case 12: regs.l = id; regs.k = dataRAM[regs.dp | 0x40]; break;
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case 13: regs.l = id; break;
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case 14: regs.trb = id; break;
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case 15: dataRAM[regs.dp] = id; break;
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}
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}
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