mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-10-04 18:41:49 +02:00
78d49d3873
byuu says: Changelog: - int_t<bits> replaced with Integer<bits> - uint_t<bits> replaced with Natural<bits> - fixed "Synchronize Audio" menu option that broke recently - all of sfc/performance ported to "auto function() -> return;" syntax With this WIP, all of higan is finally ported over to the new function declaration syntax. Thank the gods. There's still going to be periodic disruption for diffs from porting over signed->int, unsigned->uint, and whatever we come up with for the new Natural<> and Integer<> classes. But the worst of it's behind us now.
300 lines
7.4 KiB
C++
300 lines
7.4 KiB
C++
auto CPU::mmio_read(uint addr) -> uint8 {
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if((addr & 0xffc0) == 0x2140) {
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synchronizeSMP();
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return smp.port_read(addr & 3);
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}
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switch(addr & 0xffff) {
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case 0x2180: {
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uint8 result = bus.read(0x7e0000 | status.wram_addr);
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status.wram_addr = (status.wram_addr + 1) & 0x01ffff;
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return result;
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}
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case 0x4016: {
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uint8 result = regs.mdr & 0xfc;
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result |= device.controllerPort1->data() & 3;
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return result;
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}
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case 0x4017: {
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uint8 result = (regs.mdr & 0xe0) | 0x1c;
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result |= device.controllerPort2->data() & 3;
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return result;
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}
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case 0x4210: {
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uint8 result = (regs.mdr & 0x70);
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result |= status.nmi_line << 7;
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result |= 0x02; //CPU revision
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status.nmi_line = false;
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return result;
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}
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case 0x4211: {
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uint8 result = (regs.mdr & 0x7f);
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result |= status.irq_line << 7;
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status.irq_line = false;
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return result;
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}
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case 0x4212: {
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uint8 result = (regs.mdr & 0x3e);
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unsigned vbstart = ppu.overscan() == false ? 225 : 240;
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if(vcounter() >= vbstart && vcounter() <= vbstart + 2) result |= 0x01;
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if(hcounter() <= 2 || hcounter() >= 1096) result |= 0x40;
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if(vcounter() >= vbstart) result |= 0x80;
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return result;
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}
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case 0x4213: return status.pio;
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case 0x4214: return status.rddiv >> 0;
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case 0x4215: return status.rddiv >> 8;
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case 0x4216: return status.rdmpy >> 0;
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case 0x4217: return status.rdmpy >> 8;
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case 0x4218: return status.joy1l;
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case 0x4219: return status.joy1h;
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case 0x421a: return status.joy2l;
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case 0x421b: return status.joy2h;
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case 0x421c: return status.joy3l;
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case 0x421d: return status.joy3h;
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case 0x421e: return status.joy4l;
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case 0x421f: return status.joy4h;
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}
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if((addr & 0xff80) == 0x4300) {
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unsigned i = (addr >> 4) & 7;
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switch(addr & 0xff8f) {
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case 0x4300: {
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return (channel[i].direction << 7)
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| (channel[i].indirect << 6)
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| (channel[i].unused << 5)
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| (channel[i].reverse_transfer << 4)
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| (channel[i].fixed_transfer << 3)
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| (channel[i].transfer_mode << 0);
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}
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case 0x4301: return channel[i].dest_addr;
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case 0x4302: return channel[i].source_addr >> 0;
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case 0x4303: return channel[i].source_addr >> 8;
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case 0x4304: return channel[i].source_bank;
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case 0x4305: return channel[i].transfer_size >> 0;
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case 0x4306: return channel[i].transfer_size >> 8;
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case 0x4307: return channel[i].indirect_bank;
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case 0x4308: return channel[i].hdma_addr >> 0;
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case 0x4309: return channel[i].hdma_addr >> 8;
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case 0x430a: return channel[i].line_counter;
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case 0x430b: case 0x430f: return channel[i].unknown;
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}
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}
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return regs.mdr;
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}
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auto CPU::mmio_write(uint addr, uint8 data) -> void {
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if((addr & 0xffc0) == 0x2140) {
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synchronizeSMP();
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port_write(addr & 3, data);
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return;
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}
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switch(addr & 0xffff) {
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case 0x2180: {
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bus.write(0x7e0000 | status.wram_addr, data);
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status.wram_addr = (status.wram_addr + 1) & 0x01ffff;
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return;
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}
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case 0x2181: {
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status.wram_addr = (status.wram_addr & 0x01ff00) | (data << 0);
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return;
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}
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case 0x2182: {
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status.wram_addr = (status.wram_addr & 0x0100ff) | (data << 8);
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return;
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}
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case 0x2183: {
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status.wram_addr = (status.wram_addr & 0x00ffff) | ((data & 1) << 16);
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return;
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}
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case 0x4016: {
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device.controllerPort1->latch(data & 1);
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device.controllerPort2->latch(data & 1);
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return;
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}
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case 0x4200: {
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bool nmi_enabled = status.nmi_enabled;
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bool virq_enabled = status.virq_enabled;
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bool hirq_enabled = status.hirq_enabled;
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status.nmi_enabled = data & 0x80;
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status.virq_enabled = data & 0x20;
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status.hirq_enabled = data & 0x10;
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status.auto_joypad_poll_enabled = data & 0x01;
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if(!nmi_enabled && status.nmi_enabled && status.nmi_line) {
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status.nmi_transition = true;
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}
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if(status.virq_enabled && !status.hirq_enabled && status.irq_line) {
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status.irq_transition = true;
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}
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if(!status.virq_enabled && !status.hirq_enabled) {
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status.irq_line = false;
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status.irq_transition = false;
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}
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status.irq_lock = true;
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return;
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}
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case 0x4201: {
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if((status.pio & 0x80) && !(data & 0x80)) ppu.latch_counters();
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status.pio = data;
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}
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case 0x4202: {
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status.wrmpya = data;
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return;
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}
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case 0x4203: {
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status.wrmpyb = data;
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status.rdmpy = status.wrmpya * status.wrmpyb;
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return;
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}
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case 0x4204: {
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status.wrdiva = (status.wrdiva & 0xff00) | (data << 0);
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return;
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}
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case 0x4205: {
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status.wrdiva = (data << 8) | (status.wrdiva & 0x00ff);
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return;
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}
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case 0x4206: {
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status.wrdivb = data;
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status.rddiv = status.wrdivb ? status.wrdiva / status.wrdivb : 0xffff;
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status.rdmpy = status.wrdivb ? status.wrdiva % status.wrdivb : status.wrdiva;
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return;
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}
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case 0x4207: {
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status.htime = (status.htime & 0x0100) | (data << 0);
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return;
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}
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case 0x4208: {
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status.htime = ((data & 1) << 8) | (status.htime & 0x00ff);
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return;
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}
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case 0x4209: {
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status.vtime = (status.vtime & 0x0100) | (data << 0);
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return;
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}
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case 0x420a: {
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status.vtime = ((data & 1) << 8) | (status.vtime & 0x00ff);
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return;
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}
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case 0x420b: {
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for(unsigned i = 0; i < 8; i++) channel[i].dma_enabled = data & (1 << i);
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if(data) dma_run();
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return;
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}
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case 0x420c: {
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for(unsigned i = 0; i < 8; i++) channel[i].hdma_enabled = data & (1 << i);
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return;
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}
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case 0x420d: {
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status.rom_speed = data & 1 ? 6 : 8;
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return;
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}
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}
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if((addr & 0xff80) == 0x4300) {
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uint i = (addr >> 4) & 7;
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switch(addr & 0xff8f) {
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case 0x4300: {
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channel[i].direction = data & 0x80;
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channel[i].indirect = data & 0x40;
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channel[i].unused = data & 0x20;
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channel[i].reverse_transfer = data & 0x10;
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channel[i].fixed_transfer = data & 0x08;
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channel[i].transfer_mode = data & 0x07;
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return;
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}
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case 0x4301: {
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channel[i].dest_addr = data;
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return;
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}
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case 0x4302: {
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channel[i].source_addr = (channel[i].source_addr & 0xff00) | (data << 0);
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return;
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}
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case 0x4303: {
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channel[i].source_addr = (data << 8) | (channel[i].source_addr & 0x00ff);
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return;
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}
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case 0x4304: {
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channel[i].source_bank = data;
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return;
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}
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case 0x4305: {
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channel[i].transfer_size = (channel[i].transfer_size & 0xff00) | (data << 0);
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return;
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}
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case 0x4306: {
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channel[i].transfer_size = (data << 8) | (channel[i].transfer_size & 0x00ff);
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return;
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}
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case 0x4307: {
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channel[i].indirect_bank = data;
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return;
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}
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case 0x4308: {
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channel[i].hdma_addr = (channel[i].hdma_addr & 0xff00) | (data << 0);
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return;
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}
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case 0x4309: {
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channel[i].hdma_addr = (data << 8) | (channel[i].hdma_addr & 0x00ff);
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return;
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}
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case 0x430a: {
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channel[i].line_counter = data;
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return;
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}
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case 0x430b: case 0x430f: {
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channel[i].unknown = data;
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return;
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}
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}
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}
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}
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