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https://github.com/bsnes-emu/bsnes.git
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78d49d3873
byuu says: Changelog: - int_t<bits> replaced with Integer<bits> - uint_t<bits> replaced with Natural<bits> - fixed "Synchronize Audio" menu option that broke recently - all of sfc/performance ported to "auto function() -> return;" syntax With this WIP, all of higan is finally ported over to the new function declaration syntax. Thank the gods. There's still going to be periodic disruption for diffs from porting over signed->int, unsigned->uint, and whatever we come up with for the new Natural<> and Integer<> classes. But the worst of it's behind us now.
146 lines
2.9 KiB
C++
146 lines
2.9 KiB
C++
#define CYCLE_ACCURATE
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#include <sfc/sfc.hpp>
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#define SMP_CPP
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namespace SuperFamicom {
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SMP smp;
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#include "algorithms.cpp"
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#include "core.cpp"
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#include "memory.cpp"
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#include "timing.cpp"
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SMP::SMP() {
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apuram = new uint8[64 * 1024];
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for(auto& byte : iplrom) byte = 0;
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}
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auto SMP::synchronizeCPU() -> void {
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if(CPU::Threaded == true) {
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//if(clock >= 0 && scheduler.sync != Scheduler::SynchronizeMode::All) co_switch(cpu.thread);
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} else {
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while(clock >= 0) cpu.enter();
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}
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}
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auto SMP::synchronizeDSP() -> void {
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if(DSP::Threaded == true) {
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//if(dsp.clock < 0 && scheduler.sync != Scheduler::SynchronizeMode::All) co_switch(dsp.thread);
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} else {
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while(dsp.clock < 0) dsp.enter();
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}
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}
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auto SMP::enter() -> void {
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while(clock < 0) op_step();
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}
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auto SMP::power() -> void {
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Thread::frequency = system.apuFrequency();
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Thread::clock = 0;
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timer0.target = 0;
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timer1.target = 0;
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timer2.target = 0;
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for(uint n = 0; n < 256; n++) {
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cycle_table_dsp[n] = (cycle_count_table[n] * 24);
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cycle_table_cpu[n] = (cycle_count_table[n] * 24) * cpu.frequency;
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}
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cycle_step_cpu = 24 * cpu.frequency;
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reset();
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}
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auto SMP::reset() -> void {
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for(uint n = 0x0000; n <= 0xffff; n++) apuram[n] = 0x00;
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opcode_number = 0;
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opcode_cycle = 0;
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regs.pc = 0xffc0;
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regs.sp = 0xef;
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regs.a = 0x00;
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regs.x = 0x00;
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regs.y = 0x00;
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regs.p = 0x02;
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//$00f1
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status.iplrom_enable = true;
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//$00f2
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status.dsp_addr = 0x00;
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//$00f8,$00f9
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status.ram00f8 = 0x00;
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status.ram00f9 = 0x00;
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//timers
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timer0.enable = timer1.enable = timer2.enable = false;
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timer0.stage1_ticks = timer1.stage1_ticks = timer2.stage1_ticks = 0;
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timer0.stage2_ticks = timer1.stage2_ticks = timer2.stage2_ticks = 0;
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timer0.stage3_ticks = timer1.stage3_ticks = timer2.stage3_ticks = 0;
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}
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auto SMP::serialize(serializer& s) -> void {
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Thread::serialize(s);
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s.array(apuram, 64 * 1024);
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s.integer(opcode_number);
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s.integer(opcode_cycle);
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s.integer(regs.pc);
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s.integer(regs.sp);
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s.integer(regs.a);
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s.integer(regs.x);
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s.integer(regs.y);
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s.integer(regs.p.n);
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s.integer(regs.p.v);
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s.integer(regs.p.p);
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s.integer(regs.p.b);
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s.integer(regs.p.h);
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s.integer(regs.p.i);
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s.integer(regs.p.z);
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s.integer(regs.p.c);
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s.integer(rd);
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s.integer(wr);
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s.integer(dp);
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s.integer(sp);
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s.integer(ya);
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s.integer(bit);
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s.integer(status.iplrom_enable);
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s.integer(status.dsp_addr);
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s.integer(status.ram00f8);
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s.integer(status.ram00f9);
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s.integer(timer0.enable);
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s.integer(timer0.target);
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s.integer(timer0.stage1_ticks);
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s.integer(timer0.stage2_ticks);
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s.integer(timer0.stage3_ticks);
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s.integer(timer1.enable);
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s.integer(timer1.target);
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s.integer(timer1.stage1_ticks);
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s.integer(timer1.stage2_ticks);
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s.integer(timer1.stage3_ticks);
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s.integer(timer2.enable);
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s.integer(timer2.target);
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s.integer(timer2.stage1_ticks);
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s.integer(timer2.stage2_ticks);
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s.integer(timer2.stage3_ticks);
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}
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}
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