mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-02-24 07:02:27 +01:00
94b2538af5
byuu says: Basically just a project rename, with s/bsnes/higan and the new icon from lowkee added in. It won't compile on Windows because I forgot to update the resource.rc file, and a path transform command isn't working on Windows. It was really just meant as a starting point, so that v091 WIPs can flow starting from .00 with the new name (it overshadows bsnes v091, so publicly speaking this "shouldn't exist" and will probably be deleted from Google Code when v092 is ready.)
317 lines
10 KiB
C++
Executable File
317 lines
10 KiB
C++
Executable File
uint8 CPU::read(uint32 addr) {
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uint8 result = 0;
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switch(addr) {
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//DMA0CNT_H
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//DMA1CNT_H
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//DMA2CNT_H
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//DMA3CNT_H
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case 0x040000ba: case 0x040000bb:
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case 0x040000c6: case 0x040000c7:
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case 0x040000d2: case 0x040000d3:
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case 0x040000de: case 0x040000df: {
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auto &dma = regs.dma[(addr - 0x040000ba) / 12];
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unsigned shift = (addr & 1) * 8;
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return dma.control >> shift;
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}
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//TM0CNT_L
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//TM1CNT_L
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//TM2CNT_L
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//TM3CNT_L
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case 0x04000100: case 0x04000101:
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case 0x04000104: case 0x04000105:
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case 0x04000108: case 0x04000109:
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case 0x0400010c: case 0x0400010d: {
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auto &timer = regs.timer[(addr >> 2) & 3];
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unsigned shift = (addr & 1) * 8;
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return timer.period >> shift;
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}
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//TIM0CNT_H
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case 0x04000102: case 0x04000103:
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case 0x04000106: case 0x04000107:
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case 0x0400010a: case 0x0400010b:
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case 0x0400010e: case 0x0400010f: {
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auto &timer = regs.timer[(addr >> 2) & 3];
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unsigned shift = (addr & 1) * 8;
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return timer.control >> shift;
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}
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//SIOMULTI0 (SIODATA32_L)
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//SIOMULTI1 (SIODATA32_H)
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//SIOMULTI2
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//SIOMULTI3
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case 0x04000120: case 0x04000121:
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case 0x04000122: case 0x04000123:
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case 0x04000124: case 0x04000125:
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case 0x04000126: case 0x04000127: {
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auto &data = regs.serial.data[(addr >> 1) & 3];
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unsigned shift = (addr & 1) * 8;
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return data >> shift;
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}
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//SIOCNT
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case 0x04000128: return regs.serial.control >> 0;
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case 0x04000129: return regs.serial.control >> 8;
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//SIOMLT_SEND (SIODATA8)
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case 0x0400012a: return regs.serial.data8;
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case 0x0400012b: return 0u;
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//KEYINPUT
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case 0x04000130:
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for(unsigned n = 0; n < 8; n++) result |= interface->inputPoll(0, 0, n) << n;
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if((result & 0xc0) == 0xc0) result &= ~0xc0; //up+down cannot be pressed simultaneously
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if((result & 0x30) == 0x30) result &= ~0x30; //left+right cannot be pressed simultaneously
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return result ^ 0xff;
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case 0x04000131:
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result |= interface->inputPoll(0, 0, 8) << 0;
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result |= interface->inputPoll(0, 0, 9) << 1;
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return result ^ 0x03;
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//KEYCNT
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case 0x04000132: return regs.keypad.control >> 0;
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case 0x04000133: return regs.keypad.control >> 8;
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//RCNT
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case 0x04000134: return regs.joybus.settings >> 0;
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case 0x04000135: return regs.joybus.settings >> 8;
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//JOYCNT
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case 0x04000140: return regs.joybus.control >> 0;
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case 0x04000141: return regs.joybus.control >> 8;
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//JOY_RECV_L
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//JOY_RECV_H
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case 0x04000150: return regs.joybus.receive >> 0;
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case 0x04000151: return regs.joybus.receive >> 8;
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case 0x04000152: return regs.joybus.receive >> 16;
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case 0x04000153: return regs.joybus.receive >> 24;
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//JOY_TRANS_L
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//JOY_TRANS_H
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case 0x04000154: return regs.joybus.transmit >> 0;
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case 0x04000155: return regs.joybus.transmit >> 8;
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case 0x04000156: return regs.joybus.transmit >> 16;
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case 0x04000157: return regs.joybus.transmit >> 24;
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//JOYSTAT
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case 0x04000158: return regs.joybus.status >> 0;
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case 0x04000159: return regs.joybus.status >> 8;
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//IE
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case 0x04000200: return regs.irq.enable >> 0;
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case 0x04000201: return regs.irq.enable >> 8;
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//IF
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case 0x04000202: return regs.irq.flag >> 0;
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case 0x04000203: return regs.irq.flag >> 8;
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//WAITCNT
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case 0x04000204: return regs.wait.control >> 0;
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case 0x04000205: return regs.wait.control >> 8;
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//IME
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case 0x04000208: return regs.ime;
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case 0x04000209: return 0u;
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//POSTFLG + HALTCNT
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case 0x04000300: return regs.postboot;
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case 0x04000301: return 0u;
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//MEMCNT_L
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case 0x04000800: return regs.memory.control >> 0;
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case 0x04000801: return regs.memory.control >> 8;
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//MEMCNT_H
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case 0x04000802: return regs.memory.control >> 16;
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case 0x04000803: return regs.memory.control >> 24;
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}
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return 0u;
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}
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void CPU::write(uint32 addr, uint8 byte) {
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switch(addr) {
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//DMA0SAD
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//DMA1SAD
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//DMA2SAD
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//DMA3SAD
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case 0x040000b0: case 0x040000b1: case 0x040000b2: case 0x040000b3:
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case 0x040000bc: case 0x040000bd: case 0x040000be: case 0x040000bf:
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case 0x040000c8: case 0x040000c9: case 0x040000ca: case 0x040000cb:
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case 0x040000d4: case 0x040000d5: case 0x040000d6: case 0x040000d7: {
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auto &dma = regs.dma[(addr - 0x040000b0) / 12];
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unsigned shift = (addr & 3) * 8;
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dma.source = (dma.source & ~(255 << shift)) | (byte << shift);
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return;
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}
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//DMA0DAD
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//DMA1DAD
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//DMA2DAD
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//DMA3DAD
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case 0x040000b4: case 0x040000b5: case 0x040000b6: case 0x040000b7:
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case 0x040000c0: case 0x040000c1: case 0x040000c2: case 0x040000c3:
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case 0x040000cc: case 0x040000cd: case 0x040000ce: case 0x040000cf:
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case 0x040000d8: case 0x040000d9: case 0x040000da: case 0x040000db: {
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auto &dma = regs.dma[(addr - 0x040000b4) / 12];
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unsigned shift = (addr & 3) * 8;
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dma.target = (dma.target & ~(255 << shift)) | (byte << shift);
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return;
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}
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//DMA0CNT_L
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//DMA1CNT_L
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//DMA2CNT_L
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//DMA3CNT_L
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case 0x040000b8: case 0x040000b9:
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case 0x040000c4: case 0x040000c5:
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case 0x040000d0: case 0x040000d1:
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case 0x040000dc: case 0x040000dd: {
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auto &dma = regs.dma[(addr - 0x040000b8) / 12];
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unsigned shift = (addr & 1) * 8;
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dma.length = (dma.length & ~(255 << shift)) | (byte << shift);
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return;
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}
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//DMA0CNT_H
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//DMA1CNT_H
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//DMA2CNT_H
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//DMA3CNT_H
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case 0x040000ba: case 0x040000bb:
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case 0x040000c6: case 0x040000c7:
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case 0x040000d2: case 0x040000d3:
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case 0x040000de: case 0x040000df: {
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auto &dma = regs.dma[(addr - 0x040000ba) / 12];
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unsigned shift = (addr & 1) * 8;
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bool enable = dma.control.enable;
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dma.control = (dma.control & ~(255 << shift)) | (byte << shift);
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if(enable == 0 && dma.control.enable) {
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if(dma.control.timingmode == 0) dma.pending = true; //immediate transfer mode
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dma.run.target = dma.target;
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dma.run.source = dma.source;
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dma.run.length = dma.length;
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} else if(dma.control.enable == 0) {
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dma.pending = false;
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}
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return;
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}
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//TM0CNT_L
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//TM1CNT_L
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//TM2CNT_L
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//TM3CNT_L
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case 0x04000100: case 0x04000101:
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case 0x04000104: case 0x04000105:
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case 0x04000108: case 0x04000109:
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case 0x0400010c: case 0x0400010d: {
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auto &timer = regs.timer[(addr >> 2) & 3];
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unsigned shift = (addr & 1) * 8;
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timer.reload = (timer.reload & ~(255 << shift)) | (byte << shift);
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return;
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}
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//TM0CNT_H
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//TM1CNT_H
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//TM2CNT_H
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//TM3CNT_H
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case 0x04000102:
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case 0x04000106:
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case 0x0400010a:
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case 0x0400010e: {
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auto &timer = regs.timer[(addr >> 2) & 3];
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bool enable = timer.control.enable;
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timer.control = byte;
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if(enable == 0 && timer.control.enable == 1) {
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timer.period = timer.reload;
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}
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return;
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}
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//SIOMULTI0 (SIODATA32_L)
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//SIOMULTI1 (SIODATA32_H)
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//SIOMULTI2
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//SIOMULTI3
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case 0x04000120: case 0x04000121:
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case 0x04000122: case 0x04000123:
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case 0x04000124: case 0x04000125:
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case 0x04000126: case 0x04000127: {
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auto &data = regs.serial.data[(addr >> 1) & 3];
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unsigned shift = (addr & 1) * 8;
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data = (data & ~(255 << shift)) | (byte << shift);
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return;
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}
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//SIOCNT
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case 0x04000128: regs.serial.control = (regs.serial.control & 0xff00) | (byte << 0); return;
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case 0x04000129: regs.serial.control = (regs.serial.control & 0x00ff) | (byte << 8); return;
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//SIOMLT_SEND (SIODATA8)
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case 0x0400012a: regs.serial.data8 = byte; return;
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case 0x0400012b: return;
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//KEYCNT
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case 0x04000132: regs.keypad.control = (regs.keypad.control & 0xff00) | (byte << 0); return;
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case 0x04000133: regs.keypad.control = (regs.keypad.control & 0x00ff) | (byte << 8); return;
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//RCNT
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case 0x04000134: regs.joybus.settings = (regs.joybus.settings & 0xff00) | (byte << 0); return;
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case 0x04000135: regs.joybus.settings = (regs.joybus.settings & 0x00ff) | (byte << 8); return;
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//JOYCNT
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case 0x04000140: regs.joybus.control = (regs.joybus.control & 0xff00) | (byte << 0); return;
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case 0x04000141: regs.joybus.control = (regs.joybus.control & 0x00ff) | (byte << 8); return;
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//JOY_RECV_L
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//JOY_RECV_H
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case 0x04000150: regs.joybus.receive = (regs.joybus.receive & 0xffffff00) | (byte << 0); return;
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case 0x04000151: regs.joybus.receive = (regs.joybus.receive & 0xffff00ff) | (byte << 8); return;
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case 0x04000152: regs.joybus.receive = (regs.joybus.receive & 0xff00ffff) | (byte << 16); return;
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case 0x04000153: regs.joybus.receive = (regs.joybus.receive & 0x00ffffff) | (byte << 24); return;
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//JOY_TRANS_L
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//JOY_TRANS_H
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case 0x04000154: regs.joybus.transmit = (regs.joybus.transmit & 0xffffff00) | (byte << 0); return;
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case 0x04000155: regs.joybus.transmit = (regs.joybus.transmit & 0xffff00ff) | (byte << 8); return;
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case 0x04000156: regs.joybus.transmit = (regs.joybus.transmit & 0xff00ffff) | (byte << 16); return;
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case 0x04000157: regs.joybus.transmit = (regs.joybus.transmit & 0x00ffffff) | (byte << 24); return;
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//JOYSTAT
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case 0x04000158: regs.joybus.status = (regs.joybus.status & 0xff00) | (byte << 0); return;
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case 0x04000159: regs.joybus.status = (regs.joybus.status & 0x00ff) | (byte << 8); return;
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//IE
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case 0x04000200: regs.irq.enable = (regs.irq.enable & 0xff00) | (byte << 0); return;
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case 0x04000201: regs.irq.enable = (regs.irq.enable & 0x00ff) | (byte << 8); return;
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//IF
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case 0x04000202: regs.irq.flag = regs.irq.flag & ~(byte << 0); return;
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case 0x04000203: regs.irq.flag = regs.irq.flag & ~(byte << 8); return;
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//WAITCNT
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case 0x04000204: regs.wait.control = (regs.wait.control & 0xff00) | ((byte & 0xff) << 0); return;
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case 0x04000205: regs.wait.control = (regs.wait.control & 0x00ff) | ((byte & 0x7f) << 8); return;
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//IME
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case 0x04000208: regs.ime = byte >> 0; return;
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case 0x04000209: return;
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//POSTFLG, HALTCNT
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case 0x04000300: regs.postboot |= byte >> 0; return;
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case 0x04000301: regs.mode = byte & 0x80 ? Registers::Mode::Stop : Registers::Mode::Halt; return;
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//MEMCNT_L
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//MEMCNT_H
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case 0x04000800: regs.memory.control = (regs.memory.control & 0xffffff00) | (byte << 0); return;
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case 0x04000801: regs.memory.control = (regs.memory.control & 0xffff00ff) | (byte << 8); return;
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case 0x04000802: regs.memory.control = (regs.memory.control & 0xff00ffff) | (byte << 16); return;
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case 0x04000803: regs.memory.control = (regs.memory.control & 0x00ffffff) | (byte << 24); return;
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}
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}
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