mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-10-04 09:22:01 +02:00
95547f4ff8
- Major source code cleanup
- Completely rewrote memory mapper to support runtime MMCs
- Updated S-DD1 MMC to use new memory mapping interface
- Improved S-DD1 emulation, thanks to information from orwannon
- Added support for SameGame -- load via "Load Special -> Load BS-X Slotted Cart" menu option
- Completely rewrote cartridge loader to support BS-X, BS-X slotted carts and ST carts
- Created custom dialog windows for multicart loading
- Improved generic memory mapper, which eliminates the need for cart.db [Nach]
- Added BS-X slotted cart detection to generic memory mapper [Nach]
- Linux port will now ignore keypresses when window is inactive
- Linux port will use much less CPU power when idle
- Added detailed compilation instructions to Makefile for Linux port
- Added "make install" target and PNG program icon for Linux port
- Switched Windows compiler to MinGW/GCC4
- Windows executable is now packed with UPX to decrease filesize
- Removed .ufo, .gd7 and .078 ROM extensions; added .bs extension
- Added preliminary support for the BS-X base unit, BS-X base cartridge + MMC, and BS-X flash I/O
122 lines
3.0 KiB
C++
122 lines
3.0 KiB
C++
/*****
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* These 3 functions control bus timing for the CPU.
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* cpu_io is an I/O cycle, and always 6 clock cycles long.
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* mem_read / mem_write indicate memory access bus cycles.
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* they are either 6, 8, or 12 bus cycles long, depending
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* both on location and the $420d.d0 FastROM enable bit.
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*****/
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void sCPU::op_io() {
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status.clock_count = 6;
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precycle_edge();
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add_clocks(6);
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cycle_edge();
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}
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uint8 sCPU::op_read(uint32 addr) {
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status.clock_count = bus.speed(addr);
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precycle_edge();
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add_clocks(status.clock_count - 4);
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regs.mdr = bus.read(addr);
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add_clocks(4);
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cycle_edge();
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return regs.mdr;
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}
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void sCPU::op_write(uint32 addr, uint8 data) {
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status.clock_count = bus.speed(addr);
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precycle_edge();
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add_clocks(status.clock_count);
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regs.mdr = data;
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bus.write(addr, regs.mdr);
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cycle_edge();
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}
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//
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alwaysinline uint8 sCPU::op_readpc() {
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return op_read((regs.pc.b << 16) + regs.pc.w++);
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}
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alwaysinline uint8 sCPU::op_readstack() {
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if(regs.e) {
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regs.s.l++;
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} else {
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regs.s.w++;
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}
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return op_read(regs.s.w);
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}
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alwaysinline uint8 sCPU::op_readstackn() {
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return op_read(++regs.s.w);
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}
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alwaysinline uint8 sCPU::op_readaddr(uint32 addr) {
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return op_read(addr & 0xffff);
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}
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alwaysinline uint8 sCPU::op_readlong(uint32 addr) {
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return op_read(addr & 0xffffff);
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}
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alwaysinline uint8 sCPU::op_readdbr(uint32 addr) {
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return op_read(((regs.db << 16) + addr) & 0xffffff);
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}
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alwaysinline uint8 sCPU::op_readpbr(uint32 addr) {
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return op_read((regs.pc.b << 16) + (addr & 0xffff));
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}
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alwaysinline uint8 sCPU::op_readdp(uint32 addr) {
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if(regs.e && regs.d.l == 0x00) {
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return op_read((regs.d & 0xff00) + ((regs.d + (addr & 0xffff)) & 0xff));
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} else {
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return op_read((regs.d + (addr & 0xffff)) & 0xffff);
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}
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}
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alwaysinline uint8 sCPU::op_readsp(uint32 addr) {
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return op_read((regs.s + (addr & 0xffff)) & 0xffff);
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}
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alwaysinline void sCPU::op_writestack(uint8 data) {
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op_write(regs.s.w, data);
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if(regs.e) {
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regs.s.l--;
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} else {
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regs.s.w--;
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}
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}
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alwaysinline void sCPU::op_writestackn(uint8 data) {
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op_write(regs.s.w--, data);
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}
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alwaysinline void sCPU::op_writeaddr(uint32 addr, uint8 data) {
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op_write(addr & 0xffff, data);
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}
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alwaysinline void sCPU::op_writelong(uint32 addr, uint8 data) {
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op_write(addr & 0xffffff, data);
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}
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alwaysinline void sCPU::op_writedbr(uint32 addr, uint8 data) {
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op_write(((regs.db << 16) + addr) & 0xffffff, data);
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}
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alwaysinline void sCPU::op_writepbr(uint32 addr, uint8 data) {
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op_write((regs.pc.b << 16) + (addr & 0xffff), data);
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}
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alwaysinline void sCPU::op_writedp(uint32 addr, uint8 data) {
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if(regs.e && regs.d.l == 0x00) {
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op_write((regs.d & 0xff00) + ((regs.d + (addr & 0xffff)) & 0xff), data);
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} else {
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op_write((regs.d + (addr & 0xffff)) & 0xffff, data);
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}
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}
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alwaysinline void sCPU::op_writesp(uint32 addr, uint8 data) {
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op_write((regs.s + (addr & 0xffff)) & 0xffff, data);
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}
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