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https://github.com/bsnes-emu/bsnes.git
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50420e3dd2
byuu says:
Changelog:
- added nall/bit-field.hpp
- updated all CPU cores (sans LR35902 due to some complexities) to use
BitFields instead of bools
- updated as many CPU cores as I could to use BitFields instead of union {
struct { uint8_t ... }; }; pairs
The speed changes are mostly a wash for this. In some instances,
I noticed a ~2-3% speedup (eg SNES emulation), and in others a 2-3%
slowdown (eg Famicom emulation.) It's within the margin of error, so
it's safe to say it has no impact.
This does give us a lot of new useful things, however:
- no more manual reconstruction of flag values from lots of left shifts
and ORs
- no more manual deconstruction of flag values from lots of ANDs
- ability to get completely free aliases to flag groups (eg GSU can
provide alt2, alt1 and also alt (which is alt2,alt1 combined)
- removes the need for the nasty order_lsbN macro hack (eventually will
make higan 100% endian independent)
- saves us from insane compilers that try and do nasty things with
alignment on union-structs
- saves us from insane compilers that try to store bit-field bits in
reverse order
- will allow some really novel new use cases (I'm planning an
instant-decode ARM opcode function, for instance.)
- reduces code size (we can serialize flag registers in one line instead
of one for each flag)
However, I probably won't use it for super critical code that's constantly
reading out register values (eg PPU MMIO registers.) I think there we
would end up with a performance penalty.
57 lines
1.1 KiB
C++
57 lines
1.1 KiB
C++
auto GSU::serialize(serializer& s) -> void {
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s.integer(regs.pipeline);
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s.integer(regs.ramaddr);
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for(auto n : range(16)) {
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s.integer(regs.r[n].data);
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s.integer(regs.r[n].modified);
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}
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s.integer(regs.sfr.data);
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s.integer(regs.pbr);
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s.integer(regs.rombr);
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s.integer(regs.rambr);
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s.integer(regs.cbr);
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s.integer(regs.scbr);
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s.integer(regs.scmr.ht);
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s.integer(regs.scmr.ron);
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s.integer(regs.scmr.ran);
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s.integer(regs.scmr.md);
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s.integer(regs.colr);
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s.integer(regs.por.obj);
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s.integer(regs.por.freezehigh);
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s.integer(regs.por.highnibble);
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s.integer(regs.por.dither);
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s.integer(regs.por.transparent);
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s.integer(regs.bramr);
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s.integer(regs.vcr);
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s.integer(regs.cfgr.irq);
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s.integer(regs.cfgr.ms0);
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s.integer(regs.clsr);
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s.integer(regs.romcl);
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s.integer(regs.romdr);
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s.integer(regs.ramcl);
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s.integer(regs.ramar);
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s.integer(regs.ramdr);
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s.integer(regs.sreg);
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s.integer(regs.dreg);
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s.array(cache.buffer);
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s.array(cache.valid);
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for(uint n : range(2)) {
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s.integer(pixelcache[n].offset);
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s.integer(pixelcache[n].bitpend);
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s.array(pixelcache[n].data);
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}
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}
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