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50420e3dd2
byuu says:
Changelog:
- added nall/bit-field.hpp
- updated all CPU cores (sans LR35902 due to some complexities) to use
BitFields instead of bools
- updated as many CPU cores as I could to use BitFields instead of union {
struct { uint8_t ... }; }; pairs
The speed changes are mostly a wash for this. In some instances,
I noticed a ~2-3% speedup (eg SNES emulation), and in others a 2-3%
slowdown (eg Famicom emulation.) It's within the margin of error, so
it's safe to say it has no impact.
This does give us a lot of new useful things, however:
- no more manual reconstruction of flag values from lots of left shifts
and ORs
- no more manual deconstruction of flag values from lots of ANDs
- ability to get completely free aliases to flag groups (eg GSU can
provide alt2, alt1 and also alt (which is alt2,alt1 combined)
- removes the need for the nasty order_lsbN macro hack (eventually will
make higan 100% endian independent)
- saves us from insane compilers that try and do nasty things with
alignment on union-structs
- saves us from insane compilers that try to store bit-field bits in
reverse order
- will allow some really novel new use cases (I'm planning an
instant-decode ARM opcode function, for instance.)
- reduces code size (we can serialize flag registers in one line instead
of one for each flag)
However, I probably won't use it for super critical code that's constantly
reading out register values (eg PPU MMIO registers.) I think there we
would end up with a performance penalty.
28 lines
512 B
C++
28 lines
512 B
C++
auto uPD96050::serialize(serializer& s) -> void {
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s.array(dataRAM);
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s.array(regs.stack);
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s.integer(regs.pc);
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s.integer(regs.rp);
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s.integer(regs.dp);
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s.integer(regs.sp);
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s.integer(regs.k);
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s.integer(regs.l);
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s.integer(regs.m);
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s.integer(regs.n);
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s.integer(regs.a);
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s.integer(regs.b);
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s.integer(regs.flaga.data);
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s.integer(regs.flagb.data);
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s.integer(regs.tr);
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s.integer(regs.trb);
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s.integer(regs.sr.data);
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s.integer(regs.dr);
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s.integer(regs.si);
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s.integer(regs.so);
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}
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