mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-10-04 12:41:33 +02:00
09b326ae86
I have done quite a bit, so I´ll try my best to recap most of the fixes since the last release...
- HDMA was not running during DMA transfers
- Emulator did not recognize any filetype other than .smc
- Added configuration file support and imported my vector/string/config libraries into bsnes
- Added option to use system RAM instead of video RAM for display, this can greatly increase speed on certain video cards
- Increased speed by ~15% by adding 256x224 renderer (still very buggy when the SNES mixes video modes mid-frame)
- mvn/mvp opcodes were not setting the DB register
- Fixed joypad input in many games (Super Mario: All Stars, Dragon Quest III, etc.)
- Major speedup with frakeskip option
- Fixed default aspect ratio when emulator is first started
There´s probably a lot more, but that´s all I remember offhand... this release should be a lot closer to the quality of v0.005a, but still needs a bit more polishing.
317 lines
6.7 KiB
C++
317 lines
6.7 KiB
C++
#include "../../base.h"
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#include "bcpu_op_adc.cpp"
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#include "bcpu_op_and.cpp"
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#include "bcpu_op_cmp.cpp"
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#include "bcpu_op_eor.cpp"
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#include "bcpu_op_incdec.cpp"
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#include "bcpu_op_lda.cpp"
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#include "bcpu_op_misc.cpp"
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#include "bcpu_op_ora.cpp"
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#include "bcpu_op_pc.cpp"
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#include "bcpu_op_sbc.cpp"
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#include "bcpu_op_shift.cpp"
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#include "bcpu_op_sta.cpp"
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#include "bcpu_op_stack.cpp"
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#include "bcpu_exec.cpp"
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#include "bcpu_mmio.cpp"
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uint8 bCPU::pio_status() {
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return status.pio;
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}
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/***********
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*** IRQ ***
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***********
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cycles:
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[1] pbr,pc ; io
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[2] pbr,pc ; io
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[3] 0,s ; pbr
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[4] 0,s-1 ; pch
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[5] 0,s-2 ; pcl
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[6] 0,s-3 ; p
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[7] 0,va ; aavl
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[8] 0,va+1 ; aavh
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*/
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void bCPU::irq(uint16 addr) {
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if(cpustate == CPUSTATE_WAI) {
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regs.pc.w++;
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cpustate = CPUSTATE_RUN;
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}
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clock->add_cc1_cycles(mem_bus->speed(regs.pc)); //1
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clock->add_cc1_cycles(6); //2
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stack_write(regs.pc.b); //3
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stack_write(regs.pc.h); //4
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stack_write(regs.pc.l); //5
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stack_write(regs.p); //6
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rd.l = op_read(OPMODE_ADDR, addr); //7
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rd.h = op_read(OPMODE_ADDR, addr + 1); //8
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regs.pc.b = 0x00;
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regs.pc.w = rd.w;
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regs.p.d = 0;
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regs.p.i = 1;
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snes->notify(SNES::CPU_EXEC_OPCODE);
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}
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void bCPU::run() {
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uint16 v, h, hc, vs;
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v = clock->vcounter();
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h = clock->hcounter();
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hc = clock->hcycles();
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vs = clock->visible_scanlines();
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//HDMA test
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if(v < vs && h >= 278) {
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if(status.hdma_triggered == false) {
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status.hdma_triggered = true;
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dma->hdma_run();
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return;
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}
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}
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switch(cpustate) {
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case CPUSTATE_RUN:
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case CPUSTATE_WAI:
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//NMI test
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if(v >= (vs + 1) && status.nmi_triggered == false) {
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if((v == (vs + 1) && hc >= 12) || (v > (vs + 1))) {
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status.nmi_triggered = true;
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status.nmi_pin = 0;
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if(status.nmi_enabled == true) {
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irq(0xffea);
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return;
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}
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}
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}
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//IRQ test
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if(!regs.p.i) {
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if(status.virq_enabled == true && status.virq_enabled == true) {
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if(v == status.virq_pos && h >= status.hirq_pos && status.irq_pin == 1) {
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status.irq_triggered = true;
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status.irq_pin = 0;
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irq(0xffee);
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return;
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}
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} else if(status.virq_enabled == true) {
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if(v == status.virq_pos && status.irq_pin == 1) {
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status.irq_triggered = true;
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status.irq_pin = 0;
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irq(0xffee);
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return;
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}
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} else if(status.hirq_enabled == true) {
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if(h >= status.hirq_pos && status.irq_pin == 1) {
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status.irq_triggered = true;
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status.irq_pin = 0;
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irq(0xffee);
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return;
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}
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}
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}
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exec_opcode();
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break;
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case CPUSTATE_DMA:
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dma->run();
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break;
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case CPUSTATE_STP:
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exec_opcode();
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break;
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}
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}
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void bCPU::scanline() {
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uint16 v = clock->vcounter();
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status.hdma_triggered = false;
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if(v == 225 && status.auto_joypad_poll == true) {
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snes->poll_input();
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//When the SNES auto-polls the joypads, it writes 1, then 0 to
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//$4016, then reads from each 16 times to get the joypad state
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//information. As a result, the joypad read positions are set
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//to 16 after such a poll. Position 16 is the controller
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//connected status bit.
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status.joypad1_read_pos = 16;
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}
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if(status.virq_enabled == false) {
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status.irq_pin = 1;
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}
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}
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void bCPU::frame() {
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status.hdma_triggered = false;
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status.nmi_triggered = false;
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status.r4210_read = false;
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status.irq_pin = 1;
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dma->hdma_initialize();
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}
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void bCPU::power() {
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regs.a = regs.x = regs.y = 0x0000;
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regs.s = 0x01ff;
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reset();
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}
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void bCPU::reset() {
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/* reset vector location */
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regs.pc = mem_bus->read(0xfffc) | (mem_bus->read(0xfffd) << 8);
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/* registers are not fully reset by SNES */
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regs.x.h = 0x00;
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regs.y.h = 0x00;
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regs.s.h = 0x01;
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regs.d = 0x0000;
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regs.db = 0x00;
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regs.p = 0x34;
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regs.e = 1;
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cpustate = CPUSTATE_RUN;
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dma->reset();
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mmio_reset();
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optbl = optbl_e;
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status.hdma_triggered = false;
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status.nmi_triggered = false;
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status.nmi_pin = 1;
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status.r4210_read = false;
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status.irq_triggered = false;
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status.irq_pin = 1;
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}
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void bCPU::cpu_c2() {
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if(regs.d.l != 0x00) {
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clock->add_cc1_cycles(6);
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}
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}
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void bCPU::cpu_c4(uint16 a, uint16 b) {
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if(((a & 0xff00) != (b & 0xff00)) || !regs.p.x) {
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clock->add_cc1_cycles(6);
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}
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}
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void bCPU::cpu_c6(uint16 a) {
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if(regs.e) {
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if((regs.pc.w & 0xff00) != (a & 0xff00)) {
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clock->add_cc1_cycles(6);
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}
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}
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}
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void bCPU::cpu_io() {
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clock->add_cc1_cycles(6);
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}
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uint8 bCPU::op_read() {
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uint8 r;
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r = mem_bus->read(regs.pc);
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clock->add_cc1_cycles(mem_bus->speed(regs.pc));
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regs.pc.w++;
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return r;
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}
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uint8 bCPU::op_read(uint8 mode, uint32 addr) {
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uint8 r;
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switch(mode) {
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case OPMODE_ADDR:
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addr &= 0xffff;
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break;
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case OPMODE_LONG:
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addr &= 0xffffff;
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break;
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case OPMODE_DBR:
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addr &= 0xffffff;
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addr = (regs.db << 16) + addr;
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break;
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case OPMODE_PBR:
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addr &= 0xffff;
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addr = (regs.pc.b << 16) | addr;
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break;
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case OPMODE_DP:
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addr &= 0xffff;
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addr = (regs.d + addr) & 0xffff;
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break;
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case OPMODE_SP:
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addr &= 0xffff;
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addr = (regs.s + addr) & 0xffff;
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break;
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}
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r = mem_bus->read(addr);
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clock->add_cc1_cycles(mem_bus->speed(addr));
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return r;
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}
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void bCPU::op_write(uint8 mode, uint32 addr, uint8 value) {
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switch(mode) {
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case OPMODE_ADDR:
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addr &= 0xffff;
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break;
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case OPMODE_LONG:
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addr &= 0xffffff;
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break;
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case OPMODE_DBR:
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addr &= 0xffffff;
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addr = (regs.db << 16) + addr;
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break;
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case OPMODE_PBR:
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addr &= 0xffff;
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addr = (regs.pc.b << 16) | addr;
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break;
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case OPMODE_DP:
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addr &= 0xffff;
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addr = (regs.d + addr) & 0xffff;
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break;
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case OPMODE_SP:
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addr &= 0xffff;
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addr = (regs.s + addr) & 0xffff;
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break;
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}
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mem_bus->write(addr, value);
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clock->add_cc1_cycles(mem_bus->speed(addr));
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}
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uint8 bCPU::stack_read() {
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byte r;
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if(regs.e) {
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regs.s.l++;
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} else {
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regs.s.w++;
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}
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r = mem_bus->read(regs.s);
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clock->add_cc1_cycles(mem_bus->speed(regs.s));
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return r;
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}
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void bCPU::stack_write(uint8 value) {
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mem_bus->write(regs.s, value);
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clock->add_cc1_cycles(mem_bus->speed(regs.s));
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if(regs.e) {
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regs.s.l--;
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} else {
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regs.s.w--;
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}
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}
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bCPU::bCPU() {
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dma = new bDMA(this);
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mmio = new bCPUMMIO(this);
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init_op_tables();
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}
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bCPU::~bCPU() {
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delete(mmio);
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delete(dma);
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}
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