mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-10-04 10:46:32 +02:00
09b326ae86
I have done quite a bit, so I´ll try my best to recap most of the fixes since the last release...
- HDMA was not running during DMA transfers
- Emulator did not recognize any filetype other than .smc
- Added configuration file support and imported my vector/string/config libraries into bsnes
- Added option to use system RAM instead of video RAM for display, this can greatly increase speed on certain video cards
- Increased speed by ~15% by adding 256x224 renderer (still very buggy when the SNES mixes video modes mid-frame)
- mvn/mvp opcodes were not setting the DB register
- Fixed joypad input in many games (Super Mario: All Stars, Dragon Quest III, etc.)
- Major speedup with frakeskip option
- Fixed default aspect ratio when emulator is first started
There´s probably a lot more, but that´s all I remember offhand... this release should be a lot closer to the quality of v0.005a, but still needs a bit more polishing.
780 lines
22 KiB
C++
780 lines
22 KiB
C++
/*****************
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*** 0x0a: asl ***
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*****************
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cycles:
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[1] pbr,pc ; opcode
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[2] pbr,pc+1 ; io
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*/
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void bCPU::op_aslb() {
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cpu_io(); //2
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regs.p.c = !!(regs.a.l & 0x80);
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regs.a.l <<= 1;
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regs.p.n = !!(regs.a.l & 0x80);
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regs.p.z = (regs.a.l == 0);
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}
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void bCPU::op_aslw() {
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cpu_io(); //2
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regs.p.c = !!(regs.a.w & 0x8000);
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regs.a.w <<= 1;
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regs.p.n = !!(regs.a.w & 0x8000);
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regs.p.z = (regs.a.w == 0);
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}
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/**********************
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*** 0x0e: asl addr ***
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**********************
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cycles:
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[1 ] pbr,pc ; opcode
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[2 ] pbr,pc+1 ; aal
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[3 ] pbr,pc+2 ; aah
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[4 ] dbr,aa ; data low
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[4a] dbr,aa+1 ; data high [1]
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[5 ] dbr,aa+1 ; io
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[6a] dbr,aa+1 ; data high [1]
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[6 ] dbr,aa ; data low
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*/
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void bCPU::op_asl_addrb() {
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aa.l = op_read(); //2
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aa.h = op_read(); //3
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rd.l = op_read(OPMODE_DBR, aa.w); //4
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regs.p.c = !!(rd.l & 0x80);
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rd.l <<= 1;
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cpu_io(); //5
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op_write(OPMODE_DBR, aa.w, rd.l); //6
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regs.p.n = !!(rd.l & 0x80);
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regs.p.z = (rd.l == 0);
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}
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void bCPU::op_asl_addrw() {
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aa.l = op_read(); //2
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aa.h = op_read(); //3
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rd.l = op_read(OPMODE_DBR, aa.w); //4
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rd.h = op_read(OPMODE_DBR, aa.w + 1); //4a
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regs.p.c = !!(rd.w & 0x8000);
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rd.w <<= 1;
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cpu_io(); //5
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op_write(OPMODE_DBR, aa.w + 1, rd.h); //6a
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op_write(OPMODE_DBR, aa.w, rd.l); //6
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regs.p.n = !!(rd.w & 0x8000);
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regs.p.z = (rd.w == 0);
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}
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/************************
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*** 0x1e: asl addr,x ***
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************************
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cycles:
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[1 ] pbr,pc ; opcode
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[2 ] pbr,pc+1 ; aal
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[3 ] pbr,pc+2 ; aah
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[4 ] dbr,aah,aal+xl ; io
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[5 ] dbr,aa+x ; data low
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[5a] dbr,aa+x+1 ; data high [1]
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[6 ] dbr,aa+x+1 ; io
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[7a] dbr,aa+x+1 ; data high [1]
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[7 ] dbr,aa+x ; data low
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*/
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void bCPU::op_asl_addrxb() {
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aa.l = op_read(); //2
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aa.h = op_read(); //3
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cpu_io(); //4
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rd.l = op_read(OPMODE_DBR, aa.w + regs.x.w); //5
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regs.p.c = !!(rd.l & 0x80);
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rd.l <<= 1;
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cpu_io(); //6
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op_write(OPMODE_DBR, aa.w + regs.x.w, rd.l); //7
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regs.p.n = !!(rd.l & 0x80);
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regs.p.z = (rd.l == 0);
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}
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void bCPU::op_asl_addrxw() {
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aa.l = op_read(); //2
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aa.h = op_read(); //3
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cpu_io(); //4
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rd.l = op_read(OPMODE_DBR, aa.w + regs.x.w); //5
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rd.h = op_read(OPMODE_DBR, aa.w + regs.x.w + 1); //5a
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regs.p.c = !!(rd.w & 0x8000);
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rd.w <<= 1;
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cpu_io(); //6
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op_write(OPMODE_DBR, aa.w + regs.x.w + 1, rd.h); //7a
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op_write(OPMODE_DBR, aa.w + regs.x.w, rd.l); //7
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regs.p.n = !!(rd.w & 0x8000);
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regs.p.z = (rd.w == 0);
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}
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/********************
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*** 0x06: asl dp ***
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********************
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cycles:
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[1 ] pbr,pc ; opcode
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[2 ] pbr,pc+1 ; dp
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[2a] pbr,pc+1 ; io [2]
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[3 ] 0,d+dp ; data low
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[3a] 0,d+dp+1 ; data high [1]
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[4 ] 0,d+dp+1 ; io
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[5a] 0,d+dp+1 ; data high [1]
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[5 ] 0,d+dp ; data low
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*/
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void bCPU::op_asl_dpb() {
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dp = op_read(); //2
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cpu_c2(); //2a
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rd.l = op_read(OPMODE_DP, dp); //3
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regs.p.c = !!(rd.l & 0x80);
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rd.l <<= 1;
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cpu_io(); //4
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op_write(OPMODE_DP, dp, rd.l); //5
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regs.p.n = !!(rd.l & 0x80);
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regs.p.z = (rd.l == 0);
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}
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void bCPU::op_asl_dpw() {
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dp = op_read(); //2
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cpu_c2(); //2a
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rd.l = op_read(OPMODE_DP, dp); //3
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rd.h = op_read(OPMODE_DP, dp + 1); //3a
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regs.p.c = !!(rd.w & 0x8000);
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rd.w <<= 1;
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cpu_io(); //4
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op_write(OPMODE_DP, dp + 1, rd.h); //5a
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op_write(OPMODE_DP, dp, rd.l); //5
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regs.p.n = !!(rd.w & 0x8000);
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regs.p.z = (rd.w == 0);
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}
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/**********************
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*** 0x16: asl dp,x ***
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**********************
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cycles:
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[1 ] pbr,pc ; opcode
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[2 ] pbr,pc+1 ; dp
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[2a] pbr,pc+1 ; io [2]
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[3 ] pbr,pc+1 ; io
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[4 ] 0,d+dp+x ; data low
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[4a] 0,d+dp+x+1 ; data high [1]
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[5 ] 0,d+dp+x+1 ; io
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[6a] 0,d+dp+x+1 ; data high [1]
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[6 ] 0,d+dp+x ; data low
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*/
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void bCPU::op_asl_dpxb() {
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dp = op_read(); //2
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cpu_c2(); //2a
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cpu_io(); //3
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rd.l = op_read(OPMODE_DP, dp + regs.x.w); //4
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regs.p.c = !!(rd.l & 0x80);
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rd.l <<= 1;
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cpu_io(); //5
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op_write(OPMODE_DP, dp + regs.x.w, rd.l); //6
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regs.p.n = !!(rd.l & 0x80);
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regs.p.z = (rd.l == 0);
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}
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void bCPU::op_asl_dpxw() {
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dp = op_read(); //2
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cpu_c2(); //2a
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cpu_io(); //3
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rd.l = op_read(OPMODE_DP, dp + regs.x.w); //4
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rd.h = op_read(OPMODE_DP, dp + regs.x.w + 1); //4a
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regs.p.c = !!(rd.w & 0x8000);
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rd.w <<= 1;
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cpu_io(); //5
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op_write(OPMODE_DP, dp + regs.x.w + 1, rd.h); //6a
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op_write(OPMODE_DP, dp + regs.x.w, rd.l); //6
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regs.p.n = !!(rd.w & 0x8000);
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regs.p.z = (rd.w == 0);
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}
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/*****************
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*** 0x4a: lsr ***
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*****************
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cycles:
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[1] pbr,pc ; opcode
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[2] pbr,pc+1 ; io
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*/
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void bCPU::op_lsrb() {
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cpu_io(); //2
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regs.p.c = regs.a.l & 1;
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regs.a.l >>= 1;
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regs.p.n = !!(regs.a.l & 0x80);
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regs.p.z = (regs.a.l == 0);
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}
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void bCPU::op_lsrw() {
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cpu_io(); //2
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regs.p.c = regs.a.w & 1;
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regs.a.w >>= 1;
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regs.p.n = !!(regs.a.w & 0x8000);
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regs.p.z = (regs.a.w == 0);
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}
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/**********************
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*** 0x4e: lsr addr ***
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**********************
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cycles:
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[1 ] pbr,pc ; opcode
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[2 ] pbr,pc+1 ; aal
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[3 ] pbr,pc+2 ; aah
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[4 ] dbr,aa ; data low
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[4a] dbr,aa+1 ; data high [1]
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[5 ] dbr,aa+1 ; io
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[6a] dbr,aa+1 ; data high [1]
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[6 ] dbr,aa ; data low
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*/
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void bCPU::op_lsr_addrb() {
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aa.l = op_read(); //2
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aa.h = op_read(); //3
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rd.l = op_read(OPMODE_DBR, aa.w); //4
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regs.p.c = rd.l & 1;
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rd.l >>= 1;
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cpu_io(); //5
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op_write(OPMODE_DBR, aa.w, rd.l); //6
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regs.p.n = !!(rd.l & 0x80);
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regs.p.z = (rd.l == 0);
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}
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void bCPU::op_lsr_addrw() {
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aa.l = op_read(); //2
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aa.h = op_read(); //3
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rd.l = op_read(OPMODE_DBR, aa.w); //4
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rd.h = op_read(OPMODE_DBR, aa.w + 1); //4a
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regs.p.c = rd.w & 1;
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rd.w >>= 1;
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cpu_io(); //5
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op_write(OPMODE_DBR, aa.w + 1, rd.h); //6a
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op_write(OPMODE_DBR, aa.w, rd.l); //6
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regs.p.n = !!(rd.w & 0x8000);
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regs.p.z = (rd.w == 0);
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}
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/************************
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*** 0x5e: lsr addr,x ***
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************************
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cycles:
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[1 ] pbr,pc ; opcode
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[2 ] pbr,pc+1 ; aal
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[3 ] pbr,pc+2 ; aah
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[4 ] dbr,aah,aal+xl ; io
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[5 ] dbr,aa+x ; data low
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[5a] dbr,aa+x+1 ; data high [1]
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[6 ] dbr,aa+x+1 ; io
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[7a] dbr,aa+x+1 ; data high [1]
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[7 ] dbr,aa+x ; data low
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*/
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void bCPU::op_lsr_addrxb() {
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aa.l = op_read(); //2
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aa.h = op_read(); //3
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cpu_io(); //4
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rd.l = op_read(OPMODE_DBR, aa.w + regs.x.w); //5
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regs.p.c = rd.l & 1;
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rd.l >>= 1;
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cpu_io(); //6
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op_write(OPMODE_DBR, aa.w + regs.x.w, rd.l); //7
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regs.p.n = !!(rd.l & 0x80);
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regs.p.z = (rd.l == 0);
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}
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void bCPU::op_lsr_addrxw() {
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aa.l = op_read(); //2
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aa.h = op_read(); //3
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cpu_io(); //4
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rd.l = op_read(OPMODE_DBR, aa.w + regs.x.w); //5
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rd.h = op_read(OPMODE_DBR, aa.w + regs.x.w + 1); //5a
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regs.p.c = rd.w & 1;
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rd.w >>= 1;
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cpu_io(); //6
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op_write(OPMODE_DBR, aa.w + regs.x.w + 1, rd.h); //7a
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op_write(OPMODE_DBR, aa.w + regs.x.w, rd.l); //7
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regs.p.n = !!(rd.w & 0x8000);
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regs.p.z = (rd.w == 0);
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}
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/********************
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*** 0x46: lsr dp ***
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********************
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cycles:
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[1 ] pbr,pc ; opcode
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[2 ] pbr,pc+1 ; dp
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[2a] pbr,pc+1 ; io [2]
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[3 ] 0,d+dp ; data low
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[3a] 0,d+dp+1 ; data high [1]
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[4 ] 0,d+dp+1 ; io
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[5a] 0,d+dp+1 ; data high [1]
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[5 ] 0,d+dp ; data low
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*/
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void bCPU::op_lsr_dpb() {
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dp = op_read(); //2
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cpu_c2(); //2a
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rd.l = op_read(OPMODE_DP, dp); //3
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regs.p.c = rd.l & 1;
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rd.l >>= 1;
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cpu_io(); //4
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op_write(OPMODE_DP, dp, rd.l); //5
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regs.p.n = !!(rd.l & 0x80);
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regs.p.z = (rd.l == 0);
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}
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void bCPU::op_lsr_dpw() {
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dp = op_read(); //2
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cpu_c2(); //2a
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rd.l = op_read(OPMODE_DP, dp); //3
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rd.h = op_read(OPMODE_DP, dp + 1); //3a
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regs.p.c = rd.w & 1;
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rd.w >>= 1;
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cpu_io(); //4
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op_write(OPMODE_DP, dp + 1, rd.h); //5a
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op_write(OPMODE_DP, dp, rd.l); //5
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regs.p.n = !!(rd.w & 0x8000);
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regs.p.z = (rd.w == 0);
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}
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/**********************
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*** 0x56: lsr dp,x ***
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**********************
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cycles:
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[1 ] pbr,pc ; opcode
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[2 ] pbr,pc+1 ; dp
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[2a] pbr,pc+1 ; io [2]
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[3 ] pbr,pc+1 ; io
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[4 ] 0,d+dp+x ; data low
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[4a] 0,d+dp+x+1 ; data high [1]
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[5 ] 0,d+dp+x+1 ; io
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[6a] 0,d+dp+x+1 ; data high [1]
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[6 ] 0,d+dp+x ; data low
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*/
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void bCPU::op_lsr_dpxb() {
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dp = op_read(); //2
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cpu_c2(); //2a
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cpu_io(); //3
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rd.l = op_read(OPMODE_DP, dp + regs.x.w); //4
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regs.p.c = rd.l & 1;
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rd.l >>= 1;
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cpu_io(); //5
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op_write(OPMODE_DP, dp + regs.x.w, rd.l); //6
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regs.p.n = !!(rd.l & 0x80);
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regs.p.z = (rd.l == 0);
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}
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void bCPU::op_lsr_dpxw() {
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dp = op_read(); //2
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cpu_c2(); //2a
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cpu_io(); //3
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rd.l = op_read(OPMODE_DP, dp + regs.x.w); //4
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rd.h = op_read(OPMODE_DP, dp + regs.x.w + 1); //4a
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regs.p.c = rd.w & 1;
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rd.w >>= 1;
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cpu_io(); //5
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op_write(OPMODE_DP, dp + regs.x.w + 1, rd.h); //6a
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op_write(OPMODE_DP, dp + regs.x.w, rd.l); //6
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regs.p.n = !!(rd.w & 0x8000);
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regs.p.z = (rd.w == 0);
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}
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/*****************
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*** 0x2a: rol ***
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*****************
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cycles:
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[1] pbr,pc ; opcode
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[2] pbr,pc+1 ; io
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*/
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void bCPU::op_rolb() {
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uint8 c = regs.p.c;
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cpu_io(); //2
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regs.p.c = !!(regs.a.l & 0x80);
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regs.a.l <<= 1;
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regs.a.l |= c;
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regs.p.n = !!(regs.a.l & 0x80);
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regs.p.z = (regs.a.l == 0);
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}
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void bCPU::op_rolw() {
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uint16 c = regs.p.c;
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cpu_io(); //2
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regs.p.c = !!(regs.a.w & 0x8000);
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regs.a.w <<= 1;
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regs.a.w |= c;
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regs.p.n = !!(regs.a.w & 0x8000);
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regs.p.z = (regs.a.w == 0);
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}
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/**********************
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*** 0x2e: rol addr ***
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**********************
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cycles:
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[1 ] pbr,pc ; opcode
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[2 ] pbr,pc+1 ; aal
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[3 ] pbr,pc+2 ; aah
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[4 ] dbr,aa ; data low
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[4a] dbr,aa+1 ; data high [1]
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[5 ] dbr,aa+1 ; io
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[6a] dbr,aa+1 ; data high [1]
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[6 ] dbr,aa ; data low
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*/
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void bCPU::op_rol_addrb() {
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uint8 c = regs.p.c;
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aa.l = op_read(); //2
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aa.h = op_read(); //3
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rd.l = op_read(OPMODE_DBR, aa.w); //4
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regs.p.c = !!(rd.l & 0x80);
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rd.l <<= 1;
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rd.l |= c;
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cpu_io(); //5
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op_write(OPMODE_DBR, aa.w, rd.l); //6
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regs.p.n = !!(rd.l & 0x80);
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regs.p.z = (rd.l == 0);
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}
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void bCPU::op_rol_addrw() {
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uint16 c = regs.p.c;
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aa.l = op_read(); //2
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|
aa.h = op_read(); //3
|
|
rd.l = op_read(OPMODE_DBR, aa.w); //4
|
|
rd.h = op_read(OPMODE_DBR, aa.w + 1); //4a
|
|
regs.p.c = !!(rd.w & 0x8000);
|
|
rd.w <<= 1;
|
|
rd.w |= c;
|
|
cpu_io(); //5
|
|
op_write(OPMODE_DBR, aa.w + 1, rd.h); //6a
|
|
op_write(OPMODE_DBR, aa.w, rd.l); //6
|
|
regs.p.n = !!(rd.w & 0x8000);
|
|
regs.p.z = (rd.w == 0);
|
|
}
|
|
|
|
/************************
|
|
*** 0x3e: rol addr,x ***
|
|
************************
|
|
cycles:
|
|
[1 ] pbr,pc ; opcode
|
|
[2 ] pbr,pc+1 ; aal
|
|
[3 ] pbr,pc+2 ; aah
|
|
[4 ] dbr,aah,aal+xl ; io
|
|
[5 ] dbr,aa+x ; data low
|
|
[5a] dbr,aa+x+1 ; data high [1]
|
|
[6 ] dbr,aa+x+1 ; io
|
|
[7a] dbr,aa+x+1 ; data high [1]
|
|
[7 ] dbr,aa+x ; data low
|
|
*/
|
|
void bCPU::op_rol_addrxb() {
|
|
uint8 c = regs.p.c;
|
|
aa.l = op_read(); //2
|
|
aa.h = op_read(); //3
|
|
cpu_io(); //4
|
|
rd.l = op_read(OPMODE_DBR, aa.w + regs.x.w); //5
|
|
regs.p.c = !!(rd.l & 0x80);
|
|
rd.l <<= 1;
|
|
rd.l |= c;
|
|
cpu_io(); //6
|
|
op_write(OPMODE_DBR, aa.w + regs.x.w, rd.l); //7
|
|
regs.p.n = !!(rd.l & 0x80);
|
|
regs.p.z = (rd.l == 0);
|
|
}
|
|
|
|
void bCPU::op_rol_addrxw() {
|
|
uint16 c = regs.p.c;
|
|
aa.l = op_read(); //2
|
|
aa.h = op_read(); //3
|
|
cpu_io(); //4
|
|
rd.l = op_read(OPMODE_DBR, aa.w + regs.x.w); //5
|
|
rd.h = op_read(OPMODE_DBR, aa.w + regs.x.w + 1); //5a
|
|
regs.p.c = !!(rd.w & 0x8000);
|
|
rd.w <<= 1;
|
|
rd.w |= c;
|
|
cpu_io(); //6
|
|
op_write(OPMODE_DBR, aa.w + regs.x.w + 1, rd.h); //7a
|
|
op_write(OPMODE_DBR, aa.w + regs.x.w, rd.l); //7
|
|
regs.p.n = !!(rd.w & 0x8000);
|
|
regs.p.z = (rd.w == 0);
|
|
}
|
|
|
|
/********************
|
|
*** 0x26: rol dp ***
|
|
********************
|
|
cycles:
|
|
[1 ] pbr,pc ; opcode
|
|
[2 ] pbr,pc+1 ; dp
|
|
[2a] pbr,pc+1 ; io [2]
|
|
[3 ] 0,d+dp ; data low
|
|
[3a] 0,d+dp+1 ; data high [1]
|
|
[4 ] 0,d+dp+1 ; io
|
|
[5a] 0,d+dp+1 ; data high [1]
|
|
[5 ] 0,d+dp ; data low
|
|
*/
|
|
void bCPU::op_rol_dpb() {
|
|
uint8 c = regs.p.c;
|
|
dp = op_read(); //2
|
|
cpu_c2(); //2a
|
|
rd.l = op_read(OPMODE_DP, dp); //3
|
|
regs.p.c = !!(rd.l & 0x80);
|
|
rd.l <<= 1;
|
|
rd.l |= c;
|
|
cpu_io(); //4
|
|
op_write(OPMODE_DP, dp, rd.l); //5
|
|
regs.p.n = !!(rd.l & 0x80);
|
|
regs.p.z = (rd.l == 0);
|
|
}
|
|
|
|
void bCPU::op_rol_dpw() {
|
|
uint16 c = regs.p.c;
|
|
dp = op_read(); //2
|
|
cpu_c2(); //2a
|
|
rd.l = op_read(OPMODE_DP, dp); //3
|
|
rd.h = op_read(OPMODE_DP, dp + 1); //3a
|
|
regs.p.c = !!(rd.w & 0x8000);
|
|
rd.w <<= 1;
|
|
rd.w |= c;
|
|
cpu_io(); //4
|
|
op_write(OPMODE_DP, dp + 1, rd.h); //5a
|
|
op_write(OPMODE_DP, dp, rd.l); //5
|
|
regs.p.n = !!(rd.w & 0x8000);
|
|
regs.p.z = (rd.w == 0);
|
|
}
|
|
|
|
/**********************
|
|
*** 0x36: rol dp,x ***
|
|
**********************
|
|
cycles:
|
|
[1 ] pbr,pc ; opcode
|
|
[2 ] pbr,pc+1 ; dp
|
|
[2a] pbr,pc+1 ; io [2]
|
|
[3 ] pbr,pc+1 ; io
|
|
[4 ] 0,d+dp+x ; data low
|
|
[4a] 0,d+dp+x+1 ; data high [1]
|
|
[5 ] 0,d+dp+x+1 ; io
|
|
[6a] 0,d+dp+x+1 ; data high [1]
|
|
[6 ] 0,d+dp+x ; data low
|
|
*/
|
|
void bCPU::op_rol_dpxb() {
|
|
uint8 c = regs.p.c;
|
|
dp = op_read(); //2
|
|
cpu_c2(); //2a
|
|
cpu_io(); //3
|
|
rd.l = op_read(OPMODE_DP, dp + regs.x.w); //4
|
|
regs.p.c = !!(rd.l & 0x80);
|
|
rd.l <<= 1;
|
|
rd.l |= c;
|
|
cpu_io(); //5
|
|
op_write(OPMODE_DP, dp + regs.x.w, rd.l); //6
|
|
regs.p.n = !!(rd.l & 0x80);
|
|
regs.p.z = (rd.l == 0);
|
|
}
|
|
|
|
void bCPU::op_rol_dpxw() {
|
|
uint16 c = regs.p.c;
|
|
dp = op_read(); //2
|
|
cpu_c2(); //2a
|
|
cpu_io(); //3
|
|
rd.l = op_read(OPMODE_DP, dp + regs.x.w); //4
|
|
rd.h = op_read(OPMODE_DP, dp + regs.x.w + 1); //4a
|
|
regs.p.c = !!(rd.w & 0x8000);
|
|
rd.w <<= 1;
|
|
rd.w |= c;
|
|
cpu_io(); //5
|
|
op_write(OPMODE_DP, dp + regs.x.w + 1, rd.h); //6a
|
|
op_write(OPMODE_DP, dp + regs.x.w, rd.l); //6
|
|
regs.p.n = !!(rd.w & 0x8000);
|
|
regs.p.z = (rd.w == 0);
|
|
}
|
|
|
|
/*****************
|
|
*** 0x6a: ror ***
|
|
*****************
|
|
cycles:
|
|
[1] pbr,pc ; opcode
|
|
[2] pbr,pc+1 ; io
|
|
*/
|
|
void bCPU::op_rorb() {
|
|
uint8 c = (regs.p.c)?0x80:0;
|
|
cpu_io(); //2
|
|
regs.p.c = regs.a.l & 1;
|
|
regs.a.l >>= 1;
|
|
regs.a.l |= c;
|
|
regs.p.n = !!(regs.a.l & 0x80);
|
|
regs.p.z = (regs.a.l == 0);
|
|
}
|
|
|
|
void bCPU::op_rorw() {
|
|
uint16 c = (regs.p.c)?0x8000:0;
|
|
cpu_io(); //2
|
|
regs.p.c = regs.a.w & 1;
|
|
regs.a.w >>= 1;
|
|
regs.a.w |= c;
|
|
regs.p.n = !!(regs.a.w & 0x8000);
|
|
regs.p.z = (regs.a.w == 0);
|
|
}
|
|
|
|
/**********************
|
|
*** 0x6e: ror addr ***
|
|
**********************
|
|
cycles:
|
|
[1 ] pbr,pc ; opcode
|
|
[2 ] pbr,pc+1 ; aal
|
|
[3 ] pbr,pc+2 ; aah
|
|
[4 ] dbr,aa ; data low
|
|
[4a] dbr,aa+1 ; data high [1]
|
|
[5 ] dbr,aa+1 ; io
|
|
[6a] dbr,aa+1 ; data high [1]
|
|
[6 ] dbr,aa ; data low
|
|
*/
|
|
void bCPU::op_ror_addrb() {
|
|
uint8 c = (regs.p.c)?0x80:0;
|
|
aa.l = op_read(); //2
|
|
aa.h = op_read(); //3
|
|
rd.l = op_read(OPMODE_DBR, aa.w); //4
|
|
regs.p.c = rd.l & 1;
|
|
rd.l >>= 1;
|
|
rd.l |= c;
|
|
cpu_io(); //5
|
|
op_write(OPMODE_DBR, aa.w, rd.l); //6
|
|
regs.p.n = !!(rd.l & 0x80);
|
|
regs.p.z = (rd.l == 0);
|
|
}
|
|
|
|
void bCPU::op_ror_addrw() {
|
|
uint16 c = (regs.p.c)?0x8000:0;
|
|
aa.l = op_read(); //2
|
|
aa.h = op_read(); //3
|
|
rd.l = op_read(OPMODE_DBR, aa.w); //4
|
|
rd.h = op_read(OPMODE_DBR, aa.w + 1); //4a
|
|
regs.p.c = rd.w & 1;
|
|
rd.w >>= 1;
|
|
rd.w |= c;
|
|
cpu_io(); //5
|
|
op_write(OPMODE_DBR, aa.w + 1, rd.h); //6a
|
|
op_write(OPMODE_DBR, aa.w, rd.l); //6
|
|
regs.p.n = !!(rd.w & 0x8000);
|
|
regs.p.z = (rd.w == 0);
|
|
}
|
|
|
|
/************************
|
|
*** 0x7e: ror addr,x ***
|
|
************************
|
|
cycles:
|
|
[1 ] pbr,pc ; opcode
|
|
[2 ] pbr,pc+1 ; aal
|
|
[3 ] pbr,pc+2 ; aah
|
|
[4 ] dbr,aah,aal+xl ; io
|
|
[5 ] dbr,aa+x ; data low
|
|
[5a] dbr,aa+x+1 ; data high [1]
|
|
[6 ] dbr,aa+x+1 ; io
|
|
[7a] dbr,aa+x+1 ; data high [1]
|
|
[7 ] dbr,aa+x ; data low
|
|
*/
|
|
void bCPU::op_ror_addrxb() {
|
|
uint8 c = (regs.p.c)?0x80:0;
|
|
aa.l = op_read(); //2
|
|
aa.h = op_read(); //3
|
|
cpu_io(); //4
|
|
rd.l = op_read(OPMODE_DBR, aa.w + regs.x.w); //5
|
|
regs.p.c = rd.l & 1;
|
|
rd.l >>= 1;
|
|
rd.l |= c;
|
|
cpu_io(); //6
|
|
op_write(OPMODE_DBR, aa.w + regs.x.w, rd.l); //7
|
|
regs.p.n = !!(rd.l & 0x80);
|
|
regs.p.z = (rd.l == 0);
|
|
}
|
|
|
|
void bCPU::op_ror_addrxw() {
|
|
uint16 c = (regs.p.c)?0x8000:0;
|
|
aa.l = op_read(); //2
|
|
aa.h = op_read(); //3
|
|
cpu_io(); //4
|
|
rd.l = op_read(OPMODE_DBR, aa.w + regs.x.w); //5
|
|
rd.h = op_read(OPMODE_DBR, aa.w + regs.x.w + 1); //5a
|
|
regs.p.c = rd.w & 1;
|
|
rd.w >>= 1;
|
|
rd.w |= c;
|
|
cpu_io(); //6
|
|
op_write(OPMODE_DBR, aa.w + regs.x.w + 1, rd.h); //7a
|
|
op_write(OPMODE_DBR, aa.w + regs.x.w, rd.l); //7
|
|
regs.p.n = !!(rd.w & 0x8000);
|
|
regs.p.z = (rd.w == 0);
|
|
}
|
|
|
|
/********************
|
|
*** 0x66: ror dp ***
|
|
********************
|
|
cycles:
|
|
[1 ] pbr,pc ; opcode
|
|
[2 ] pbr,pc+1 ; dp
|
|
[2a] pbr,pc+1 ; io [2]
|
|
[3 ] 0,d+dp ; data low
|
|
[3a] 0,d+dp+1 ; data high [1]
|
|
[4 ] 0,d+dp+1 ; io
|
|
[5a] 0,d+dp+1 ; data high [1]
|
|
[5 ] 0,d+dp ; data low
|
|
*/
|
|
void bCPU::op_ror_dpb() {
|
|
uint8 c = (regs.p.c)?0x80:0;
|
|
dp = op_read(); //2
|
|
cpu_c2(); //2a
|
|
rd.l = op_read(OPMODE_DP, dp); //3
|
|
regs.p.c = rd.l & 1;
|
|
rd.l >>= 1;
|
|
rd.l |= c;
|
|
cpu_io(); //4
|
|
op_write(OPMODE_DP, dp, rd.l); //5
|
|
regs.p.n = !!(rd.l & 0x80);
|
|
regs.p.z = (rd.l == 0);
|
|
}
|
|
|
|
void bCPU::op_ror_dpw() {
|
|
uint16 c = (regs.p.c)?0x8000:0;
|
|
dp = op_read(); //2
|
|
cpu_c2(); //2a
|
|
rd.l = op_read(OPMODE_DP, dp); //3
|
|
rd.h = op_read(OPMODE_DP, dp + 1); //3a
|
|
regs.p.c = rd.w & 1;
|
|
rd.w >>= 1;
|
|
rd.w |= c;
|
|
cpu_io(); //4
|
|
op_write(OPMODE_DP, dp + 1, rd.h); //5a
|
|
op_write(OPMODE_DP, dp, rd.l); //5
|
|
regs.p.n = !!(rd.w & 0x8000);
|
|
regs.p.z = (rd.w == 0);
|
|
}
|
|
|
|
/**********************
|
|
*** 0x76: ror dp,x ***
|
|
**********************
|
|
cycles:
|
|
[1 ] pbr,pc ; opcode
|
|
[2 ] pbr,pc+1 ; dp
|
|
[2a] pbr,pc+1 ; io [2]
|
|
[3 ] pbr,pc+1 ; io
|
|
[4 ] 0,d+dp+x ; data low
|
|
[4a] 0,d+dp+x+1 ; data high [1]
|
|
[5 ] 0,d+dp+x+1 ; io
|
|
[6a] 0,d+dp+x+1 ; data high [1]
|
|
[6 ] 0,d+dp+x ; data low
|
|
*/
|
|
void bCPU::op_ror_dpxb() {
|
|
uint8 c = (regs.p.c)?0x80:0;
|
|
dp = op_read(); //2
|
|
cpu_c2(); //2a
|
|
cpu_io(); //3
|
|
rd.l = op_read(OPMODE_DP, dp + regs.x.w); //4
|
|
regs.p.c = rd.l & 1;
|
|
rd.l >>= 1;
|
|
rd.l |= c;
|
|
cpu_io(); //5
|
|
op_write(OPMODE_DP, dp + regs.x.w, rd.l); //6
|
|
regs.p.n = !!(rd.l & 0x80);
|
|
regs.p.z = (rd.l == 0);
|
|
}
|
|
|
|
void bCPU::op_ror_dpxw() {
|
|
uint16 c = (regs.p.c)?0x8000:0;
|
|
dp = op_read(); //2
|
|
cpu_c2(); //2a
|
|
cpu_io(); //3
|
|
rd.l = op_read(OPMODE_DP, dp + regs.x.w); //4
|
|
rd.h = op_read(OPMODE_DP, dp + regs.x.w + 1); //4a
|
|
regs.p.c = rd.w & 1;
|
|
rd.w >>= 1;
|
|
rd.w |= c;
|
|
cpu_io(); //5
|
|
op_write(OPMODE_DP, dp + regs.x.w + 1, rd.h); //6a
|
|
op_write(OPMODE_DP, dp + regs.x.w, rd.l); //6
|
|
regs.p.n = !!(rd.w & 0x8000);
|
|
regs.p.z = (rd.w == 0);
|
|
}
|