mirror of
https://github.com/bsnes-emu/bsnes.git
synced 2025-10-04 15:51:50 +02:00
byuu says: Changelog: - fixed LYC interrupt at LY=0 (fixes Makai Toushi SaGa) - fixed MBC3 ROM bank mapping (fixes Harvest Moon GBC) - added Super Game Boy MLT_REQ support to JOYP, needed for ICD2-R emulation - temporarily changed System::run() to execute only four cycles before exiting for bsnes, will make two versions later - uses actual boot ROMs, has DMG+SGB1 for now. Need SGB2, don't care about CGB. Defaults to SGB1, no way to select just yet. DMG 4-second wait is annoying. Does not force games to act like SGB on bgameboy itself, because that has no ICD2 and fails the required MLT_REQ check
82 lines
1.7 KiB
C++
Executable File
82 lines
1.7 KiB
C++
Executable File
//4194304hz (4 * 1024 * 1024)
|
|
//70224 clocks/frame
|
|
// 456 clocks/scanline
|
|
// 154 scanlines/frame
|
|
|
|
//4194304 / 4096 = 1024
|
|
//4194304 / 262144 = 16
|
|
//4194304 / 65536 = 64
|
|
//4394304 / 16384 = 256
|
|
|
|
#ifdef CPU_CPP
|
|
|
|
#include "opcode.cpp"
|
|
|
|
void CPU::add_clocks(unsigned clocks) {
|
|
system.clocks_executed += clocks;
|
|
scheduler.exit();
|
|
|
|
status.clock += clocks;
|
|
if(status.clock >= 4 * 1024 * 1024) {
|
|
status.clock -= 4 * 1024 * 1024;
|
|
cartridge.mbc3.second();
|
|
}
|
|
|
|
status.timer0 += clocks;
|
|
if(status.timer0 >= 16) timer_stage0();
|
|
|
|
cpu.clock += clocks;
|
|
if(cpu.clock >= 0) co_switch(scheduler.active_thread = lcd.thread);
|
|
}
|
|
|
|
void CPU::timer_stage0() { //262144hz
|
|
if(status.timer_enable && status.timer_clock == 1) {
|
|
if(++status.tima == 0) {
|
|
status.tima = status.tma;
|
|
interrupt_raise(Interrupt::Timer);
|
|
}
|
|
}
|
|
|
|
status.timer0 -= 16;
|
|
if(++status.timer1 >= 4) timer_stage1();
|
|
}
|
|
|
|
void CPU::timer_stage1() { // 65536hz
|
|
if(status.timer_enable && status.timer_clock == 2) {
|
|
if(++status.tima == 0) {
|
|
status.tima = status.tma;
|
|
interrupt_raise(Interrupt::Timer);
|
|
}
|
|
}
|
|
|
|
status.timer1 -= 4;
|
|
if(++status.timer2 >= 4) timer_stage2();
|
|
}
|
|
|
|
void CPU::timer_stage2() { // 16384hz
|
|
if(status.timer_enable && status.timer_clock == 3) {
|
|
if(++status.tima == 0) {
|
|
status.tima = status.tma;
|
|
interrupt_raise(Interrupt::Timer);
|
|
}
|
|
}
|
|
|
|
status.div++;
|
|
|
|
status.timer2 -= 4;
|
|
if(++status.timer3 >= 4) timer_stage3();
|
|
}
|
|
|
|
void CPU::timer_stage3() { // 4096hz
|
|
if(status.timer_enable && status.timer_clock == 0) {
|
|
if(++status.tima == 0) {
|
|
status.tima = status.tma;
|
|
interrupt_raise(Interrupt::Timer);
|
|
}
|
|
}
|
|
|
|
status.timer3 -= 4;
|
|
}
|
|
|
|
#endif
|