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https://github.com/nophead/Mendel90.git
synced 2025-01-17 04:48:15 +01:00
Can now make a single STL regardless of whether it is on the BOM.
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parent
3e16e05231
commit
1e86cd17aa
31
stls.py
31
stls.py
@ -11,8 +11,10 @@ def stls(machine, parts = None):
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#
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#
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target_dir = machine + "/stls"
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target_dir = machine + "/stls"
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if os.path.isdir(target_dir):
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if os.path.isdir(target_dir):
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shutil.rmtree(target_dir)
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if not parts:
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os.makedirs(target_dir)
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shutil.rmtree(target_dir)
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else:
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os.makedirs(target_dir)
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#
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#
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# Set the target machine
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# Set the target machine
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@ -24,16 +26,16 @@ def stls(machine, parts = None):
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#
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#
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# Make a list of all the stls in the BOM
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# Make a list of all the stls in the BOM
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#
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#
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targets = []
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if parts:
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for line in open(machine + "/bom/bom.txt", "rt").readlines():
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targets = parts
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words = line.split()
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else:
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if words:
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targets = []
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last_word = words[-1]
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for line in open(machine + "/bom/bom.txt", "rt").readlines():
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if len(last_word) > 4 and last_word[-4:] == ".stl":
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words = line.split()
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if not parts or (last_word in parts):
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if words:
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targets.append(last_word.replace(".stl", "_stl"))
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last_word = words[-1]
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if len(last_word) > 4 and last_word[-4:] == ".stl":
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targets.append(last_word)
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#
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#
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# Find all the scad files
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# Find all the scad files
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#
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#
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@ -46,7 +48,8 @@ def stls(machine, parts = None):
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words = line.split()
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words = line.split()
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if(len(words) and words[0] == "module"):
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if(len(words) and words[0] == "module"):
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module = words[1].split('(')[0]
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module = words[1].split('(')[0]
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if module in targets:
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stl = module.replace("_stl", ".stl")
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if stl in targets:
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#
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#
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# make a file to use the module
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# make a file to use the module
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#
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#
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@ -60,7 +63,7 @@ def stls(machine, parts = None):
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#
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#
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stl_name = target_dir + "/" + module[:-4] + ".stl"
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stl_name = target_dir + "/" + module[:-4] + ".stl"
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openscad.run("-o", stl_name, stl_maker_name)
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openscad.run("-o", stl_name, stl_maker_name)
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targets.remove(module)
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targets.remove(stl)
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#
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#
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# List the ones we didn't find
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# List the ones we didn't find
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