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Module blurb parenthesis parsing is now greedy to handle args that default to function calls.

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This means that library modules cannot be one liners.
This commit is contained in:
Chris Palmer
2021-09-27 16:17:08 +01:00
parent c6b280f0e8
commit 4993c3e82d
12 changed files with 86 additions and 36 deletions
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3
vitamins/pcb.scad
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@@ -1109,7 +1109,8 @@ module pcb_grid_components(type, components, cutouts = false, angle = undef) //!
}
module pcb_cutouts(type, angle = undef) pcb_components(type, true, angle); //! Make cut outs to clear components on a PCB
module pcb_cutouts(type, angle = undef) //! Make cut outs to clear components on a PCB
pcb_components(type, true, angle);
module pcb_grid_positions(type) {
grid = pcb_grid(type);

3
vitamins/veroboard.scad
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@@ -141,7 +141,8 @@ module vero_components(type, cutouts = false, angle = undef)
translate_z(vero_thickness(type))
pcb_component(comp, cutouts, angle);
module vero_cutouts(type, angle = undef) vero_components(type, true, angle); //! Make cutouts to clear components
module vero_cutouts(type, angle = undef) //! Make cutouts to clear components
vero_components(type, true, angle);
module veroboard_assembly(type, height, thickness, flip = false, ngb = false) //! Draw the assembly with components and fasteners in place
assembly(vero_assembly(type), ngb = ngb) {