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Fix m3_scx_high_5_bits on DMG
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@@ -25,7 +25,7 @@ typedef enum {
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GB_CONFLICT_LCDC_CGB_DOUBLE,
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GB_CONFLICT_STAT_CGB_DOUBLE,
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GB_CONFLICT_NR10_CGB_DOUBLE,
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GB_CONFLICT_SCX_CGB_DOUBLE,
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GB_CONFLICT_SCX_DMG_AND_CGB_DOUBLE,
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} conflict_t;
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static const conflict_t cgb_conflict_map[0x80] = {
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@@ -48,7 +48,7 @@ static const conflict_t cgb_double_conflict_map[0x80] = {
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[GB_IO_WY] = GB_CONFLICT_READ_OLD,
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[GB_IO_STAT] = GB_CONFLICT_STAT_CGB_DOUBLE,
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[GB_IO_NR10] = GB_CONFLICT_NR10_CGB_DOUBLE,
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[GB_IO_SCX] = GB_CONFLICT_SCX_CGB_DOUBLE,
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[GB_IO_SCX] = GB_CONFLICT_SCX_DMG_AND_CGB_DOUBLE,
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[GB_IO_WX] = GB_CONFLICT_READ_OLD,
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};
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@@ -59,15 +59,12 @@ static const conflict_t dmg_conflict_map[0x80] = {
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[GB_IO_LCDC] = GB_CONFLICT_DMG_LCDC,
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[GB_IO_SCY] = GB_CONFLICT_READ_NEW,
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[GB_IO_STAT] = GB_CONFLICT_STAT_DMG,
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[GB_IO_BGP] = GB_CONFLICT_PALETTE_DMG,
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[GB_IO_OBP0] = GB_CONFLICT_PALETTE_DMG,
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[GB_IO_OBP1] = GB_CONFLICT_PALETTE_DMG,
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[GB_IO_WY] = GB_CONFLICT_READ_OLD,
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[GB_IO_WX] = GB_CONFLICT_WX_DMG,
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/* Todo: these were not verified at all */
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[GB_IO_SCX] = GB_CONFLICT_READ_NEW,
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[GB_IO_SCX] = GB_CONFLICT_SCX_DMG_AND_CGB_DOUBLE,
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};
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/* Todo: Verify on an SGB1 */
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@@ -77,15 +74,12 @@ static const conflict_t sgb_conflict_map[0x80] = {
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[GB_IO_LCDC] = GB_CONFLICT_SGB_LCDC,
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[GB_IO_SCY] = GB_CONFLICT_READ_NEW,
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[GB_IO_STAT] = GB_CONFLICT_STAT_DMG,
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[GB_IO_BGP] = GB_CONFLICT_READ_NEW,
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[GB_IO_OBP0] = GB_CONFLICT_READ_NEW,
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[GB_IO_OBP1] = GB_CONFLICT_READ_NEW,
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[GB_IO_WY] = GB_CONFLICT_READ_OLD,
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[GB_IO_WX] = GB_CONFLICT_WX_DMG,
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/* Todo: these were not verified at all */
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[GB_IO_SCX] = GB_CONFLICT_READ_NEW,
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[GB_IO_SCX] = GB_CONFLICT_SCX_DMG_AND_CGB_DOUBLE,
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};
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static uint8_t cycle_read(GB_gameboy_t *gb, uint16_t addr)
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@@ -302,7 +296,7 @@ static void cycle_write(GB_gameboy_t *gb, uint16_t addr, uint8_t value)
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break;
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}
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case GB_CONFLICT_SCX_CGB_DOUBLE:
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case GB_CONFLICT_SCX_DMG_AND_CGB_DOUBLE:
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GB_advance_cycles(gb, gb->pending_cycles - 2);
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GB_write_memory(gb, addr, value);
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gb->pending_cycles = 6;
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