Update to bsnes v046 release.

Unfortunately, I was not able to include any actual Super Game Boy support in this release. I was however able to back-port all other changes since v045, as well as add a lot of new stuff. Though there are few visible changes from the last release, internally much has changed. I'm releasing this mostly as a point release whilst everything should be stable.
I've decided to support the Super Game Boy via external DLL (or SO for Linux users.) There are many reasons for this. Most notably is that the largest special chip in bsnes right now weighs in at ~30kb of code. Emulating an entire Game Boy, not including the SGB enhancements, would require an additional ~800kb of code, or nearly half the size of the entire SNES emulation core. Add to that potential issues with licensing, conflicts with the build process / namespace, a significant increase to build time, and a lack of flexibility over which Game Boy emulator to use, and it's pretty clear that this is something best left external. At least until we have a fully trimmed, fully working SGB emulator available.
The way this will work is bsnes will look for SuperGameBoy.(dll,so), and if present, it will call out to pre-defined functions. Users will need the SGB BIOS loaded, at which point they can select a Game Boy cartridge, and bsnes will use the DLL for actual emulation. Sadly I don't have a working DLL ready for this release, and even if I did, there's no sound bridge yet for the Game Boy audio.
Other than that, much of the core has been updated in an attempt to make the core more library-like. It still has a few major limitations: it requires libco (which is not portable) and nall (which is quite large), and only one instance can be instantiated as all of the base objects are pre-defined and inter-linked. Not that I can imagine any practical use for multiple simultaneous SNES emulators anyway ...
Changelog:
    - Save RAM is now automatically saved once per minute
    - Added delay to Super Scope / Justifier latching to fix X-Zone
    - Fixed an edge case in CPU<>PPU counter history
    - S-CPU can now run up to one full scanline ahead of S-PPU before syncing
    - Added interface for Super Game Boy support (no emulation yet)
    - Fixed a bug with path selection not adding trailing slash
    - All S-SMP opcodes re-written to use new pre-processor
    - Entire core encapsulated into SNES namespace
    - Core accepts files via memory only; zlib and libjma moved outside of core
    - Major Makefile restructuring: it's now possible to build with just "make" alone
    - Linux: libxtst / inputproto is no longer required for compilation
    - Lots of additional code cleanup

license.txt

@@ -1,86 +0,0 @@
-bsnes (TM) Reference License
-Copyright (C) 2004 - 2008 byuu
-All rights reserved
-
-1. Definitions
-
-The terms "reproduce", "reproduction", "distribute" and "distribution" have the
-same meaning here as under U.S. copyright law.
-
-"The software" means this software package as a whole, including, but not
-limited to, this license, binaries, source code, documentation, and data.
-
-"You" means the licensee of the software.
-
-"The licensor" means the copyright holder of the software, byuu.
-
-2. Grant of Rights
-
-Subject to the terms of this license, the licensor grants you a
-non-transferable, non-exclusive, worldwide, royalty-free copyright license to
-reproduce the software for non-commercial use only, provided the software
-remains unmodified, and there is no charge for the software itself, its' use,
-nor for the medium upon which the software is distributed. The reproduction of
-modified or derivative works of the software is strictly prohibited, except when
-transmitted solely to the licensor.
-
-3. Limitations
-
-This license does not grant you any rights to use the licensor's name, logo or
-trademarks.
-
-The software is provided "as is", and any express or implied warranties,
-including, but not limited to, the implied warranties of merchantability and
-fitness for a particular purpose are disclaimed. In no event shall the licensor
-be liable for any direct, indirect, incidental, special, exemplary, or
-consequential damages (including, but not limited to, procurement of substitute
-goods or services; loss of use, data, or profits; or business interruption)
-however caused and on any theory of liability, whether in contract, strict
-liability, or tort (including negligence or otherwise) arising in any way out of
-the use of the software, even if advised of the possibility of such damage.
-
-In the event that this license is determined to be invalid or unenforceable, the
-Grant of Rights will become null and void, and no rights shall be granted to the
-licensee, within the scope of U.S. copyright law.
-
-4. Exemptions
-
-The software includes the work of other copyright holders, which is licensed
-under different agreements, and exempt from this license. Below is a complete
-list of all such software, and their respective copyright holders and licenses.
-Further, respective source code files are labeled with their correct licensing
-information in the header. The lack of such a header indicates said file falls
-under the bsnes license.
-
-HQ2x filter, author: MaxST, license: LGPL
-JMA decompressor, author: NSRT Team, license: GPL (*)
-NTSC filter, author: blargg, license: LGPL
-zlib decompressor, license: zlib license
-
-(*) bsnes has received an exemption from the copyright holder to use this work.
-
-The software also includes works which have been released to the public domain,
-which are not bound to any licensing agreements. Below is a complete list of all
-such software.
-
-libco, author: byuu
-libui, author: byuu
-OBC-1 emu, author: byuu
-S-DD1 emu, author: Andreas Naive
-S-RTC emu, author: byuu
-
-Any software listed above as exemptions may be relicensed individually from
-bsnes under their respective terms. However, no bsnes licensed portions can be
-combined with such a derivative work.
-
-The software also includes the work of other copyright holders, which is
-licensed under the terms of the bsnes license, with permission to do so from the
-respective authors. Below is a complete list of all such software.
-
-Cx4 emu, authors: anomie, Overload, zsKnight, Nach
-DSP-1 emu, authors: Overload, John Weidman, Neviksti, Andreas Naive
-DSP-2 emu, author: Overload
-DSP-3 emu, authors: John Weidman, Kris Bleakley, Lancer, z80 gaiden
-DSP-4 emu, authors: Dreamer Nom, John Weidman, Kris Bleakley, Nach, z80 gaiden
-S-DSP emu, author: blargg
-ST-010 emu, authors: John Weidman, Matthew Kendora, Overload, Feather

readme.txt

@@ -1,100 +0,0 @@
-bsnes
-Version: 0.032
-Author: byuu
-
---------
-General:
---------
-bsnes is a Super Nintendo / Super Famicom emulator that began on
-October 14th, 2004.
-
-The latest version can be downloaded from:
-http://byuu.org/
-
-Please see license.txt for important licensing information.
-
---------------
-Configuration:
---------------
-bsnes has two configuration files: bsnes.cfg, for program settings; and
-locale.cfg, for localization.
-
-For each file, bsnes will start by looking inside the same folder where the
-bsnes executable is located. If said file is not found, it will then check your
-user profile folder. On Windows, this is located at "%APPDATA%/.bsnes". On all
-other operating systems, this is located at "~/.bsnes". If said file is still
-not found, it will automatically be created in your user profile folder.
-
-If you wish to use bsnes in single-user mode, be sure that both files exist
-inside the same folder as the bsnes executable. If they do not, you can simply
-create new blank files and bsnes will use them in the future.
-
-If you wish to use bsnes in multi-user mode, simply delete these two files from
-the bsnes executable directory if they exist.
-
-If you wish to have multiple configuration profiles for the same user, you will
-need to make copies of the bsnes executable, and use each one in single-user
-mode.
-
-------------------
-Known Limitations:
-------------------
-S-CPU
-- Multiply / divide register delays not implemented
-
-S-PPU
-- Uses scanline-based renderer. This is very inaccurate, but few (if any)
-  games rely on mid-scanline writes to function correctly
-- Does not support FirstSprite+Y priority
-- OAM / CGRAM accesses during active display not supported correctly
-- RTO flags are not calculated on frames that are skipped when frameskipping
-  is enabled. This provides a major speedup, however it will cause in issues
-  in games that test these flags, eg the SNES Test Program Electronics Test.
-  Turning frameskipping off will allow RTO flag calculation on every frame
-
-Hardware Bugs
-- S-CPU.r1 HDMA crashing bug not emulated
-- S-CPU<>S-SMP communication bus conflicts not emulated
-
----------------------
-Unsupported Hardware:
----------------------
-SA-1
-Coprocessor used in many popular games, including:
-- Dragon Ball Z Hyper Dimension
-- Kirby Super Star
-- Kirby's Dreamland 3
-- Marvelous
-- SD Gundam G-NEXT
-- Super Mario RPG
-
-Super FX
-Coprocessor used in many popular games, including:
-- Doom
-- Star Fox
-- Star Fox 2 (unreleased beta)
-- Super Mario World 2: Yoshi's Island
-
-SPC7110
-Coprocessor used only by the following games:
-- Far East of Eden Zero
-- Far East of Eden Zero: Shounen Jump no Shou
-- Momotarou Densetsu Happy
-- Super Power League 4
-
-ST-011
-SETA DSP used by Quick-move Shogi Match with Nidan Rank-holder Morita
-
-ST-018
-SETA RISC CPU used by Quick-move Shogi Match with Nidan Rank-holder Morita 2
-
-Super Gameboy
-Cartridge passthrough used for playing Gameboy games
-
-------------------------
-Unsupported Controllers:
-------------------------
-Mouse
-Super Scope
-Justifier
-Multitap (4-port and 5-port)

src/Makefile

@@ -1,55 +1,40 @@
-include lib/nall/Makefile.string
-prefix = /usr/local
+include lib/nall/Makefile
+ui = ui_qt
 
 ################
 ### compiler ###
 ################
 
-ifneq ($(findstring gcc,$(compiler)),) # GCC family
-  flags = -O3 -fomit-frame-pointer -Ilib
-  c = $(compiler) $(flags)
-  cpp = $(subst cc,++,$(compiler)) $(flags)
-  obj = o
-  rule = -c $< -o $@
-  link = -s
-  mkbin = -o$1
-  mkdef = -D$1
-  mklib = -l$1
-else ifeq ($(compiler),cl) # Visual C++
-  flags = /nologo /wd4355 /wd4996 /O2 /EHsc /Ilib
-  c = cl $(flags)
-  cpp = cl $(flags)
-  obj = obj
-  rule = /c $< /Fo$@
-  link = /link
-  mkbin = /Fe$1
-  mkdef = /D$1
-  mklib = $1.lib
-else
-  unknown_compiler: help;
-endif
+c     := $(compiler)
+cpp   := $(subst cc,++,$(compiler))
+flags := -O3 -fomit-frame-pointer -Ilib
+link  := -s
 
-##########
-### os ###
-##########
+# profile-guided instrumentation:
+# flags += -fprofile-generate
+# link += -lgcov
 
-ifeq ($(platform),x) # X11
-  ruby = video.glx video.xv video.sdl audio.openal audio.oss audio.alsa audio.ao input.sdl input.x
-  link += `pkg-config --libs gtk+-2.0`
-  link += $(call mklib,Xtst)
-  delete = rm -f $1
-else ifeq ($(platform),win) # Windows
-  ruby = video.direct3d video.wgl video.directdraw video.gdi audio.directsound input.directinput
-  link += $(if $(findstring mingw,$(compiler)),-mwindows)
-  link += $(call mklib,uuid)
-  link += $(call mklib,kernel32)
-  link += $(call mklib,user32)
-  link += $(call mklib,gdi32)
-  link += $(call mklib,shell32)
-  link += $(call mklib,winmm)
-  link += $(call mklib,comdlg32)
-  link += $(call mklib,comctl32)
-  delete = $(if $(findstring i586-mingw-gcc,$(compiler)),rm -f $1,del $(subst /,\,$1))
+# profile-guided optimization:
+flags += -fprofile-use
+
+################
+### platform ###
+################
+
+ifeq ($(platform),x)
+  ruby := video.glx video.xv video.sdl
+  ruby += audio.alsa audio.openal audio.oss audio.pulseaudio audio.ao
+  ruby += input.sdl input.x
+else ifeq ($(platform),win)
+  ruby := video.direct3d video.wgl video.directdraw video.gdi
+  ruby += audio.directsound
+  ruby += input.rawinput input.directinput
+
+  link += -mwindows
+# link += -mconsole
+  link += -luuid -lkernel32 -luser32 -lgdi32 -lshell32
+  # statically link Qt for Windows build
+  link += -enable-stdcall-fixup -Wl,-s -Wl,-enable-auto-import -Wl,-enable-runtime-pseudo-reloc
 else
   unknown_platform: help;
 endif
@@ -58,199 +43,188 @@ endif
 ### ruby ###
 ############
 
-rubyflags =
-rubyflags += $(if $(findstring .sdl,$(ruby)),`sdl-config --cflags`)
+rubyflags = $(call ifhas,.sdl,$(ruby),`sdl-config --cflags`)
 
-link += $(if $(findstring video.direct3d,$(ruby)),$(call mklib,d3d9))
-link += $(if $(findstring video.directdraw,$(ruby)),$(call mklib,ddraw))
-link += $(if $(findstring video.glx,$(ruby)),$(call mklib,GL))
-link += $(if $(findstring video.wgl,$(ruby)),$(call mklib,opengl32))
-link += $(if $(findstring video.xv,$(ruby)),$(call mklib,Xv))
-link += $(if $(findstring audio.alsa,$(ruby)),$(call mklib,asound))
-link += $(if $(findstring audio.ao,$(ruby)),$(call mklib,ao))
-link += $(if $(findstring audio.directsound,$(ruby)),$(call mklib,dsound))
-link += $(if $(findstring audio.openal,$(ruby)),$(if $(call streq,$(platform),x),$(call mklib,openal),$(call mklib,openal32)))
-link += $(if $(findstring input.directinput,$(ruby)),$(call mklib,dinput8) $(call mklib,dxguid))
-link += $(if $(findstring input.sdl,$(ruby)),`sdl-config --libs`)
+link += $(call ifhas,.sdl,$(ruby),`sdl-config --libs`)
+link += $(call ifhas,video.direct3d,$(ruby),-ld3d9)
+link += $(call ifhas,video.directdraw,$(ruby),-lddraw)
+link += $(call ifhas,video.glx,$(ruby),-lGL)
+link += $(call ifhas,video.wgl,$(ruby),-lopengl32)
+link += $(call ifhas,video.xv,$(ruby),-lXv)
+link += $(call ifhas,audio.alsa,$(ruby),-lasound)
+link += $(call ifhas,audio.ao,$(ruby),-lao)
+link += $(call ifhas,audio.directsound,$(ruby),-ldsound)
+link += $(call ifhas,audio.openal,$(ruby),$(if $(call streq,$(platform),x),-lopenal,-lopenal32))
+link += $(call ifhas,audio.pulseaudio,$(ruby),-lpulse-simple)
+link += $(call ifhas,input.directinput,$(ruby),-ldinput8 -ldxguid)
+link += $(call ifhas,input.rawinput,$(ruby),-lxinput -ldinput8 -ldxguid)
 
-####################################
-### main target and dependencies ###
-####################################
+####################
+### core objects ###
+####################
 
-objects = main libco hiro ruby libfilter string reader cart cheat \
-  memory smemory cpu scpu smp ssmp sdsp ppu bppu snes \
-  bsx srtc sdd1 cx4 dsp1 dsp2 dsp3 dsp4 obc1 st010
+objects = libco ruby libreader libfilter string \
+  system cartridge cheat \
+  memory smemory cpu cpucore scpu smp smpcore ssmp sdsp ppu bppu \
+  sgb sa1 bsx srtc sdd1 spc7110 cx4 dsp1 dsp2 dsp3 dsp4 obc1 st010
 
 ifeq ($(enable_gzip),true)
   objects += adler32 compress crc32 deflate gzio inffast inflate inftrees ioapi trees unzip zip zutil
-  flags += $(call mkdef,GZIP_SUPPORT)
+  flags += -DGZIP_SUPPORT
 endif
 
 ifeq ($(enable_jma),true)
   objects += jma jcrc32 lzmadec 7zlzma iiostrm inbyte lzma winout
-  flags += $(call mkdef,JMA_SUPPORT)
+  flags += -DJMA_SUPPORT
 endif
 
-objects := $(patsubst %,obj/%.$(obj),$(objects))
-rubydef := $(foreach c,$(subst .,_,$(call strupper,$(ruby))),$(call mkdef,$c))
-
-# Windows resource file
-ifeq ($(platform),win)
-  ifeq ($(compiler),cl)
-    objects += obj/bsnes.res
-  else ifneq ($(findstring gcc,$(compiler)),)
-    objects += obj/bsnesrc.$(obj)
-  endif
-endif
-
-################
-### implicit ###
-################
+######################
+### implicit rules ###
+######################
 
 compile = \
   $(strip \
     $(if $(filter %.c,$<), \
-      $(c) $1 $(rule), \
+      $(c) $(flags) $1 -c $< -o $@, \
       $(if $(filter %.cpp,$<), \
-        $(cpp) $1 $(rule) \
+        $(cpp) $(flags) $1 -c $< -o $@ \
       ) \
     ) \
   )
 
-%.$(obj): $<; $(call compile)
+%.o: $<; $(call compile)
 
 all: build;
 
-############
-### main ###
-############
-
-obj/main.$(obj): ui/main.cpp ui/* ui/base/* ui/loader/* ui/settings/*
-obj/bsnes.res: ui/bsnes.rc; rc /r /foobj/bsnes.res ui/bsnes.rc
-obj/bsnesrc.$(obj): ui/bsnes.rc; windres ui/bsnes.rc obj/bsnesrc.$(obj)
+include $(ui)/Makefile
+objects := $(patsubst %,obj/%.o,$(objects))
+rubydef := $(foreach c,$(subst .,_,$(call strupper,$(ruby))),-D$c)
 
 #################
 ### libraries ###
 #################
 
-obj/ruby.$(obj): lib/ruby/ruby.cpp lib/ruby/*
+obj/ruby.o: lib/ruby/ruby.cpp $(call rwildcard,lib/ruby/*)
 	$(call compile,$(rubydef) $(rubyflags))
-obj/hiro.$(obj): lib/hiro/hiro.cpp lib/hiro/* lib/hiro/gtk/* lib/hiro/win/*
-	$(call compile,$(if $(call streq,$(platform),x),`pkg-config --cflags gtk+-2.0`))
-obj/libco.$(obj):     lib/libco/libco.c lib/libco/*
-	$(call compile,-static)
-obj/libfilter.$(obj): lib/libfilter/libfilter.cpp lib/libfilter/*
-obj/string.$(obj):    lib/nall/string.cpp lib/nall/*
+obj/libco.o: lib/libco/libco.c lib/libco/*
+	$(c) -O3 -fomit-frame-pointer -static -Ilib -c $< -o $@
+obj/libreader.o: lib/libreader/libreader.cpp lib/libreader/*
+obj/libfilter.o: lib/libfilter/libfilter.cpp lib/libfilter/*
+obj/string.o: lib/nall/string.cpp lib/nall/*
 
 #################
 ### utilities ###
 #################
 
-obj/reader.$(obj): reader/reader.cpp reader/*
-obj/cart.$(obj)  : cart/cart.cpp cart/*
-obj/cheat.$(obj) : cheat/cheat.cpp cheat/*
+obj/cartridge.o: cartridge/cartridge.cpp cartridge/*
+obj/cheat.o    : cheat/cheat.cpp cheat/*
 
 ##############
 ### memory ###
 ##############
 
-obj/memory.$(obj) : memory/memory.cpp memory/*
-obj/smemory.$(obj): memory/smemory/smemory.cpp memory/smemory/* memory/smemory/mapper/*
+obj/memory.o : memory/memory.cpp memory/*
+obj/smemory.o: memory/smemory/smemory.cpp $(call rwildcard,memory/smemory/)
 
 ###########
 ### cpu ###
 ###########
 
-obj/cpu.$(obj) : cpu/cpu.cpp cpu/*
-obj/scpu.$(obj): cpu/scpu/scpu.cpp cpu/scpu/* cpu/scpu/core/* cpu/scpu/dma/* cpu/scpu/memory/* cpu/scpu/mmio/* cpu/scpu/timing/*
+obj/cpu.o    : cpu/cpu.cpp cpu/*
+obj/cpucore.o: cpu/core/core.cpp $(call rwildcard,cpu/core/)
+obj/scpu.o   : cpu/scpu/scpu.cpp $(call rwildcard,cpu/scpu/)
 
 ###########
 ### smp ###
 ###########
 
-obj/smp.$(obj) : smp/smp.cpp smp/*
-obj/ssmp.$(obj): smp/ssmp/ssmp.cpp smp/ssmp/* smp/ssmp/core/* smp/ssmp/memory/* smp/ssmp/timing/*
+obj/smp.o    : smp/smp.cpp smp/*
+obj/smpcore.o: smp/core/core.cpp $(call rwildcard,smp/core/)
+obj/ssmp.o   : smp/ssmp/ssmp.cpp $(call rwildcard,smp/ssmp/)
 
 ###########
 ### dsp ###
 ###########
 
-obj/adsp.$(obj): dsp/adsp/adsp.cpp dsp/adsp/*
-obj/bdsp.$(obj): dsp/bdsp/bdsp.cpp dsp/bdsp/*
-obj/sdsp.$(obj): dsp/sdsp/sdsp.cpp dsp/sdsp/*
+obj/adsp.o: dsp/adsp/adsp.cpp dsp/adsp/*
+obj/sdsp.o: dsp/sdsp/sdsp.cpp dsp/sdsp/*
 
 ###########
 ### ppu ###
 ###########
 
-obj/ppu.$(obj) : ppu/ppu.cpp ppu/*
-obj/bppu.$(obj): ppu/bppu/bppu.cpp ppu/bppu/*
+obj/ppu.o : ppu/ppu.cpp ppu/*
+obj/bppu.o: ppu/bppu/bppu.cpp ppu/bppu/*
 
-############
-### snes ###
-############
+##############
+### system ###
+##############
 
-obj/snes.$(obj): snes/snes.cpp snes/* snes/scheduler/* snes/video/* snes/audio/* snes/input/*
+obj/system.o: system/system.cpp $(call rwildcard,system/)
 
 #####################
 ### special chips ###
 #####################
 
-obj/bsx.$(obj)  : chip/bsx/bsx.cpp chip/bsx/*
-obj/srtc.$(obj) : chip/srtc/srtc.cpp chip/srtc/*
-obj/sdd1.$(obj) : chip/sdd1/sdd1.cpp chip/sdd1/*
-obj/cx4.$(obj)  : chip/cx4/cx4.cpp chip/cx4/*
-obj/dsp1.$(obj) : chip/dsp1/dsp1.cpp chip/dsp1/*
-obj/dsp2.$(obj) : chip/dsp2/dsp2.cpp chip/dsp2/*
-obj/dsp3.$(obj) : chip/dsp3/dsp3.cpp chip/dsp3/*
-obj/dsp4.$(obj) : chip/dsp4/dsp4.cpp chip/dsp4/*
-obj/obc1.$(obj) : chip/obc1/obc1.cpp chip/obc1/*
-obj/st010.$(obj): chip/st010/st010.cpp chip/st010/*
+obj/sgb.o    : chip/sgb/sgb.cpp $(call rwildcard,chip/sgb/)
+obj/sa1.o    : chip/sa1/sa1.cpp $(call rwildcard,chip/sa1/)
+obj/bsx.o    : chip/bsx/bsx.cpp chip/bsx/*
+obj/srtc.o   : chip/srtc/srtc.cpp chip/srtc/*
+obj/sdd1.o   : chip/sdd1/sdd1.cpp chip/sdd1/*
+obj/spc7110.o: chip/spc7110/spc7110.cpp chip/spc7110/*
+obj/cx4.o    : chip/cx4/cx4.cpp chip/cx4/*
+obj/dsp1.o   : chip/dsp1/dsp1.cpp chip/dsp1/*
+obj/dsp2.o   : chip/dsp2/dsp2.cpp chip/dsp2/*
+obj/dsp3.o   : chip/dsp3/dsp3.cpp chip/dsp3/*
+obj/dsp4.o   : chip/dsp4/dsp4.cpp chip/dsp4/*
+obj/obc1.o   : chip/obc1/obc1.cpp chip/obc1/*
+obj/st010.o  : chip/st010/st010.cpp chip/st010/*
 
 ############
 ### zlib ###
 ############
 
-obj/adler32.$(obj) : reader/zlib/adler32.c reader/zlib/*
-obj/compress.$(obj): reader/zlib/compress.c reader/zlib/*
-obj/crc32.$(obj)   : reader/zlib/crc32.c reader/zlib/*
-obj/deflate.$(obj) : reader/zlib/deflate.c reader/zlib/*
-obj/gzio.$(obj)    : reader/zlib/gzio.c reader/zlib/*
-obj/inffast.$(obj) : reader/zlib/inffast.c reader/zlib/*
-obj/inflate.$(obj) : reader/zlib/inflate.c reader/zlib/*
-obj/inftrees.$(obj): reader/zlib/inftrees.c reader/zlib/*
-obj/ioapi.$(obj)   : reader/zlib/ioapi.c reader/zlib/*
-obj/trees.$(obj)   : reader/zlib/trees.c reader/zlib/*
-obj/unzip.$(obj)   : reader/zlib/unzip.c reader/zlib/*
-obj/zip.$(obj)     : reader/zlib/zip.c reader/zlib/*
-obj/zutil.$(obj)   : reader/zlib/zutil.c reader/zlib/*
+obj/adler32.o : lib/zlib/adler32.c lib/zlib/*
+obj/compress.o: lib/zlib/compress.c lib/zlib/*
+obj/crc32.o   : lib/zlib/crc32.c lib/zlib/*
+obj/deflate.o : lib/zlib/deflate.c lib/zlib/*
+obj/gzio.o    : lib/zlib/gzio.c lib/zlib/*
+obj/inffast.o : lib/zlib/inffast.c lib/zlib/*
+obj/inflate.o : lib/zlib/inflate.c lib/zlib/*
+obj/inftrees.o: lib/zlib/inftrees.c lib/zlib/*
+obj/ioapi.o   : lib/zlib/ioapi.c lib/zlib/*
+obj/trees.o   : lib/zlib/trees.c lib/zlib/*
+obj/unzip.o   : lib/zlib/unzip.c lib/zlib/*
+obj/zip.o     : lib/zlib/zip.c lib/zlib/*
+obj/zutil.o   : lib/zlib/zutil.c lib/zlib/*
 
-###########
-### jma ###
-###########
+##############
+### libjma ###
+##############
 
-obj/jma.$(obj)    : reader/jma/jma.cpp reader/jma/*
-obj/jcrc32.$(obj) : reader/jma/jcrc32.cpp reader/jma/*
-obj/lzmadec.$(obj): reader/jma/lzmadec.cpp reader/jma/*
-obj/7zlzma.$(obj) : reader/jma/7zlzma.cpp reader/jma/*
-obj/iiostrm.$(obj): reader/jma/iiostrm.cpp reader/jma/*
-obj/inbyte.$(obj) : reader/jma/inbyte.cpp reader/jma/*
-obj/lzma.$(obj)   : reader/jma/lzma.cpp reader/jma/*
-obj/winout.$(obj) : reader/jma/winout.cpp reader/jma/*
+obj/jma.o    : lib/libjma/jma.cpp lib/libjma/*
+obj/jcrc32.o : lib/libjma/jcrc32.cpp lib/libjma/*
+obj/lzmadec.o: lib/libjma/lzmadec.cpp lib/libjma/*
+obj/7zlzma.o : lib/libjma/7zlzma.cpp lib/libjma/*
+obj/iiostrm.o: lib/libjma/iiostrm.cpp lib/libjma/*
+obj/inbyte.o : lib/libjma/inbyte.cpp lib/libjma/*
+obj/lzma.o   : lib/libjma/lzma.cpp lib/libjma/*
+obj/winout.o : lib/libjma/winout.cpp lib/libjma/*
 
 ###############
 ### targets ###
 ###############
 
-build: $(objects)
-	$(strip $(cpp) $(call mkbin,../bsnes) $(objects) $(link))
+build: ui_build $(objects)
+	$(strip $(cpp) -o../bsnes $(objects) $(link))
 
 install:
 	install -D -m 755 ../bsnes $(DESTDIR)$(prefix)/bin/bsnes
-	install -D -m 644 data/bsnes.png $(DESTDIR)$(prefix)/share/icons/bsnes.png
+	install -D -m 644 data/bsnes.png $(DESTDIR)$(prefix)/share/pixmaps/bsnes.png
+	install -D -m 644 data/bsnes.desktop $(DESTDIR)$(prefix)/share/applications/bsnes.desktop
 
-clean:
-	-@$(call delete,obj/*.$(obj))
+clean: ui_clean
+	-@$(call delete,obj/*.o)
 	-@$(call delete,*.res)
 	-@$(call delete,*.pgd)
 	-@$(call delete,*.pgc)
@@ -269,7 +243,6 @@ help:
 	@echo "  gcc              - GCC compiler"
 	@echo "  mingw32-gcc      - MinGW compiler"
 	@echo "  i586-mingw32-gcc - MinGW cross compiler"
-	@echo "  cl               - Visual C++"
 	@echo ""
 	@echo "Available options:"
 	@echo "  enable_gzip=[true|false] - Enable ZIP / GZ support (default=false)"
@@ -277,3 +250,4 @@ help:
 	@echo ""
 	@echo "Example: $(MAKE) platform=x compiler=gcc enable_gzip=true"
 	@echo ""
+

src/base.hpp

@@ -1,4 +1,4 @@
-#define BSNES_VERSION "0.032"
+#define BSNES_VERSION "0.046"
 #define BSNES_TITLE   "bsnes v" BSNES_VERSION
 
 #define BUSCORE sBus
@@ -9,48 +9,36 @@
 
 //S-DSP can be encapsulated into a state machine using #define magic
 //this avoids ~2.048m co_switch() calls per second (~5% speedup)
-#define USE_STATE_MACHINE
-
-//FAST_FRAMESKIP disables calculation of RTO during frameskip
-//frameskip offers near-zero speedup if RTO is calculated
-//accuracy is not affected by this define when frameskipping is off
-#define FAST_FRAMESKIP
+#define DSP_STATE_MACHINE
 
 //game genie + pro action replay code support (~2% speed hit)
 #define CHEAT_SYSTEM
 
+#include <libco/libco.h>
+
 #include <nall/algorithm.hpp>
 #include <nall/array.hpp>
 #include <nall/bit.hpp>
-#include <nall/config.hpp>
 #include <nall/detect.hpp>
+#include <nall/dl.hpp>
+#include <nall/endian.hpp>
 #include <nall/function.hpp>
-#include <nall/modulo.hpp>
+#include <nall/moduloarray.hpp>
 #include <nall/new.hpp>
-#include <nall/sort.hpp>
+#include <nall/platform.hpp>
+#include <nall/property.hpp>
 #include <nall/stdint.hpp>
 #include <nall/string.hpp>
+#include <nall/utility.hpp>
 #include <nall/vector.hpp>
 using namespace nall;
 
-#include <libco/libco.h>
-#include <bbase.h>
+typedef int8_t   int8;
+typedef int16_t  int16;
+typedef int32_t  int32;
+typedef uint8_t  uint8;
+typedef uint16_t uint16;
+typedef uint32_t uint32;
 
-//platform-specific global functions
-void alert(const char*, ...);
-void dprintf(const char*, ...);
-void dprintf(uint, const char*, ...);
+#include "interface.hpp"
 
-namespace source {
-  enum {
-    none = 0,
-    debug,
-    cpu,
-    ppu,
-    smp,
-    dsp,
-    bus,
-  };
-};
-
-#include "interface.h"

src/cart/cart.cpp

@@ -1,137 +0,0 @@
-#include "../base.h"
-#define CART_CPP
-
-#include <nall/crc32.hpp>
-#include <nall/ups.hpp>
-
-#include "cart_normal.cpp"
-#include "cart_bsx.cpp"
-#include "cart_bsc.cpp"
-#include "cart_st.cpp"
-
-#include "cart_file.cpp"
-#include "cart_header.cpp"
-
-namespace memory {
-  MappedRAM cartrom, cartram;
-  MappedRAM bscram;
-  MappedRAM stArom, stAram;
-  MappedRAM stBrom, stBram;
-};
-
-Cartridge cartridge;
-
-Cartridge::MemoryMapper Cartridge::mapper() { return info.mapper; }
-Cartridge::Region Cartridge::region() { return info.region; }
-
-bool Cartridge::loaded() { return cart.loaded; }
-
-void Cartridge::load_begin(CartridgeType cart_type) {
-  cart.rom = cart.ram = 0;
-  bs.ram   = 0;
-  stA.rom  = stA.ram  = 0;
-  stB.rom  = stB.ram  = 0;
-
-  cart.rom_size = cart.ram_size = 0;
-  bs.ram_size   = 0;
-  stA.rom_size  = stA.ram_size  = 0;
-  stB.rom_size  = stB.ram_size  = 0;
-
-  info.type = cart_type;
-
-  info.bsxbase  = false;
-  info.bsxcart  = false;
-  info.bsxflash = false;
-  info.st       = false;
-
-  info.superfx = false;
-  info.sa1     = false;
-  info.spc7110 = false;
-  info.srtc    = false;
-  info.sdd1    = false;
-  info.cx4     = false;
-  info.dsp1    = false;
-  info.dsp2    = false;
-  info.dsp3    = false;
-  info.dsp4    = false;
-  info.obc1    = false;
-  info.st010   = false;
-  info.st011   = false;
-  info.st018   = false;
-
-  info.dsp1_mapper = DSP1Unmapped;
-
-  info.header_index = 0xffc0;
-  info.mapper = LoROM;
-  info.name[0] = 0;
-  info.region = NTSC;
-
-  info.rom_size = 0;
-  info.ram_size = 0;
-}
-
-void Cartridge::load_end() {
-  memory::cartrom.map(cart.rom, cart.rom_size);
-  memory::cartram.map(cart.ram, cart.ram_size);
-  memory::bscram.map(bs.ram, bs.ram_size);
-  memory::stArom.map(stA.rom, stA.rom_size);
-  memory::stAram.map(stA.ram, stA.ram_size);
-  memory::stBrom.map(stB.rom, stB.rom_size);
-  memory::stBram.map(stB.ram, stB.ram_size);
-
-  memory::cartrom.write_protect(true);
-  memory::cartram.write_protect(false);
-  memory::bscram.write_protect(true);
-  memory::stArom.write_protect(true);
-  memory::stAram.write_protect(false);
-  memory::stBrom.write_protect(true);
-  memory::stBram.write_protect(false);
-
-  if(fexists(get_cheat_filename(cart.fn, "cht"))) {
-    cheat.clear();
-    cheat.load(cheatfn);
-  }
-
-  cart.loaded = true;
-  bus.load_cart();
-}
-
-bool Cartridge::unload() {
-  if(cart.loaded == false) return false;
-
-  bus.unload_cart();
-
-  switch(info.type) {
-    case CartridgeNormal:      unload_cart_normal(); break;
-    case CartridgeBSX:         unload_cart_bsx();    break;
-    case CartridgeBSC:         unload_cart_bsc();    break;
-    case CartridgeSufamiTurbo: unload_cart_st();     break;
-  }
-
-  if(cart.rom) { delete[] cart.rom; cart.rom = 0; }
-  if(cart.ram) { delete[] cart.ram; cart.ram = 0; }
-  if(bs.ram)   { delete[] bs.ram;   bs.ram   = 0; }
-  if(stA.rom)  { delete[] stA.rom;  stA.rom  = 0; }
-  if(stA.ram)  { delete[] stA.ram;  stA.ram  = 0; }
-  if(stB.rom)  { delete[] stB.rom;  stB.rom  = 0; }
-  if(stB.ram)  { delete[] stB.ram;  stB.ram  = 0; }
-
-  char fn[PATH_MAX];
-  strcpy(fn, cart.fn);
-  modify_extension(fn, "cht");
-  if(cheat.count() > 0 || fexists(get_cheat_filename(cart.fn, "cht"))) {
-    cheat.save(cheatfn);
-    cheat.clear();
-  }
-
-  cart.loaded = false;
-  return true;
-}
-
-Cartridge::Cartridge() {
-  cart.loaded = false;
-}
-
-Cartridge::~Cartridge() {
-  if(cart.loaded == true) unload();
-}

src/cart/cart.h

@@ -1,156 +0,0 @@
-class Cartridge {
-public:
-  enum CartridgeType {
-    CartridgeNormal,
-    CartridgeBSX,
-    CartridgeBSC,
-    CartridgeSufamiTurbo,
-  };
-
-  enum HeaderField {
-    CART_NAME = 0x00,
-    MAPPER    = 0x15,
-    ROM_TYPE  = 0x16,
-    ROM_SIZE  = 0x17,
-    RAM_SIZE  = 0x18,
-    REGION    = 0x19,
-    COMPANY   = 0x1a,
-    VERSION   = 0x1b,
-    ICKSUM    = 0x1c,
-    CKSUM     = 0x1e,
-    RESL      = 0x3c,
-    RESH      = 0x3d,
-  };
-
-  enum Region {
-    NTSC,
-    PAL,
-  };
-
-  enum MemoryMapper {
-    LoROM,
-    HiROM,
-    ExLoROM,
-    ExHiROM,
-    BSXROM,
-    BSCLoROM,
-    BSCHiROM,
-    STROM,
-  };
-
-  enum DSP1MemoryMapper {
-    DSP1Unmapped,
-    DSP1LoROM1MB,
-    DSP1LoROM2MB,
-    DSP1HiROM,
-  };
-
-  struct {
-    bool loaded;
-    char fn[PATH_MAX];
-    uint8 *rom, *ram;
-    uint rom_size, ram_size;
-  } cart;
-
-  struct {
-    char fn[PATH_MAX];
-    uint8 *ram;
-    uint ram_size;
-  } bs;
-
-  struct {
-    char fn[PATH_MAX];
-    uint8 *rom, *ram;
-    uint rom_size, ram_size;
-  } stA, stB;
-
-  struct {
-    CartridgeType type;
-
-    uint32 crc32;
-    char filename[PATH_MAX * 4];
-    char name[128];
-
-    Region region;
-    MemoryMapper mapper;
-    uint rom_size;
-    uint ram_size;
-
-    bool bsxbase;
-    bool bsxcart;
-    bool bsxflash;
-    bool st;
-    bool superfx;
-    bool sa1;
-    bool srtc;
-    bool sdd1;
-    bool spc7110;
-    bool cx4;
-    bool dsp1;
-    bool dsp2;
-    bool dsp3;
-    bool dsp4;
-    bool obc1;
-    bool st010;
-    bool st011;
-    bool st018;
-
-    DSP1MemoryMapper dsp1_mapper;
-
-    uint header_index;
-  } info;
-
-  MemoryMapper mapper();
-  Region region();
-
-  void load_cart_normal(const char*);
-  void load_cart_bsx(const char*, const char*);
-  void load_cart_bsc(const char*, const char*);
-  void load_cart_st(const char*, const char*, const char*);
-
-  void unload_cart_normal();
-  void unload_cart_bsx();
-  void unload_cart_bsc();
-  void unload_cart_st();
-
-  bool loaded();
-  void load_begin(CartridgeType);
-  void load_end();
-  bool unload();
-
-  void find_header();
-  void read_header();
-  void read_extended_header();
-
-  enum CompressionMode {
-    CompressionNone,    //always load without compression
-    CompressionInspect, //use file header inspection
-    CompressionAuto,    //use file extension or file header inspection (configured by user)
-  };
-  bool load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression = CompressionNone);
-  bool save_file(const char *fn, uint8 *data, uint size);
-  bool apply_patch(const uint8_t *pdata, unsigned psize, uint8_t *&data, unsigned &size);
-  char* modify_extension(char *filename, const char *extension);
-  char* get_base_filename(char *filename);
-  char* get_path_filename(char *filename, const char *path, const char *source, const char *extension);
-  char* get_patch_filename(const char *source, const char *extension);
-  char* get_save_filename(const char *source, const char *extension);
-  char* get_cheat_filename(const char *source, const char *extension);
-
-  Cartridge();
-  ~Cartridge();
-
-private:
-  char patchfn[PATH_MAX];
-  char savefn[PATH_MAX];
-  char cheatfn[PATH_MAX];
-};
-
-namespace memory {
-  extern MappedRAM cartrom, cartram;
-  extern MappedRAM bscram;
-  extern MappedRAM stArom, stAram;
-  extern MappedRAM stBrom, stBram;
-};
-
-extern Cartridge cartridge;

src/cart/cart_bsc.cpp

@@ -1,65 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_bsc(const char *base, const char *slot) {
-  if(!base || !*base) return;
-
-  strcpy(cart.fn, base);
-  strcpy(bs.fn, slot ? slot : "");
-  load_begin(CartridgeBSC);
-
-  uint8_t *data = 0;
-  unsigned size;
-  load_file(cart.fn, data, size, CompressionAuto);
-  cart.rom = data, cart.rom_size = size;
-
-  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
-    apply_patch(data, size, cart.rom, cart.rom_size);
-    delete[] data;
-  }
-
-  if(*bs.fn) {
-    if(load_file(bs.fn, data, size, CompressionAuto) == true) {
-      info.bsxflash = true;
-      bs.ram = data, bs.ram_size = size;
-      if(load_file(get_patch_filename(bs.fn, "ups"), data, size, CompressionInspect) == true) {
-        apply_patch(data, size, bs.ram, bs.ram_size);
-        delete[] data;
-      }
-    }
-  }
-
-  find_header();
-  read_header();
-
-  info.mapper = cartridge.info.header_index == 0x7fc0 ? BSCLoROM : BSCHiROM;
-  info.region = NTSC;
-
-  if(info.ram_size > 0) {
-    cart.ram = new uint8_t[cart.ram_size = info.ram_size];
-    memset(cart.ram, 0xff, cart.ram_size);
-
-    if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
-      memcpy(cart.ram, data, min(size, cart.ram_size));
-      delete[] data;
-    }
-  }
-
-  load_end();
-
-  //set base filename
-  strcpy(info.filename, cart.fn);
-  get_base_filename(info.filename);
-  if(*bs.fn) {
-    char filenameBS[PATH_MAX];
-    strcpy(filenameBS, bs.fn);
-    get_base_filename(filenameBS);
-    strcat(info.filename, " + ");
-    strcat(info.filename, filenameBS);
-  }
-}
-
-void Cartridge::unload_cart_bsc() {
-  if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_bsx.cpp

@@ -1,61 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_bsx(const char *base, const char *slot) {
-  if(!base || !*base) return;
-
-  strcpy(cart.fn, base);
-  strcpy(bs.fn, slot ? slot : "");
-
-  load_begin(CartridgeBSX);
-  info.bsxbase = true;
-  info.bsxcart = true;
-  info.mapper = BSXROM;
-  info.region = NTSC;
-
-  uint8_t *data = 0;
-  unsigned size;
-  load_file(cart.fn, data, size, CompressionAuto);
-  cart.rom = data, cart.rom_size = size;
-  cart.ram = 0, cart.ram_size = 0;
-
-  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
-    apply_patch(data, size, cart.rom, cart.rom_size);
-    delete[] data;
-  }
-
-  memset(bsxcart.sram.handle (), 0x00, bsxcart.sram.size ());
-  memset(bsxcart.psram.handle(), 0x00, bsxcart.psram.size());
-
-  if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
-    memcpy(bsxcart.sram.handle (), data, min(bsxcart.sram.size (), size));
-    delete[] data;
-  }
-
-  if(load_file(get_save_filename(cart.fn, "psr"), data, size, CompressionNone) == true) {
-    memcpy(bsxcart.psram.handle(), data, min(bsxcart.psram.size(), size));
-    delete[] data;
-  }
-
-  if(*bs.fn) {
-    if(load_file(bs.fn, data, size, CompressionAuto) == true) {
-      info.bsxflash = true;
-      bs.ram = data, bs.ram_size = size;
-      if(load_file(get_patch_filename(bs.fn, "ups"), data, size, CompressionInspect) == true) {
-        apply_patch(data, size, bs.ram, bs.ram_size);
-        delete[] data;
-      }
-    }
-  }
-
-  load_end();
-
-  strcpy(info.filename, !*bs.fn ? cart.fn : bs.fn);
-  get_base_filename(info.filename);
-}
-
-void Cartridge::unload_cart_bsx() {
-  save_file(get_save_filename(cart.fn, "srm"), bsxcart.sram.handle (), bsxcart.sram.size ());
-  save_file(get_save_filename(cart.fn, "psr"), bsxcart.psram.handle(), bsxcart.psram.size());
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_file.cpp

@@ -1,179 +0,0 @@
-#ifdef CART_CPP
-
-#include "../reader/filereader.h"
-
-#if defined(GZIP_SUPPORT)
-  #include "../reader/gzreader.h"
-  #include "../reader/zipreader.h"
-#endif
-
-#if defined(JMA_SUPPORT)
-  #include "../reader/jmareader.h"
-#endif
-
-char* Cartridge::modify_extension(char *filename, const char *extension) {
-  int i;
-  for(i = strlen(filename); i >= 0; i--) {
-    if(filename[i] == '.') break;
-    if(filename[i] == '/') break;
-    if(filename[i] == '\\') break;
-  }
-  if(i > 0 && filename[i] == '.') filename[i] = 0;
-  strcat(filename, ".");
-  strcat(filename, extension);
-  return filename;
-}
-
-//remove directory information and file extension ("/foo/bar.ext" -> "bar")
-char* Cartridge::get_base_filename(char *filename) {
-  //remove extension
-  for(int i = strlen(filename) - 1; i >= 0; i--) {
-    if(filename[i] == '.') {
-      filename[i] = 0;
-      break;
-    }
-  }
-
-  //remove directory information
-  for(int i = strlen(filename) - 1; i >= 0; i--) {
-    if(filename[i] == '/' || filename[i] == '\\') {
-      i++;
-      char *output = filename;
-      while(true) {
-        *output++ = filename[i];
-        if(!filename[i]) break;
-        i++;
-      }
-      break;
-    }
-  }
-}
-
-char* Cartridge::get_path_filename(char *filename, const char *path, const char *source, const char *extension) {
-  strcpy(filename, source);
-  for(char *p = filename; *p; p++) { if(*p == '\\') *p = '/'; }
-  modify_extension(filename, extension);
-
-  //override path with user-specified folder, if one was defined
-  if(*path) {
-    lstring part;
-    split(part, "/", filename);
-    string fn = path;
-    if(strend(fn, "/") == false) strcat(fn, "/");
-    strcat(fn, part[count(part) - 1]);
-    strcpy(filename, fn);
-
-    //resolve relative path, if found
-    if(strbegin(fn, "./") == true) {
-      ltrim(fn, "./");
-      strcpy(filename, config::path.base);
-      strcat(filename, fn);
-    }
-  }
-
-  return filename;
-}
-
-char* Cartridge::get_patch_filename(const char *source, const char *extension) {
-  return get_path_filename(patchfn, config::path.patch, source, extension);
-}
-
-char* Cartridge::get_save_filename(const char *source, const char *extension) {
-  return get_path_filename(savefn, config::path.save, source, extension);
-}
-
-char* Cartridge::get_cheat_filename(const char *source, const char *extension) {
-  return get_path_filename(cheatfn, config::path.cheat, source, extension);
-}
-
-bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression) {
-  dprintf("* Loading \"%s\" ...", fn);
-
-  if(fexists(fn) == false) return false;
-
-  Reader::Type filetype = Reader::Normal;
-  if(compression == CompressionInspect) filetype = Reader::detect(fn, true);
-  if(compression == CompressionAuto) filetype = Reader::detect(fn, config::file.autodetect_type);
-
-  switch(filetype) {
-    default:
-      dprintf("* Warning: filetype detected as unsupported compression type.");
-      dprintf("* Will attempt to load as uncompressed file -- may fail.");
-    case Reader::Normal: {
-      FileReader ff(fn);
-      if(!ff.ready()) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-      size = ff.size();
-      data = ff.read();
-    } break;
-
-    #ifdef GZIP_SUPPORT
-    case Reader::GZIP: {
-      GZReader gf(fn);
-      if(!gf.ready()) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-      size = gf.size();
-      data = gf.read();
-    } break;
-
-    case Reader::ZIP: {
-      ZipReader zf(fn);
-      size = zf.size();
-      data = zf.read();
-    } break;
-    #endif
-
-    #ifdef JMA_SUPPORT
-    case Reader::JMA: {
-      try {
-        JMAReader jf(fn);
-        size = jf.size();
-        data = jf.read();
-      } catch(JMA::jma_errors jma_error) {
-        alert("Error loading image file (%s)!", fn);
-        return false;
-      }
-    } break;
-    #endif
-  }
-
-  return true;
-}
-
-bool Cartridge::apply_patch(const uint8_t *pdata, const unsigned psize, uint8_t *&data, unsigned &size) {
-  uint8_t *outdata = 0;
-  unsigned outsize;
-  ups patcher;
-  ups::result result = patcher.apply(pdata, psize, data, size, outdata, outsize);
-
-  bool apply = false;
-  if(result == ups::ok) apply = true;
-  if(config::file.bypass_patch_crc32 == true) {
-    if(result == ups::input_crc32_invalid) apply = true;
-    if(result == ups::output_crc32_invalid) apply = true;
-  }
-
-  if(apply == true) {
-    delete[] data;
-    data = new uint8_t[size = outsize];
-    memcpy(data, outdata, outsize);
-  } else {
-    dprintf("* Warning: patch application failed!");
-  }
-
-  if(outdata) delete[] outdata;
-}
-
-bool Cartridge::save_file(const char *fn, uint8 *data, uint size) {
-  FILE *fp = fopen(fn, "wb");
-  if(!fp) return false;
-  fwrite(data, 1, size, fp);
-  fclose(fp);
-  return true;
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_header.cpp

@@ -1,194 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::read_header() {
-  uint8 *rom = cart.rom;
-  uint index = info.header_index;
-  uint8 mapper   = rom[index + MAPPER];
-  uint8 rom_type = rom[index + ROM_TYPE];
-  uint8 company  = rom[index + COMPANY];
-  uint8 region   = rom[index + REGION] & 0x7f;
-
-  //detect presence of BS-X flash cartridge connector (reads extended header information)
-  bool has_bsxflash = false;
-  if(rom[index - 14] == 'Z') {
-    if(rom[index - 11] == 'J') {
-      uint8 n13 = rom[index - 13];
-      if((n13 >= 'A' && n13 <= 'Z') || (n13 >= '0' && n13 <= '9')) {
-        if(company == 0x33 || (rom[index - 10] == 0x00 && rom[index - 4] == 0x00)) {
-          has_bsxflash = true;
-        }
-      }
-    }
-  }
-
-  if(has_bsxflash == true) {
-    info.mapper = index == 0x7fc0 ? BSCLoROM : BSCHiROM;
-  } else if(index == 0x7fc0 && cart.rom_size >= 0x401000) {
-    info.mapper = ExLoROM;
-  } else if(index == 0x7fc0 && mapper == 0x32) {
-    info.mapper = ExLoROM;
-  } else if(index == 0x7fc0) {
-    info.mapper = LoROM;
-  } else if(index == 0xffc0) {
-    info.mapper = HiROM;
-  } else { //index == 0x40ffc0
-    info.mapper = ExHiROM;
-  }
-
-  if(mapper == 0x20 && (rom_type == 0x13 || rom_type == 0x14 || rom_type == 0x15 || rom_type == 0x1a)) {
-    info.superfx = true;
-  }
-
-  if(mapper == 0x23 && (rom_type == 0x34 || rom_type == 0x35)) {
-    info.sa1 = true;
-  }
-
-  if(mapper == 0x35 && rom_type == 0x55) {
-    info.srtc = true;
-  }
-
-  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
-    info.sdd1 = true;
-  }
-
-  if(mapper == 0x3a && (rom_type == 0xf5 || rom_type == 0xf9)) {
-    //rom_type: 0xf5 = no S-RTC, 0xf9 = S-RTC
-    info.spc7110 = true;
-  }
-
-  if(mapper == 0x20 && rom_type == 0xf3) {
-    info.cx4 = true;
-  }
-
-  if((mapper == 0x20 || mapper == 0x21) && rom_type == 0x03) {
-    info.dsp1 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x05 && company != 0xb2) {
-    info.dsp1 = true;
-  }
-
-  if(mapper == 0x31 && (rom_type == 0x03 || rom_type == 0x05)) {
-    info.dsp1 = true;
-  }
-
-  if(info.dsp1 == true) {
-    if((mapper & 0x2f) == 0x20 && cart.rom_size <= 0x100000) {
-      info.dsp1_mapper = DSP1LoROM1MB;
-    } else if((mapper & 0x2f) == 0x20) {
-      info.dsp1_mapper = DSP1LoROM2MB;
-    } else if((mapper & 0x2f) == 0x21) {
-      info.dsp1_mapper = DSP1HiROM;
-    }
-  }
-
-  if(mapper == 0x20 && rom_type == 0x05) {
-    info.dsp2 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x05 && company == 0xb2) {
-    info.dsp3 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x03) {
-    info.dsp4 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x25) {
-    info.obc1 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0xf6) {
-    //TODO: both ST010 and ST011 share the same mapper + rom_type.
-    //need way to determine which is which.
-    //for now, default to supported ST010.
-    info.st010 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0xf5) {
-    info.st018 = true;
-  }
-
-  if(rom[info.header_index + RAM_SIZE] & 7) {
-    info.ram_size = 1024 << (rom[info.header_index + RAM_SIZE] & 7);
-  } else {
-    info.ram_size = 0;
-  }
-
-  //0, 1, 13 = NTSC; 2 - 12 = PAL
-  info.region = (region <= 1 || region >= 13) ? NTSC : PAL;
-
-  memcpy(&info.name, &rom[info.header_index + CART_NAME], 21);
-  info.name[21] = 0;
-  trim(info.name);
-
-  //convert undisplayable characters (half-width katakana, etc) to '?' characters
-  for(int i = 0; i < 21; i++) {
-    if(info.name[i] & 0x80) info.name[i] = '?';
-  }
-
-  //always display something
-  if(!info.name[0]) strcpy(info.name, "(untitled)");
-}
-
-void Cartridge::find_header() {
-  int32 score_lo = 0, score_hi = 0, score_ex = 0;
-  uint8_t *rom = cart.rom;
-
-  if(cart.rom_size < 0x010000) {
-    //cart too small to be anything but lorom
-    info.header_index = 0x007fc0;
-    return;
-  }
-
-  if((rom[0x7fc0 + MAPPER] & ~0x10) == 0x20) score_lo++;
-  if((rom[0xffc0 + MAPPER] & ~0x10) == 0x21) score_hi++;
-
-  if(rom[0x7fc0 + ROM_TYPE] < 0x08) score_lo++;
-  if(rom[0xffc0 + ROM_TYPE] < 0x08) score_hi++;
-
-  if(rom[0x7fc0 + ROM_SIZE] < 0x10) score_lo++;
-  if(rom[0xffc0 + ROM_SIZE] < 0x10) score_hi++;
-
-  if(rom[0x7fc0 + RAM_SIZE] < 0x08) score_lo++;
-  if(rom[0xffc0 + RAM_SIZE] < 0x08) score_hi++;
-
-  if(rom[0x7fc0 + REGION] < 14) score_lo++;
-  if(rom[0xffc0 + REGION] < 14) score_hi++;
-
-  if(rom[0x7fc0 + COMPANY] < 3) score_lo++;
-  if(rom[0xffc0 + COMPANY] < 3) score_hi++;
-
-  if(rom[0x7fc0 + RESH] & 0x80) score_lo += 2;
-  if(rom[0xffc0 + RESH] & 0x80) score_hi += 2;
-
-  uint16 cksum, icksum;
-  cksum  = rom[0x7fc0 +  CKSUM] | (rom[0x7fc0 +  CKSUM + 1] << 8);
-  icksum = rom[0x7fc0 + ICKSUM] | (rom[0x7fc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_lo += 8;
-  }
-
-  cksum  = rom[0xffc0 +  CKSUM] | (rom[0xffc0 +  CKSUM + 1] << 8);
-  icksum = rom[0xffc0 + ICKSUM] | (rom[0xffc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_hi += 8;
-  }
-
-  if(cart.rom_size < 0x401000) {
-    score_ex = 0;
-  } else {
-    if(rom[0x7fc0 + MAPPER] == 0x32) score_lo++;
-    else score_ex += 16;
-  }
-
-  if(score_lo >= score_hi && score_lo >= score_ex) {
-    info.header_index = 0x007fc0;
-  } else if(score_hi >= score_ex) {
-    info.header_index = 0x00ffc0;
-  } else {
-    info.header_index = 0x40ffc0;
-  }
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_normal.cpp

@@ -1,54 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_normal(const char *filename) {
-  if(!filename || !*filename) return;
-
-  uint8_t *data = 0;
-  unsigned size;
-  if(load_file(filename, data, size, CompressionAuto) == false) return;
-  strcpy(cart.fn, filename);
-
-  load_begin(CartridgeNormal);
-
-  //load ROM data, ignore 512-byte header if detected
-  if((size & 0x7fff) != 512) {
-    cart.rom = new uint8_t[cart.rom_size = size];
-    memcpy(cart.rom, data, size);
-  } else {
-    cart.rom = new uint8_t[cart.rom_size = size - 512];
-    memcpy(cart.rom, data + 512, size - 512);
-  }
-  delete[] data;
-
-  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
-    apply_patch(data, size, cart.rom, cart.rom_size);
-    delete[] data;
-  }
-
-  info.crc32 = crc32_calculate(cart.rom, cart.rom_size);
-
-  find_header();
-  read_header();
-
-  if(info.ram_size > 0) {
-    cart.ram = new uint8_t[cart.ram_size = info.ram_size];
-    memset(cart.ram, 0xff, cart.ram_size);
-
-    if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
-      memcpy(cart.ram, data, min(size, cart.ram_size));
-      delete[] data;
-    }
-  }
-
-  load_end();
-
-  //set base filename
-  strcpy(info.filename, cart.fn);
-  get_base_filename(info.filename);
-}
-
-void Cartridge::unload_cart_normal() {
-  if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
-}
-
-#endif //ifdef CART_CPP

src/cart/cart_st.cpp

@@ -1,96 +0,0 @@
-#ifdef CART_CPP
-
-void Cartridge::load_cart_st(const char *base, const char *slotA, const char *slotB) {
-  if(!base || !*base) return;
-
-  strcpy(cart.fn, base);
-  strcpy(stA.fn, slotA ? slotA : "");
-  strcpy(stB.fn, slotB ? slotB : "");
-
-  load_begin(CartridgeSufamiTurbo);
-  info.st = true;
-  info.mapper = STROM;
-  info.region = NTSC;
-
-  uint8_t *data = 0;
-  unsigned size;
-  if(load_file(cart.fn, data, size, CompressionAuto) == true) {
-    cart.rom = new(zeromemory) uint8_t[cart.rom_size = 0x040000];
-    memcpy(cart.rom, data, min(size, cart.rom_size));
-    delete[] data;
-    if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
-      apply_patch(data, size, cart.rom, cart.rom_size);
-      delete[] data;
-    }
-  }
-
-  if(*stA.fn) {
-    if(load_file(stA.fn, data, size, CompressionAuto) == true) {
-      stA.rom = new(zeromemory) uint8_t[stA.rom_size = 0x100000];
-      memcpy(stA.rom, data, min(size, stA.rom_size));
-      delete[] data;
-      if(load_file(get_patch_filename(stA.fn, "ups"), data, size, CompressionInspect) == true) {
-        apply_patch(data, size, stA.rom, stA.rom_size);
-        delete[] data;
-      }
-
-      stA.ram = new uint8_t[stA.ram_size = 0x020000];
-      memset(stA.ram, 0xff, stA.ram_size);
-
-      if(load_file(get_save_filename(stA.fn, "srm"), data, size, CompressionNone) == true) {
-        memcpy(stA.ram, data, min(size, 0x020000U));
-        delete[] data;
-      }
-    }
-  }
-
-  if(*stB.fn) {
-    if(load_file(stB.fn, data, size, CompressionAuto) == true) {
-      stB.rom = new(zeromemory) uint8_t[stB.rom_size = 0x100000];
-      memcpy(stB.rom, data, min(size, stB.rom_size));
-      delete[] data;
-      if(load_file(get_patch_filename(stB.fn, "ups"), data, size, CompressionInspect) == true) {
-        apply_patch(data, size, stB.rom, stB.rom_size);
-        delete[] data;
-      }
-
-      stB.ram = new uint8_t[stB.ram_size = 0x020000];
-      memset(stB.ram, 0xff, stB.ram_size);
-
-      if(load_file(get_save_filename(stB.fn, "srm"), data, size, CompressionNone) == true) {
-        memcpy(stB.ram, data, min(size, 0x020000U));
-        delete[] data;
-      }
-    }
-  }
-
-  load_end();
-
-  //set base filename
-  if(!*stA.fn && !*stB.fn) {
-    strcpy(info.filename, cart.fn);
-    get_base_filename(info.filename);
-  } else if(*stA.fn && !*stB.fn) {
-    strcpy(info.filename, stA.fn);
-    get_base_filename(info.filename);
-  } else if(!*stA.fn && *stB.fn) {
-    strcpy(info.filename, stB.fn);
-    get_base_filename(info.filename);
-  } else {
-    char filenameA[PATH_MAX], filenameB[PATH_MAX];
-    strcpy(filenameA, stA.fn);
-    get_base_filename(filenameA);
-    strcpy(filenameB, stB.fn);
-    get_base_filename(filenameB);
-    strcpy(info.filename, filenameA);
-    strcat(info.filename, " + ");
-    strcat(info.filename, filenameB);
-  }
-}
-
-void Cartridge::unload_cart_st() {
-  if(stA.ram) save_file(get_save_filename(stA.fn, "srm"), stA.ram, stA.ram_size);
-  if(stB.ram) save_file(get_save_filename(stB.fn, "srm"), stB.ram, stB.ram_size);
-}
-
-#endif //ifdef CART_CPP

src/cartridge/cartridge.cpp

@@ -0,0 +1,157 @@
+#include <../base.hpp>
+
+#define CARTRIDGE_CPP
+namespace SNES {
+
+#include "header.cpp"
+
+namespace memory {
+  MappedRAM cartrom, cartram, cartrtc;
+  MappedRAM bsxflash, bsxram, bsxpram;
+  MappedRAM stArom, stAram;
+  MappedRAM stBrom, stBram;
+  MappedRAM gbrom, gbram;
+};
+
+Cartridge cartridge;
+
+void Cartridge::load(Mode cartridge_mode) {
+  cartinfo_t cartinfo;
+  read_header(cartinfo, memory::cartrom.data(), memory::cartrom.size());
+  set_cartinfo(cartinfo);
+
+  set(mode, cartridge_mode);
+
+  if(cartinfo.ram_size > 0) {
+    memory::cartram.map(new(zeromemory) uint8_t[cartinfo.ram_size], cartinfo.ram_size);
+  }
+
+  if(cartinfo.srtc || cartinfo.spc7110rtc) {
+    memory::cartrtc.map(new(zeromemory) uint8_t[20], 20);
+  }
+
+  if(mode() == ModeBsx) {
+    memory::bsxram.map (new(zeromemory) uint8_t[ 32 * 1024],  32 * 1024);
+    memory::bsxpram.map(new(zeromemory) uint8_t[512 * 1024], 512 * 1024);
+  }
+
+  if(mode() == ModeSufamiTurbo) {
+    if(memory::stArom.data()) memory::stAram.map(new(zeromemory) uint8_t[128 * 1024], 128 * 1024);
+    if(memory::stBrom.data()) memory::stBram.map(new(zeromemory) uint8_t[128 * 1024], 128 * 1024);
+  }
+
+  if(mode() == ModeSuperGameBoy) {
+    if(memory::gbrom.data()) memory::gbram.map(new(zeromemory) uint8_t[64 * 1024], 64 * 1024);
+  }
+
+  memory::cartrom.write_protect(true);
+  memory::cartram.write_protect(false);
+  memory::cartrtc.write_protect(false);
+  memory::bsxflash.write_protect(true);
+  memory::bsxram.write_protect(false);
+  memory::bsxpram.write_protect(false);
+  memory::stArom.write_protect(true);
+  memory::stAram.write_protect(false);
+  memory::stBrom.write_protect(true);
+  memory::stBram.write_protect(false);
+  memory::gbrom.write_protect(true);
+  memory::gbram.write_protect(false);
+
+  bus.load_cart();
+  set(loaded, true);
+}
+
+void Cartridge::unload() {
+  memory::cartrom.reset();
+  memory::cartram.reset();
+  memory::cartrtc.reset();
+  memory::bsxflash.reset();
+  memory::bsxram.reset();
+  memory::bsxpram.reset();
+  memory::stArom.reset();
+  memory::stAram.reset();
+  memory::stBrom.reset();
+  memory::stBram.reset();
+  memory::gbrom.reset();
+  memory::gbram.reset();
+
+  if(loaded() == false) return;
+  bus.unload_cart();
+  set(loaded, false);
+}
+
+Cartridge::Type Cartridge::detect_image_type(uint8_t *data, unsigned size) const {
+  cartinfo_t info;
+  read_header(info, data, size);
+  return info.type;
+}
+
+Cartridge::Cartridge() {
+  set(loaded, false);
+  unload();
+}
+
+Cartridge::~Cartridge() {
+  unload();
+}
+
+void Cartridge::set_cartinfo(const Cartridge::cartinfo_t &source) {
+  set(region,         source.region);
+  set(mapper,         source.mapper);
+  set(dsp1_mapper,    source.dsp1_mapper);
+
+  set(has_bsx_slot,   source.bsx_slot);
+  set(has_superfx,    source.superfx);
+  set(has_sa1,        source.sa1);
+  set(has_srtc,       source.srtc);
+  set(has_sdd1,       source.sdd1);
+  set(has_spc7110,    source.spc7110);
+  set(has_spc7110rtc, source.spc7110rtc);
+  set(has_cx4,        source.cx4);
+  set(has_dsp1,       source.dsp1);
+  set(has_dsp2,       source.dsp2);
+  set(has_dsp3,       source.dsp3);
+  set(has_dsp4,       source.dsp4);
+  set(has_obc1,       source.obc1);
+  set(has_st010,      source.st010);
+  set(has_st011,      source.st011);
+  set(has_st018,      source.st018);
+}
+
+//==========
+//cartinfo_t
+//==========
+
+void Cartridge::cartinfo_t::reset() {
+  type        = TypeUnknown;
+  mapper      = LoROM;
+  dsp1_mapper = DSP1Unmapped;
+  region      = NTSC;
+
+  rom_size = 0;
+  ram_size = 0;
+
+  bsx_slot   = false;
+  superfx    = false;
+  sa1        = false;
+  srtc       = false;
+  sdd1       = false;
+  spc7110    = false;
+  spc7110rtc = false;
+  cx4        = false;
+  dsp1       = false;
+  dsp2       = false;
+  dsp3       = false;
+  dsp4       = false;
+  obc1       = false;
+  st010      = false;
+  st011      = false;
+  st018      = false;
+}
+
+Cartridge::cartinfo_t::cartinfo_t() {
+  reset();
+}
+
+};
+

src/cartridge/cartridge.hpp

@@ -0,0 +1,130 @@
+class Cartridge : public property {
+public:
+  enum Mode {
+    ModeNormal,
+    ModeBsxSlotted,
+    ModeBsx,
+    ModeSufamiTurbo,
+    ModeSuperGameBoy,
+  };
+
+  enum Type {
+    TypeNormal,
+    TypeBsxSlotted,
+    TypeBsxBios,
+    TypeBsx,
+    TypeSufamiTurboBios,
+    TypeSufamiTurbo,
+    TypeSuperGameBoyBios,
+    TypeGameBoy,
+    TypeUnknown,
+  };
+
+  enum Region {
+    NTSC,
+    PAL,
+  };
+
+  enum MemoryMapper {
+    LoROM,
+    HiROM,
+    ExLoROM,
+    ExHiROM,
+    SA1ROM,
+    SPC7110ROM,
+    BSCLoROM,
+    BSCHiROM,
+    BSXROM,
+    STROM,
+  };
+
+  enum DSP1MemoryMapper {
+    DSP1Unmapped,
+    DSP1LoROM1MB,
+    DSP1LoROM2MB,
+    DSP1HiROM,
+  };
+
+  //properties can be read via operator(), eg "if(cartridge.loaded() == true)";
+  //warning: if loaded() == false, no other property is considered valid!
+
+  property_t<bool> loaded;  //is a base cartridge inserted?
+
+  property_t<Mode>             mode;
+  property_t<Region>           region;
+  property_t<MemoryMapper>     mapper;
+  property_t<DSP1MemoryMapper> dsp1_mapper;
+
+  property_t<bool> has_bsx_slot;
+  property_t<bool> has_superfx;
+  property_t<bool> has_sa1;
+  property_t<bool> has_srtc;
+  property_t<bool> has_sdd1;
+  property_t<bool> has_spc7110, has_spc7110rtc;
+  property_t<bool> has_cx4;
+  property_t<bool> has_dsp1, has_dsp2, has_dsp3, has_dsp4;
+  property_t<bool> has_obc1;
+  property_t<bool> has_st010, has_st011, has_st018;
+
+  //main interface
+  void load(Mode);
+//void read();
+//void load();
+  void unload();
+  Type detect_image_type(uint8_t *data, unsigned size) const;
+
+  Cartridge();
+  ~Cartridge();
+
+private:
+  struct cartinfo_t {
+    Type type;
+    Region region;
+    MemoryMapper mapper;
+    DSP1MemoryMapper dsp1_mapper;
+    unsigned rom_size, ram_size;
+
+    bool bsx_slot;
+    bool superfx;
+    bool sa1;
+    bool srtc;
+    bool sdd1;
+    bool spc7110, spc7110rtc;
+    bool cx4;
+    bool dsp1, dsp2, dsp3, dsp4;
+    bool obc1;
+    bool st010, st011, st018;
+
+    void reset();
+    cartinfo_t();
+  };
+
+  enum HeaderField {
+    CartName    = 0x00,
+    Mapper      = 0x15,
+    RomType     = 0x16,
+    RomSize     = 0x17,
+    RamSize     = 0x18,
+    CartRegion  = 0x19,
+    Company     = 0x1a,
+    Version     = 0x1b,
+    Complement  = 0x1c,  //inverse checksum
+    Checksum    = 0x1e,
+    ResetVector = 0x3c,
+  };
+
+  void read_header(cartinfo_t &info, const uint8_t *data, unsigned size) const;
+  unsigned find_header(const uint8_t *data, unsigned size) const;
+  unsigned score_header(const uint8_t *data, unsigned size, unsigned addr) const;
+  void set_cartinfo(const cartinfo_t&);
+};
+
+namespace memory {
+  extern MappedRAM cartrom, cartram, cartrtc;
+  extern MappedRAM bsxflash, bsxram, bsxpram;
+  extern MappedRAM stArom, stAram;
+  extern MappedRAM stBrom, stBram;
+  extern MappedRAM gbrom, gbram;
+};
+
+extern Cartridge cartridge;

src/cartridge/header.cpp

@@ -0,0 +1,294 @@
+#ifdef CARTRIDGE_CPP
+
+void Cartridge::read_header(cartinfo_t &info, const uint8_t *data, unsigned size) const {
+  info.reset();
+
+  //=====================
+  //detect Game Boy carts
+  //=====================
+
+  if(size >= 0x0140) {
+    if(data[0x0104] == 0xce && data[0x0105] == 0xed && data[0x0106] == 0x66 && data[0x0107] == 0x66
+    && data[0x0108] == 0xcc && data[0x0109] == 0x0d && data[0x010a] == 0x00 && data[0x010b] == 0x0b) {
+      info.type = TypeGameBoy;
+      return;
+    }
+  }
+
+  const unsigned index = find_header(data, size);
+  const uint8 mapper   = data[index + Mapper];
+  const uint8 rom_type = data[index + RomType];
+  const uint8 rom_size = data[index + RomSize];
+  const uint8 company  = data[index + Company];
+  const uint8 region   = data[index + CartRegion] & 0x7f;
+
+  if(data[index + RamSize] & 7) {
+    info.ram_size = 1024 << (data[index + RamSize] & 7);
+  } else {
+    info.ram_size = 0;
+  }
+
+  //0, 1, 13 = NTSC; 2 - 12 = PAL
+  info.region = (region <= 1 || region >= 13) ? NTSC : PAL;
+
+  //=======================
+  //detect BS-X flash carts
+  //=======================
+
+  if(data[index + 0x13] == 0x00 || data[index + 0x13] == 0xff) {
+    if(data[index + 0x14] == 0x00) {
+      const uint8_t n15 = data[index + 0x15];
+      if(n15 == 0x00 || n15 == 0x80 || n15 == 0x84 || n15 == 0x9c || n15 == 0xbc || n15 == 0xfc) {
+        if(data[index + 0x1a] == 0x33 || data[index + 0x1a] == 0xff) {
+          info.type = TypeBsx;
+          info.mapper = BSXROM;
+          info.region = NTSC;  //BS-X only released in Japan
+          return;
+        }
+      }
+    }
+  }
+
+  //=========================
+  //detect Sufami Turbo carts
+  //=========================
+
+  if(!memcmp(data, "BANDAI SFC-ADX", 14)) {
+    if(!memcmp(data + 16, "SFC-ADX BACKUP", 14)) {
+      info.type = TypeSufamiTurboBios;
+    } else {
+      info.type = TypeSufamiTurbo;
+    }
+    info.mapper = STROM;
+    info.region = NTSC;  //Sufami Turbo only released in Japan
+    return;              //RAM size handled internally by load_cart_st();
+  }
+
+  //==========================
+  //detect Super Game Boy BIOS
+  //==========================
+
+  if(!memcmp(data + index, "Super GAMEBOY", 13)) {
+    info.type = TypeSuperGameBoyBios;
+    return;
+  }
+
+  //=====================
+  //detect standard carts
+  //=====================
+
+  //detect presence of BS-X flash cartridge connector (reads extended header information)
+  if(data[index - 14] == 'Z') {
+    if(data[index - 11] == 'J') {
+      uint8 n13 = data[index - 13];
+      if((n13 >= 'A' && n13 <= 'Z') || (n13 >= '0' && n13 <= '9')) {
+        if(company == 0x33 || (data[index - 10] == 0x00 && data[index - 4] == 0x00)) {
+          info.bsx_slot = true;
+        }
+      }
+    }
+  }
+
+  if(info.bsx_slot == true) {
+    if(!memcmp(data + index, "Satellaview BS-X     ", 21)) {
+      //BS-X base cart
+      info.type = TypeBsxBios;
+      info.mapper = BSXROM;
+      info.region = NTSC;  //BS-X only released in Japan
+      return;              //RAM size handled internally by load_cart_bsx() -> BSXCart class
+    } else {
+      info.type = TypeBsxSlotted;
+      info.mapper = (index == 0x7fc0 ? BSCLoROM : BSCHiROM);
+    }
+  } else {
+    //standard cart
+    info.type = TypeNormal;
+
+    if(index == 0x7fc0 && size >= 0x401000) {
+      info.mapper = ExLoROM;
+    } else if(index == 0x7fc0 && mapper == 0x32) {
+      info.mapper = ExLoROM;
+    } else if(index == 0x7fc0) {
+      info.mapper = LoROM;
+    } else if(index == 0xffc0) {
+      info.mapper = HiROM;
+    } else {  //index == 0x40ffc0
+      info.mapper = ExHiROM;
+    }
+  }
+
+  if(mapper == 0x20 && (rom_type == 0x13 || rom_type == 0x14 || rom_type == 0x15 || rom_type == 0x1a)) {
+    info.superfx = true;
+  }
+
+  if(mapper == 0x23 && (rom_type == 0x32 || rom_type == 0x34 || rom_type == 0x35)) {
+    info.sa1 = true;
+    info.mapper = SA1ROM;
+  }
+
+  if(mapper == 0x35 && rom_type == 0x55) {
+    info.srtc = true;
+  }
+
+  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
+    info.sdd1 = true;
+  }
+
+  if(mapper == 0x3a && (rom_type == 0xf5 || rom_type == 0xf9)) {
+    info.spc7110 = true;
+    info.spc7110rtc = (rom_type == 0xf9);
+    info.mapper = SPC7110ROM;
+  }
+
+  if(mapper == 0x20 && rom_type == 0xf3) {
+    info.cx4 = true;
+  }
+
+  if((mapper == 0x20 || mapper == 0x21) && rom_type == 0x03) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x05 && company != 0xb2) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x31 && (rom_type == 0x03 || rom_type == 0x05)) {
+    info.dsp1 = true;
+  }
+
+  if(info.dsp1 == true) {
+    if((mapper & 0x2f) == 0x20 && size <= 0x100000) {
+      info.dsp1_mapper = DSP1LoROM1MB;
+    } else if((mapper & 0x2f) == 0x20) {
+      info.dsp1_mapper = DSP1LoROM2MB;
+    } else if((mapper & 0x2f) == 0x21) {
+      info.dsp1_mapper = DSP1HiROM;
+    }
+  }
+
+  if(mapper == 0x20 && rom_type == 0x05) {
+    info.dsp2 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x05 && company == 0xb2) {
+    info.dsp3 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x03) {
+    info.dsp4 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x25) {
+    info.obc1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf6 && rom_size >= 10) {
+    info.st010 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf6 && rom_size < 10) {
+    info.st011 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf5) {
+    info.st018 = true;
+  }
+}
+
+unsigned Cartridge::find_header(const uint8_t *data, unsigned size) const {
+  unsigned score_lo = score_header(data, size, 0x007fc0);
+  unsigned score_hi = score_header(data, size, 0x00ffc0);
+  unsigned score_ex = score_header(data, size, 0x40ffc0);
+  if(score_ex) score_ex += 4;  //favor ExHiROM on images > 32mbits
+
+  if(score_lo >= score_hi && score_lo >= score_ex) {
+    return 0x007fc0;
+  } else if(score_hi >= score_ex) {
+    return 0x00ffc0;
+  } else {
+    return 0x40ffc0;
+  }
+}
+
+unsigned Cartridge::score_header(const uint8_t *data, unsigned size, unsigned addr) const {
+  if(size < addr + 64) return 0;  //image too small to contain header at this location?
+  int score = 0;
+
+  uint16 resetvector = data[addr + ResetVector] | (data[addr + ResetVector + 1] << 8);
+  uint16 checksum    = data[addr + Checksum   ] | (data[addr + Checksum    + 1] << 8);
+  uint16 complement  = data[addr + Complement ] | (data[addr + Complement  + 1] << 8);
+
+  uint8 resetop = data[(addr & ~0x7fff) | (resetvector & 0x7fff)];  //first opcode executed upon reset
+  uint8 mapper  = data[addr + Mapper] & ~0x10;                      //mask off irrelevent FastROM-capable bit
+
+  //$00:[000-7fff] contains uninitialized RAM and MMIO.
+  //reset vector must point to ROM at $00:[8000-ffff] to be considered valid.
+  if(resetvector < 0x8000) return 0;
+
+  //some images duplicate the header in multiple locations, and others have completely
+  //invalid header information that cannot be relied upon.
+  //below code will analyze the first opcode executed at the specified reset vector to
+  //determine the probability that this is the correct header.
+
+  //most likely opcodes
+  if(resetop == 0x78  //sei
+  || resetop == 0x18  //clc (clc; xce)
+  || resetop == 0x38  //sec (sec; xce)
+  || resetop == 0x9c  //stz $nnnn (stz $4200)
+  || resetop == 0x4c  //jmp $nnnn
+  || resetop == 0x5c  //jml $nnnnnn
+  ) score += 8;
+
+  //plausible opcodes
+  if(resetop == 0xc2  //rep #$nn
+  || resetop == 0xe2  //sep #$nn
+  || resetop == 0xad  //lda $nnnn
+  || resetop == 0xae  //ldx $nnnn
+  || resetop == 0xac  //ldy $nnnn
+  || resetop == 0xaf  //lda $nnnnnn
+  || resetop == 0xa9  //lda #$nn
+  || resetop == 0xa2  //ldx #$nn
+  || resetop == 0xa0  //ldy #$nn
+  || resetop == 0x20  //jsr $nnnn
+  || resetop == 0x22  //jsl $nnnnnn
+  ) score += 4;
+
+  //implausible opcodes
+  if(resetop == 0x40  //rti
+  || resetop == 0x60  //rts
+  || resetop == 0x6b  //rtl
+  || resetop == 0xcd  //cmp $nnnn
+  || resetop == 0xec  //cpx $nnnn
+  || resetop == 0xcc  //cpy $nnnn
+  ) score -= 4;
+
+  //least likely opcodes
+  if(resetop == 0x00  //brk #$nn
+  || resetop == 0x02  //cop #$nn
+  || resetop == 0xdb  //stp
+  || resetop == 0x42  //wdm
+  || resetop == 0xff  //sbc $nnnnnn,x
+  ) score -= 8;
+
+  //at times, both the header and reset vector's first opcode will match ...
+  //fallback and rely on info validity in these cases to determine more likely header.
+
+  //a valid checksum is the biggest indicator of a valid header.
+  if((checksum + complement) == 0xffff && (checksum != 0) && (complement != 0)) score += 4;
+
+  if(addr == 0x007fc0 && mapper == 0x20) score += 2;  //0x20 is usually LoROM
+  if(addr == 0x00ffc0 && mapper == 0x21) score += 2;  //0x21 is usually HiROM
+  if(addr == 0x007fc0 && mapper == 0x22) score += 2;  //0x22 is usually ExLoROM
+  if(addr == 0x40ffc0 && mapper == 0x25) score += 2;  //0x25 is usually ExHiROM
+
+  if(data[addr + Company] == 0x33) score += 2;        //0x33 indicates extended header
+  if(data[addr + RomType] < 0x08) score++;
+  if(data[addr + RomSize] < 0x10) score++;
+  if(data[addr + RamSize] < 0x08) score++;
+  if(data[addr + CartRegion] < 14) score++;
+
+  if(score < 0) score = 0;
+  return score;
+}
+
+#endif

src/cc.bat

@@ -1,3 +1,3 @@
-@make platform=win compiler=mingw32-gcc
-::@make platform=win compiler=mingw32-gcc enable_gzip=true enable_jma=true
+@mingw32-make
+::@mingw32-make enable_gzip=true enable_jma=true
 @pause

src/cc.sh

@@ -1,2 +0,0 @@
-make platform=x compiler=gcc
-#make platform=x compiler=gcc enable_gzip=true enable_jma=true

src/cheat/cheat.cpp

@@ -1,98 +1,348 @@
-#include "../base.h"
-#include "../reader/filereader.h"
+#include <../base.hpp>
+
+#define CHEAT_CPP
+namespace SNES {
 
 Cheat cheat;
 
-/*****
- * string <> binary code translation routines
- * decode() "7e1234:56" ->  0x7e123456
- * encode()  0x7e123456 -> "7e1234:56"
- *****/
+Cheat::cheat_t& Cheat::cheat_t::operator=(const Cheat::cheat_t& source) {
+  enabled = source.enabled;
+  code = source.code;
+  desc = source.desc;
+  count = source.count;
+
+  addr.reset();
+  data.reset();
+  for(unsigned n = 0; n < count; n++) {
+    addr[n] = source.addr[n];
+    data[n] = source.data[n];
+  }
+
+  return *this;
+}
+
+//used to sort cheat code list by description
+bool Cheat::cheat_t::operator<(const Cheat::cheat_t& source) {
+  return strcmp(desc, source.desc) < 0;
+}
+
+//parse item ("0123-4567+89AB-CDEF"), return cheat_t item
+//return true if code is valid, false otherwise
+bool Cheat::decode(const char *s, Cheat::cheat_t &item) const {
+  item.enabled = false;
+  item.count = 0;
+
+  lstring list;
+  list.split("+", s);
+
+  for(unsigned n = 0; n < list.size(); n++) {
+    unsigned addr;
+    uint8_t data;
+    type_t type;
+    if(decode(list[n], addr, data, type) == false) return false;
+
+    item.addr[item.count] = addr;
+    item.data[item.count] = data;
+    item.count++;
+  }
+
+  return true;
+}
+
+//read() is used by MemBus::read() if Cheat::enabled(addr) returns true to look up cheat code.
+//returns true if cheat code was found, false if it was not.
+//when true, cheat code substitution value is stored in data.
+bool Cheat::read(unsigned addr, uint8_t &data) const {
+  addr = mirror_address(addr);
+  for(unsigned i = 0; i < code.size(); i++) {
+    if(enabled(i) == false) continue;
+
+    for(unsigned n = 0; n < code[i].count; n++) {
+      if(addr == mirror_address(code[i].addr[n])) {
+        data = code[i].data[n];
+        return true;
+      }
+    }
+  }
+
+  //code not found, or code is disabled
+  return false;
+}
+
+//==============
+//master control
+//==============
+
+//global cheat system enable/disable:
+//if disabled, *all* cheat codes are disabled;
+//otherwise only individually disabled codes are.
+
+bool Cheat::enabled() const {
+  return cheat_system_enabled;
+}
+
+void Cheat::enable() {
+  cheat_system_enabled = true;
+  cheat_enabled = (cheat_system_enabled && cheat_enabled_code_exists);
+}
+
+void Cheat::disable() {
+  cheat_system_enabled = false;
+  cheat_enabled = false;
+}
+
+//================================
+//cheat list manipulation routines
+//================================
+
+bool Cheat::add(bool enable, const char *code_, const char *desc_) {
+  cheat_t item;
+  if(decode(code_, item) == false) return false;
+
+  unsigned i = code.size();
+  code[i] = item;
+  code[i].enabled = enable;
+  code[i].desc = desc_;
+  code[i].code = code_;
+  encode_description(code[i].desc);
+  update(code[i]);
+
+  update_cheat_status();
+  return true;
+}
+
+bool Cheat::edit(unsigned i, bool enable, const char *code_, const char *desc_) {
+  cheat_t item;
+  if(decode(code_, item) == false) return false;
+
+  //disable current code and clear from code lookup table
+  code[i].enabled = false;
+  update(code[i]);
+
+  code[i] = item;
+  code[i].enabled = enable;
+  code[i].desc = desc_;
+  code[i].code = code_;
+  encode_description(code[i].desc);
+  update(code[i]);
+
+  update_cheat_status();
+  return true;
+}
+
+bool Cheat::remove(unsigned i) {
+  unsigned size = code.size();
+  if(i >= size) return false;  //also verifies size cannot be < 1
+
+  for(unsigned n = i; n < size - 1; n++) code[n] = code[n + 1];
+  code.resize(size - 1);
+
+  update_cheat_status();
+  return true;
+}
+
+bool Cheat::get(unsigned i, cheat_t &item) const {
+  if(i >= code.size()) return false;
+
+  item = code[i];
+  decode_description(item.desc);
+  return true;
+}
+
+//==============================
+//cheat status modifier routines
+//==============================
+
+bool Cheat::enabled(unsigned i) const {
+  return (i < code.size() ? code[i].enabled : false);
+}
+
+void Cheat::enable(unsigned i) {
+  if(i >= code.size()) return;
+
+  code[i].enabled = true;
+  update(code[i]);
+  update_cheat_status();
+}
+
+void Cheat::disable(unsigned i) {
+  if(i >= code.size()) return;
+
+  code[i].enabled = false;
+  update(code[i]);
+  update_cheat_status();
+}
+
+//===============================
+//cheat file load / save routines
+//
+//file format:
+//"description", status, nnnn-nnnn[+nnnn-nnnn...]\r\n
+//...
+//===============================
+
+void Cheat::load(string data) {
+  data.replace("\r\n", "\n");
+  data.qreplace(" ", "");
+
+  lstring line;
+  line.split("\n", data);
+  for(unsigned i = 0; i < line.size(); i++) {
+    lstring part;
+    part.qsplit(",", line[i]);
+    if(part.size() != 3) continue;
+    trim(part[0], "\"");
+    add(part[1] == "enabled", /* code = */ part[2], /* desc = */ part[0]);
+  }
+}
+
+string Cheat::save() const {
+  string data;
+  for(unsigned i = 0; i < code.size(); i++) {
+    data << "\"" << code[i].desc << "\", "
+         << (code[i].enabled ? "enabled, " : "disabled, ")
+         << code[i].code << "\r\n";
+  }
+  return data;
+}
+
+void Cheat::clear() {
+  cheat_enabled_code_exists = false;
+  memset(mask, 0, 0x200000);
+  code.reset();
+}
+
+Cheat::Cheat() : cheat_system_enabled(true) {
+  clear();
+}
+
+//==================
+//internal functions
+//==================
+
+//string <> binary code translation routines
+//decode() "7e123456" -> 0x7e123456
+//encode() 0x7e123456 -> "7e123456"
+
+bool Cheat::decode(const char *s, unsigned &addr, uint8_t &data, type_t &type) const {
+  string t = s;
+  strlower(t);
+
+  #define ischr(n) ((n >= '0' && n <= '9') || (n >= 'a' && n <= 'f'))
+
+  if(strlen(t) == 8 || (strlen(t) == 9 && t[6] == ':')) {
+    //strip ':'
+    if(strlen(t) == 9 && t[6] == ':') t = string() << substr(t, 0, 6) << substr(t, 7);
+    //validate input
+    for(unsigned i = 0; i < 8; i++) if(!ischr(t[i])) return false;
 
-bool Cheat::decode(char *str, uint32 &addr, uint8 &data, uint8 &type) {
-  string t, part;
-  strcpy(t, str);
-  strlower(t());
-  if(strlen(t) == 8 || (strlen(t) == 9 && t()[6] == ':')) {
     type = ProActionReplay;
-    replace(t, ":", "");
-    uint32 r = strhex((const char*)t);
+    unsigned r = strhex((const char*)t);
     addr = r >> 8;
     data = r & 0xff;
     return true;
-  } else if(strlen(t) == 9 && t()[4] == '-') {
+  } else if(strlen(t) == 9 && t[4] == '-') {
+    //strip '-'
+    t = string() << substr(t, 0, 4) << substr(t, 5);
+    //validate input
+    for(unsigned i = 0; i < 8; i++) if(!ischr(t[i])) return false;
+
     type = GameGenie;
-    replace(t, "-", "");
     strtr(t, "df4709156bc8a23e", "0123456789abcdef");
-    uint32 r = strhex((const char*)t);
+    unsigned r = strhex((const char*)t);
     //8421 8421 8421 8421 8421 8421
     //abcd efgh ijkl mnop qrst uvwx
     //ijkl qrst opab cduv wxef ghmn
-    addr = (!!(r & 0x002000) << 23) | (!!(r & 0x001000) << 22) |
-           (!!(r & 0x000800) << 21) | (!!(r & 0x000400) << 20) |
-           (!!(r & 0x000020) << 19) | (!!(r & 0x000010) << 18) |
-           (!!(r & 0x000008) << 17) | (!!(r & 0x000004) << 16) |
-           (!!(r & 0x800000) << 15) | (!!(r & 0x400000) << 14) |
-           (!!(r & 0x200000) << 13) | (!!(r & 0x100000) << 12) |
-           (!!(r & 0x000002) << 11) | (!!(r & 0x000001) << 10) |
-           (!!(r & 0x008000) <<  9) | (!!(r & 0x004000) <<  8) |
-           (!!(r & 0x080000) <<  7) | (!!(r & 0x040000) <<  6) |
-           (!!(r & 0x020000) <<  5) | (!!(r & 0x010000) <<  4) |
-           (!!(r & 0x000200) <<  3) | (!!(r & 0x000100) <<  2) |
-           (!!(r & 0x000080) <<  1) | (!!(r & 0x000040) <<  0);
+    addr = (!!(r & 0x002000) << 23) | (!!(r & 0x001000) << 22)
+         | (!!(r & 0x000800) << 21) | (!!(r & 0x000400) << 20)
+         | (!!(r & 0x000020) << 19) | (!!(r & 0x000010) << 18)
+         | (!!(r & 0x000008) << 17) | (!!(r & 0x000004) << 16)
+         | (!!(r & 0x800000) << 15) | (!!(r & 0x400000) << 14)
+         | (!!(r & 0x200000) << 13) | (!!(r & 0x100000) << 12)
+         | (!!(r & 0x000002) << 11) | (!!(r & 0x000001) << 10)
+         | (!!(r & 0x008000) <<  9) | (!!(r & 0x004000) <<  8)
+         | (!!(r & 0x080000) <<  7) | (!!(r & 0x040000) <<  6)
+         | (!!(r & 0x020000) <<  5) | (!!(r & 0x010000) <<  4)
+         | (!!(r & 0x000200) <<  3) | (!!(r & 0x000100) <<  2)
+         | (!!(r & 0x000080) <<  1) | (!!(r & 0x000040) <<  0);
     data = r >> 24;
     return true;
+  } else {
+    return false;
   }
-  return false;
 }
 
-bool Cheat::encode(char *str, uint32 addr, uint8 data, uint8 type) {
+bool Cheat::encode(string &s, unsigned addr, uint8_t data, type_t type) const {
+  char t[16];
+
   if(type == ProActionReplay) {
-    sprintf(str, "%0.6x:%0.2x", addr, data);
+    sprintf(t, "%.6x%.2x", addr, data);
+    s = t;
     return true;
   } else if(type == GameGenie) {
-  uint32 r = addr;
-    addr = (!!(r & 0x008000) << 23) | (!!(r & 0x004000) << 22) |
-           (!!(r & 0x002000) << 21) | (!!(r & 0x001000) << 20) |
-           (!!(r & 0x000080) << 19) | (!!(r & 0x000040) << 18) |
-           (!!(r & 0x000020) << 17) | (!!(r & 0x000010) << 16) |
-           (!!(r & 0x000200) << 15) | (!!(r & 0x000100) << 14) |
-           (!!(r & 0x800000) << 13) | (!!(r & 0x400000) << 12) |
-           (!!(r & 0x200000) << 11) | (!!(r & 0x100000) << 10) |
-           (!!(r & 0x000008) <<  9) | (!!(r & 0x000004) <<  8) |
-           (!!(r & 0x000002) <<  7) | (!!(r & 0x000001) <<  6) |
-           (!!(r & 0x080000) <<  5) | (!!(r & 0x040000) <<  4) |
-           (!!(r & 0x020000) <<  3) | (!!(r & 0x010000) <<  2) |
-           (!!(r & 0x000800) <<  1) | (!!(r & 0x000400) <<  0);
-    sprintf(str, "%0.2x%0.2x-%0.4x", data, addr >> 16, addr & 0xffff);
-    strtr(str, "0123456789abcdef", "df4709156bc8a23e");
+    unsigned r = addr;
+    addr = (!!(r & 0x008000) << 23) | (!!(r & 0x004000) << 22)
+         | (!!(r & 0x002000) << 21) | (!!(r & 0x001000) << 20)
+         | (!!(r & 0x000080) << 19) | (!!(r & 0x000040) << 18)
+         | (!!(r & 0x000020) << 17) | (!!(r & 0x000010) << 16)
+         | (!!(r & 0x000200) << 15) | (!!(r & 0x000100) << 14)
+         | (!!(r & 0x800000) << 13) | (!!(r & 0x400000) << 12)
+         | (!!(r & 0x200000) << 11) | (!!(r & 0x100000) << 10)
+         | (!!(r & 0x000008) <<  9) | (!!(r & 0x000004) <<  8)
+         | (!!(r & 0x000002) <<  7) | (!!(r & 0x000001) <<  6)
+         | (!!(r & 0x080000) <<  5) | (!!(r & 0x040000) <<  4)
+         | (!!(r & 0x020000) <<  3) | (!!(r & 0x010000) <<  2)
+         | (!!(r & 0x000800) <<  1) | (!!(r & 0x000400) <<  0);
+    sprintf(t, "%.2x%.2x-%.4x", data, addr >> 16, addr & 0xffff);
+    strtr(t, "0123456789abcdef", "df4709156bc8a23e");
+    s = t;
     return true;
+  } else {
+    return false;
   }
-  return false;
 }
 
-/*****
- * address lookup table manipulation and mirroring
- * mirror_address() 0x000000 -> 0x7e0000
- * set() enable specified address, mirror accordingly
- * clear() disable specified address, mirror accordingly
- *****/
+//speed up S-CPU memory reads by disabling cheat code lookup when either:
+//a) cheat system is disabled by user, or b) no enabled cheat codes exist
+void Cheat::update_cheat_status() {
+  for(unsigned i = 0; i < code.size(); i++) {
+    if(code[i].enabled) {
+      cheat_enabled_code_exists = true;
+      cheat_enabled = (cheat_system_enabled && cheat_enabled_code_exists);
+      return;
+    }
+  }
+  cheat_enabled_code_exists = false;
+  cheat_enabled = false;
+}
 
-uint Cheat::mirror_address(uint addr) {
+//address lookup table manipulation and mirroring
+//mirror_address() 0x000000 -> 0x7e0000
+//set() enable specified address, mirror accordingly
+//clear() disable specified address, mirror accordingly
+unsigned Cheat::mirror_address(unsigned addr) const {
   if((addr & 0x40e000) != 0x0000) return addr;
   //8k WRAM mirror
   //$[00-3f|80-bf]:[0000-1fff] -> $7e:[0000-1fff]
   return (0x7e0000 + (addr & 0x1fff));
 }
 
-void Cheat::set(uint32 addr) {
+//updates mask[] table enabled bits;
+//must be called after modifying item.enabled state.
+void Cheat::update(const cheat_t &item) {
+  for(unsigned n = 0; n < item.count; n++) {
+    (item.enabled) ? set(item.addr[n]) : clear(item.addr[n]);
+  }
+}
+
+void Cheat::set(unsigned addr) {
   addr = mirror_address(addr);
 
   mask[addr >> 3] |= 1 << (addr & 7);
   if((addr & 0xffe000) == 0x7e0000) {
     //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
-    uint mirror;
-    for(int x = 0; x <= 0x3f; x++) {
+    unsigned mirror;
+    for(unsigned x = 0; x <= 0x3f; x++) {
       mirror = ((0x00 + x) << 16) + (addr & 0x1fff);
       mask[mirror >> 3] |= 1 << (mirror & 7);
       mirror = ((0x80 + x) << 16) + (addr & 0x1fff);
@@ -101,20 +351,20 @@ void Cheat::set(uint32 addr) {
   }
 }
 
-void Cheat::clear(uint32 addr) {
+void Cheat::clear(unsigned addr) {
   addr = mirror_address(addr);
 
-  //is there more than one cheat code using the same address
-  //(and likely a different override value) that is enabled?
-  //if so, do not clear code lookup table entry for this address.
-  uint8 r;
-  if(read(addr, r) == true)return;
+  //if there is more than one cheat code using the same address,
+  //(eg with a different override value) then do not clear code
+  //lookup table entry.
+  uint8_t r;
+  if(read(addr, r) == true) return;
 
   mask[addr >> 3] &= ~(1 << (addr & 7));
   if((addr & 0xffe000) == 0x7e0000) {
     //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
-    uint mirror;
-    for(int x = 0; x <= 0x3f; x++) {
+    unsigned mirror;
+    for(unsigned x = 0; x <= 0x3f; x++) {
       mirror = ((0x00 + x) << 16) + (addr & 0x1fff);
       mask[mirror >> 3] &= ~(1 << (mirror & 7));
       mirror = ((0x80 + x) << 16) + (addr & 0x1fff);
@@ -123,207 +373,19 @@ void Cheat::clear(uint32 addr) {
   }
 }
 
-/*****
- * read() is used by MemBus::read() if Cheat::enabled(addr)
- * returns true to look up cheat code.
- * returns true if cheat code was found, false if it was not.
- * when true, cheat code substitution value is stored in data.
- *****/
+//these two functions are used to safely store description text inside .cfg file format.
 
-bool Cheat::read(uint32 addr, uint8 &data) {
-  addr = mirror_address(addr);
-  for(int i = 0; i < cheat_count; i++) {
-    if(enabled(i) == false) continue;
-    if(addr == mirror_address(index[i].addr)) {
-      data = index[i].data;
-      return true;
-    }
-  }
-  //code not found, or code is disabled
-  return false;
+string& Cheat::encode_description(string &desc) const {
+  desc.replace("\"", "\\q");
+  desc.replace("\n", "\\n");
+  return desc;
 }
 
-/*****
- * update_cheat_status() will scan to see if any codes are
- * enabled. if any are, make sure the cheat system is on.
- * otherwise, turn cheat system off to speed up emulation.
- *****/
-
-void Cheat::update_cheat_status() {
-  for(unsigned i = 0; i < cheat_count; i++) {
-    if(index[i].enabled) {
-      cheat_enabled = true;
-      return;
-    }
-  }
-  cheat_enabled = false;
-}
-
-/*****
- * cheat list manipulation routines
- *****/
-
-bool Cheat::add(bool enable, char *code, char *desc) {
-  if(cheat_count >= CheatLimit) return false;
-
-  uint32 addr, len;
-  uint8  data, type;
-  if(decode(code, addr, data, type) == false) return false;
-
-  index[cheat_count].enabled = enable;
-  index[cheat_count].addr = addr;
-  index[cheat_count].data = data;
-  len = strlen(code);
-  len = len > 16 ? 16 : len;
-  memcpy(index[cheat_count].code, code, len);
-  index[cheat_count].code[len] = 0;
-  len = strlen(desc);
-  len = len > 128 ? 128 : len;
-  memcpy(index[cheat_count].desc, desc, len);
-  index[cheat_count].desc[len] = 0;
-  cheat_count++;
-  (enable) ? set(addr) : clear(addr);
-
-  update_cheat_status();
-  return true;
-}
-
-bool Cheat::edit(uint32 n, bool enable, char *code, char *desc) {
-  if(n >= cheat_count) return false;
-
-  uint32 addr, len;
-  uint8  data, type;
-  if(decode(code, addr, data, type) == false) return false;
-
-  //disable current code and clear from code lookup table
-  index[n].enabled = false;
-  clear(index[n].addr);
-
-  //update code and enable in code lookup table
-  index[n].enabled = enable;
-  index[n].addr = addr;
-  index[n].data = data;
-  len = strlen(code);
-  len = len > 16 ? 16 : len;
-  memcpy(index[n].code, code, len);
-  index[n].code[len] = 0;
-  len = strlen(desc);
-  len = len > 128 ? 128 : len;
-  memcpy(index[n].desc, desc, len);
-  index[n].desc[len] = 0;
-  set(addr);
-
-  update_cheat_status();
-  return true;
-}
-
-bool Cheat::remove(uint32 n) {
-  if(n >= cheat_count) return false;
-
-  for(unsigned i = n; i < cheat_count; i++) {
-    index[i].enabled = index[i + 1].enabled;
-    index[i].addr    = index[i + 1].addr;
-    index[i].data    = index[i + 1].data;
-    strcpy(index[i].desc, index[i + 1].desc);
-  }
-
-  cheat_count--;
-
-  update_cheat_status();
-  return true;
-}
-
-bool Cheat::get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc) {
-  if(n >= cheat_count) return false;
-  enable = index[n].enabled;
-  addr   = index[n].addr;
-  data   = index[n].data;
-  strcpy(code, index[n].code);
-  strcpy(desc, index[n].desc);
-  return true;
-}
-
-/*****
- * code status modifier routines
- *****/
-
-bool Cheat::enabled(uint32 n) {
-  if(n >= cheat_count) return false;
-  return index[n].enabled;
-}
-
-void Cheat::enable(uint32 n) {
-  if(n >= cheat_count) return;
-  index[n].enabled = true;
-  set(index[n].addr);
-  update_cheat_status();
-}
-
-void Cheat::disable(uint32 n) {
-  if(n >= cheat_count) return;
-  index[n].enabled = false;
-  clear(index[n].addr);
-  update_cheat_status();
-}
-
-/*****
- * cheat file manipulation routines
- *****/
-
-/* file format: */
-/* nnnn-nnnn = status, "description" \r\n */
-/* ... */
-
-bool Cheat::load(const char *fn) {
-  string data;
-  if(!fread(data, fn)) return false;
-  replace(data, "\r\n", "\n");
-  qreplace(data, "=", ",");
-  qreplace(data, " ", "");
-
-  lstring line;
-  split(line, "\n", data);
-  for(unsigned i = 0; i < ::count(line); i++) {
-    lstring part;
-    split(part, ",", line[i]);
-    if(::count(part) != 3) continue;
-    trim(part[2], "\"");
-    add(part[1] == "enabled", part[0](), part[2]());
-  }
-
-  return true;
-}
-
-bool Cheat::save(const char *fn) {
-  FILE *fp = fopen(fn, "wb");
-  if(!fp) return false;
-  for(unsigned i = 0; i < cheat_count; i++) {
-    fprintf(fp, "%9s = %8s, \"%s\"\r\n",
-      index[i].code,
-      index[i].enabled ? "enabled" : "disabled",
-      index[i].desc);
-  }
-  fclose(fp);
-  return true;
-}
-
-/*****
- * initialization routines
- *****/
-
-void Cheat::clear() {
-  cheat_enabled = false;
-  cheat_count = 0;
-  memset(mask, 0, 0x200000);
-  for(unsigned i = 0; i <= CheatLimit; i++) {
-    index[i].enabled = false;
-    index[i].addr = 0x000000;
-    index[i].data = 0x00;
-    strcpy(index[i].code, "");
-    strcpy(index[i].desc, "");
-  }
-}
-
-Cheat::Cheat() {
-  clear();
+string& Cheat::decode_description(string &desc) const {
+  desc.replace("\\q", "\"");
+  desc.replace("\\n", "\n");
+  return desc;
 }
+
+};
+

src/cheat/cheat.h

@@ -1,51 +0,0 @@
-class Cheat {
-public:
-  enum { CheatLimit = 1024 };
-
-  enum Type {
-    ProActionReplay,
-    GameGenie,
-  };
-
-  struct CheatIndex {
-    bool enabled;
-    uint32 addr;
-    uint8 data;
-    char code[ 16 + 1];
-    char desc[128 + 1];
-  } index[CheatLimit + 1];
-
-  bool cheat_enabled;
-  uint32 cheat_count;
-  uint8 mask[0x200000];
-
-  inline bool enabled() { return cheat_enabled; }
-  inline uint count() { return cheat_count; }
-  inline bool exists(uint32 addr) { return bool(mask[addr >> 3] & 1 << (addr & 7)); }
-
-  bool decode(char *str, uint32 &addr, uint8 &data, uint8 &type);
-  bool encode(char *str, uint32  addr, uint8  data, uint8  type);
-
-  bool read(uint32 addr, uint8 &data);
-
-  void update_cheat_status();
-  bool add(bool enable, char *code, char *desc);
-  bool edit(uint32 n, bool enable, char *code, char *desc);
-  bool get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc);
-  bool remove(uint32 n);
-  bool enabled(uint32 n);
-  void enable(uint32 n);
-  void disable(uint32 n);
-  bool load(const char *fn);
-  bool save(const char *fn);
-  void clear();
-
-  Cheat();
-
-private:
-  uint mirror_address(uint addr);
-  void set(uint32 addr);
-  void clear(uint32 addr);
-};
-
-extern Cheat cheat;

src/cheat/cheat.hpp

@@ -0,0 +1,69 @@
+class Cheat {
+public:
+  enum type_t {
+    ProActionReplay,
+    GameGenie,
+  };
+
+  struct cheat_t {
+    bool enabled;
+    string code;
+    string desc;
+
+    unsigned count;
+    array<unsigned> addr;
+    array<uint8_t> data;
+
+    cheat_t& operator=(const cheat_t&);
+    bool operator<(const cheat_t&);
+  };
+
+  bool decode(const char *s, cheat_t &item) const;
+  bool read(unsigned addr, uint8_t &data) const;
+
+  bool enabled() const;
+  void enable();
+  void disable();
+
+  inline unsigned count() const { return code.size(); }
+  inline bool active() const { return cheat_enabled; }
+  inline bool exists(unsigned addr) const { return mask[addr >> 3] & 1 << (addr & 7); }
+
+  bool add(bool enable, const char *code, const char *desc);
+  bool edit(unsigned i, bool enable, const char *code, const char *desc);
+  bool remove(unsigned i);
+  bool get(unsigned i, cheat_t &item) const;
+
+  bool enabled(unsigned i) const;
+  void enable(unsigned i);
+  void disable(unsigned i);
+
+  void load(string data);
+  string save() const;
+  void clear();
+
+  Cheat();
+
+private:
+  bool cheat_enabled;  //cheat_enabled == (cheat_enabled_code_exists && cheat_system_enabled);
+  bool cheat_enabled_code_exists;
+  bool cheat_system_enabled;
+
+  uint8_t mask[0x200000];
+  vector<cheat_t> code;
+
+  bool decode(const char *str, unsigned &addr, uint8_t &data, type_t &type) const;
+  bool encode(string &str, unsigned addr, uint8_t data, type_t type) const;
+
+  void update_cheat_status();
+  unsigned mirror_address(unsigned addr) const;
+
+  void update(const cheat_t& item);
+  void set(unsigned addr);
+  void clear(unsigned addr);
+
+  string& encode_description(string &desc) const;
+  string& decode_description(string &desc) const;
+};
+
+extern Cheat cheat;

src/chip/bsx/bsx.cpp

@@ -1,6 +1,10 @@
-#include "../../base.h"
-#define BSX_CPP
+#include <../base.hpp>
+
+#define BSX_CPP
+namespace SNES {
 
 #include "bsx_base.cpp"
 #include "bsx_cart.cpp"
 #include "bsx_flash.cpp"
+};
+

src/chip/bsx/bsx.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 mmio_read(uint addr);
-  void mmio_write(uint addr, uint8 data);
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
 
 private:
   struct {
@@ -29,19 +29,13 @@ public:
   void power();
   void reset();
 
-  uint8 mmio_read(uint addr);
-  void mmio_write(uint addr, uint8 data);
-
-  MappedRAM sram;
-  MappedRAM psram;
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
 
   BSXCart();
   ~BSXCart();
 
 private:
-  uint8 *sram_data;  //256kbit SRAM
-  uint8 *psram_data; //  4mbit PSRAM
-
   struct {
     uint8 r[16];
   } regs;
@@ -56,13 +50,13 @@ public:
   void power();
   void reset();
 
-  uint size();
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  unsigned size() const;
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 
 private:
   struct {
-    uint command;
+    unsigned command;
     uint8 write_old;
     uint8 write_new;
 

src/chip/bsx/bsx_base.cpp

@@ -1,5 +1,7 @@
 #ifdef BSX_CPP
 
+BSXBase bsxbase;
+
 void BSXBase::init() {
 }
 
@@ -15,7 +17,7 @@ void BSXBase::reset() {
   memset(&regs, 0x00, sizeof regs);
 }
 
-uint8 BSXBase::mmio_read(uint addr) {
+uint8 BSXBase::mmio_read(unsigned addr) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -28,13 +30,13 @@ uint8 BSXBase::mmio_read(uint addr) {
     case 0x2190: return regs.r2190;
 
     case 0x2192: {
-    uint counter = regs.r2192_counter++;
+      unsigned counter = regs.r2192_counter++;
       if(regs.r2192_counter >= 18) regs.r2192_counter = 0;
 
       if(counter == 0) {
-      time_t rawtime;
+        time_t rawtime;
         time(&rawtime);
-      tm *t = localtime(&rawtime);
+        tm *t = localtime(&rawtime);
 
         regs.r2192_hour   = t->tm_hour;
         regs.r2192_minute = t->tm_min;
@@ -42,11 +44,11 @@ uint8 BSXBase::mmio_read(uint addr) {
       }
 
       switch(counter) {
-        case  0: return 0x00; //???
-        case  1: return 0x00; //???
-        case  2: return 0x00; //???
-        case  3: return 0x00; //???
-        case  4: return 0x00; //???
+        case  0: return 0x00;  //???
+        case  1: return 0x00;  //???
+        case  2: return 0x00;  //???
+        case  3: return 0x00;  //???
+        case  4: return 0x00;  //???
         case  5: return 0x01;
         case  6: return 0x01;
         case  7: return 0x00;
@@ -55,11 +57,11 @@ uint8 BSXBase::mmio_read(uint addr) {
         case 10: return regs.r2192_second;
         case 11: return regs.r2192_minute;
         case 12: return regs.r2192_hour;
-        case 13: return 0x00; //???
-        case 14: return 0x00; //???
-        case 15: return 0x00; //???
-        case 16: return 0x00; //???
-        case 17: return 0x00; //???
+        case 13: return 0x00;  //???
+        case 14: return 0x00;  //???
+        case 15: return 0x00;  //???
+        case 16: return 0x00;  //???
+        case 17: return 0x00;  //???
       }
     } break;
 
@@ -73,7 +75,7 @@ uint8 BSXBase::mmio_read(uint addr) {
   return cpu.regs.mdr;
 }
 
-void BSXBase::mmio_write(uint addr, uint8 data) {
+void BSXBase::mmio_write(unsigned addr, uint8 data) {
   addr &= 0xffff;
 
   switch(addr) {
@@ -134,4 +136,5 @@ void BSXBase::mmio_write(uint addr, uint8 data) {
   }
 }
 
-#endif //ifdef BSX_CPP
+#endif
+

src/chip/bsx/bsx_cart.cpp

@@ -1,5 +1,7 @@
 #ifdef BSX_CPP
 
+BSXCart bsxcart;
+
 void BSXCart::init() {
 }
 
@@ -12,7 +14,7 @@ void BSXCart::power() {
 }
 
 void BSXCart::reset() {
-  for(uint i = 0; i < 16; i++) regs.r[i] = 0x00;
+  for(unsigned i = 0; i < 16; i++) regs.r[i] = 0x00;
   regs.r[0x07] = 0x80;
   regs.r[0x08] = 0x80;
 
@@ -20,12 +22,14 @@ void BSXCart::reset() {
 }
 
 void BSXCart::update_memory_map() {
-  Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)psram;
+  Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)memory::bsxpram;
 
-  if((regs.r[0x02] & 0x80) == 0x00) { //LoROM mapping
+  if((regs.r[0x02] & 0x80) == 0x00) {
+    //LoROM mapping
     bus.map(Bus::MapLinear, 0x00, 0x7d, 0x8000, 0xffff, cart);
     bus.map(Bus::MapLinear, 0x80, 0xff, 0x8000, 0xffff, cart);
-  } else { //HiROM mapping
+  } else {
+    //HiROM mapping
     bus.map(Bus::MapShadow, 0x00, 0x3f, 0x8000, 0xffff, cart);
     bus.map(Bus::MapLinear, 0x40, 0x7d, 0x0000, 0xffff, cart);
     bus.map(Bus::MapShadow, 0x80, 0xbf, 0x8000, 0xffff, cart);
@@ -33,16 +37,16 @@ void BSXCart::update_memory_map() {
   }
 
   if(regs.r[0x03] & 0x80) {
-    bus.map(Bus::MapLinear, 0x60, 0x6f, 0x0000, 0xffff, psram);
-  //bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
+    bus.map(Bus::MapLinear, 0x60, 0x6f, 0x0000, 0xffff, memory::bsxpram);
+  //bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, memory::bsxpram);
   }
 
   if((regs.r[0x05] & 0x80) == 0x00) {
-    bus.map(Bus::MapLinear, 0x40, 0x4f, 0x0000, 0xffff, psram);
+    bus.map(Bus::MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::bsxpram);
   }
 
   if((regs.r[0x06] & 0x80) == 0x00) {
-    bus.map(Bus::MapLinear, 0x50, 0x5f, 0x0000, 0xffff, psram);
+    bus.map(Bus::MapLinear, 0x50, 0x5f, 0x0000, 0xffff, memory::bsxpram);
   }
 
   if(regs.r[0x07] & 0x80) {
@@ -53,47 +57,41 @@ void BSXCart::update_memory_map() {
     bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom);
   }
 
-  bus.map(Bus::MapShadow, 0x20, 0x3f, 0x6000, 0x7fff, psram);
-  bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
+  bus.map(Bus::MapShadow, 0x20, 0x3f, 0x6000, 0x7fff, memory::bsxpram);
+  bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, memory::bsxpram);
 }
 
-uint8 BSXCart::mmio_read(uint addr) {
-  if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
+uint8 BSXCart::mmio_read(unsigned addr) {
+  if((addr & 0xf0ffff) == 0x005000) {  //$[00-0f]:5000 MMIO
     uint8 n = (addr >> 16) & 15;
     return regs.r[n];
   }
 
-  if((addr & 0xf8f000) == 0x105000) { //$[10-17]:[5000-5fff] SRAM
-    return sram.read(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
+  if((addr & 0xf8f000) == 0x105000) {  //$[10-17]:[5000-5fff] SRAM
+    return memory::bsxram.read(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
   }
 
   return 0x00;
 }
 
-void BSXCart::mmio_write(uint addr, uint8 data) {
-  if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
+void BSXCart::mmio_write(unsigned addr, uint8 data) {
+  if((addr & 0xf0ffff) == 0x005000) {  //$[00-0f]:5000 MMIO
     uint8 n = (addr >> 16) & 15;
     regs.r[n] = data;
     if(n == 0x0e && data & 0x80) update_memory_map();
     return;
   }
 
-  if((addr & 0xf8f000) == 0x105000) { //$[10-17]:[5000-5fff] SRAM
-    return sram.write(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
+  if((addr & 0xf8f000) == 0x105000) {  //$[10-17]:[5000-5fff] SRAM
+    return memory::bsxram.write(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
   }
 }
 
 BSXCart::BSXCart() {
-  sram_data  = new uint8_t[ 32 * 1024];
-  psram_data = new uint8_t[512 * 1024];
-
-  sram.map (sram_data,   32 * 1024);
-  psram.map(psram_data, 512 * 1024);
 }
 
 BSXCart::~BSXCart() {
-  delete[] sram_data;
-  delete[] psram_data;
 }
 
-#endif //ifdef BSX_CPP
+#endif
+

src/chip/bsx/bsx_flash.cpp

@@ -1,5 +1,7 @@
 #ifdef BSX_CPP
 
+BSXFlash bsxflash;
+
 void BSXFlash::init() {}
 void BSXFlash::enable() {}
 
@@ -15,13 +17,14 @@ void BSXFlash::reset() {
   regs.flash_enable = false;
   regs.read_enable  = false;
   regs.write_enable = false;
+  memory::bsxflash.write_protect(!regs.write_enable);
 }
 
-uint BSXFlash::size() {
-  return memory::bscram.size();
+unsigned BSXFlash::size() const {
+  return memory::bsxflash.size();
 }
 
-uint8 BSXFlash::read(uint addr) {
+uint8 BSXFlash::read(unsigned addr) {
   if(addr == 0x0002) {
     if(regs.flash_enable) return 0x80;
   }
@@ -31,7 +34,7 @@ uint8 BSXFlash::read(uint addr) {
   }
 
   if(regs.read_enable && addr >= 0xff00 && addr <= 0xff13) {
-  //read flash cartridge vendor information
+    //read flash cartridge vendor information
     switch(addr - 0xff00) {
       case 0x00: return 0x4d;
       case 0x01: return 0x00;
@@ -39,24 +42,24 @@ uint8 BSXFlash::read(uint addr) {
       case 0x03: return 0x00;
       case 0x04: return 0x00;
       case 0x05: return 0x00;
-      case 0x06: return 0x2a; //0x2a = 8mbit, 0x2b = 16mbit (not known to exist, though BIOS recognizes ID)
+      case 0x06: return 0x2a;  //0x2a = 8mbit, 0x2b = 16mbit (not known to exist, though BIOS recognizes ID)
       case 0x07: return 0x00;
       default:   return 0x00;
     }
   }
 
-  return memory::bscram.read(addr);
+  return memory::bsxflash.read(addr);
 }
 
-void BSXFlash::write(uint addr, uint8 data) {
-//there exist both read-only and read-write BS-X flash cartridges ...
-//unfortunately, the vendor info is not stored inside memory dumps
-//of BS-X flashcarts, so it is impossible to determine whether a
-//given flashcart is writeable.
-//however, it has been observed that LoROM-mapped BS-X carts always
-//use read-write flashcarts, and HiROM-mapped BS-X carts always use
-//read-only flashcarts.
-//below is an unfortunately necessary workaround to this problem.
+void BSXFlash::write(unsigned addr, uint8 data) {
+  //there exist both read-only and read-write BS-X flash cartridges ...
+  //unfortunately, the vendor info is not stored inside memory dumps
+  //of BS-X flashcarts, so it is impossible to determine whether a
+  //given flashcart is writeable.
+  //however, it has been observed that LoROM-mapped BS-X carts always
+  //use read-write flashcarts, and HiROM-mapped BS-X carts always use
+  //read-only flashcarts.
+  //below is an unfortunately necessary workaround to this problem.
   if(cartridge.mapper() == Cartridge::BSCHiROM) return;
 
   if((addr & 0xff0000) == 0) {
@@ -64,11 +67,11 @@ void BSXFlash::write(uint addr, uint8 data) {
     regs.write_new = data;
 
     if(regs.write_enable && regs.write_old == regs.write_new) {
-      return memory::bscram.write(addr, data);
+      return memory::bsxflash.write(addr, data);
     }
   } else {
     if(regs.write_enable) {
-      return memory::bscram.write(addr, data);
+      return memory::bsxflash.write(addr, data);
     }
   }
 
@@ -107,7 +110,10 @@ void BSXFlash::write(uint addr, uint8 data) {
       regs.read_enable  = false;
       regs.write_enable = false;
     }
+
+    memory::bsxflash.write_protect(!regs.write_enable);
   }
 }
 
-#endif //ifdef BSX_CPP
+#endif
+

src/chip/chip.h

@@ -1,10 +0,0 @@
-#include "bsx/bsx.h"
-#include "srtc/srtc.h"
-#include "sdd1/sdd1.h"
-#include "cx4/cx4.h"
-#include "dsp1/dsp1.h"
-#include "dsp2/dsp2.h"
-#include "dsp3/dsp3.h"
-#include "dsp4/dsp4.h"
-#include "obc1/obc1.h"
-#include "st010/st010.h"

src/chip/chip.hpp

@@ -0,0 +1,13 @@
+#include "sgb/sgb.hpp"
+#include "sa1/sa1.hpp"
+#include "bsx/bsx.hpp"
+#include "srtc/srtc.hpp"
+#include "sdd1/sdd1.hpp"
+#include "spc7110/spc7110.hpp"
+#include "cx4/cx4.hpp"
+#include "dsp1/dsp1.hpp"
+#include "dsp2/dsp2.hpp"
+#include "dsp3/dsp3.hpp"
+#include "dsp4/dsp4.hpp"
+#include "obc1/obc1.hpp"
+#include "st010/st010.hpp"

src/chip/cx4/cx4.cpp

@@ -5,8 +5,12 @@
   Portions (c) anomie, Overload, zsKnight, Nach, byuu
 */
 
-#include "../../base.h"
-#define CX4_CPP
+#include <../base.hpp>
+
+#define CX4_CPP
+namespace SNES {
+
+Cx4 cx4;
 
 #include "cx4data.cpp"
 #include "cx4fn.cpp"
@@ -29,8 +33,8 @@ uint16 addr = 0x0080 + (r * 3);
 }
 
 void Cx4::mul(uint32 x, uint32 y, uint32 &rl, uint32 &rh) {
-int64 rx = x & 0xffffff;
-int64 ry = y & 0xffffff;
+int64_t rx = x & 0xffffff;
+int64_t ry = y & 0xffffff;
   if(rx & 0x800000)rx |= ~0x7fffff;
   if(ry & 0x800000)ry |= ~0x7fffff;
 
@@ -78,7 +82,7 @@ uint16 dest, count;
   }
 }
 
-void Cx4::write(uint addr, uint8 data) {
+void Cx4::write(unsigned addr, uint8 data) {
   addr &= 0x1fff;
 
   if(addr < 0x0c00) {
@@ -160,7 +164,7 @@ void Cx4::writel(uint16 addr, uint32 data) {
   write(addr + 2, data >> 16);
 }
 
-uint8 Cx4::read(uint addr) {
+uint8 Cx4::read(unsigned addr) {
   addr &= 0x1fff;
 
   if(addr < 0x0c00) {
@@ -194,3 +198,5 @@ void Cx4::reset() {
   memset(ram, 0, 0x0c00);
   memset(reg, 0, 0x0100);
 }
+};
+

src/chip/cx4/cx4.hpp

@@ -90,8 +90,8 @@ public:
   void   power();
   void   reset();
 
-  uint8  read (uint addr);
-  void   write(uint addr, uint8 data);
+  uint8  read (unsigned addr);
+  void   write(unsigned addr, uint8 data);
 };
 
 extern Cx4 cx4;

src/chip/cx4/cx4data.cpp

@@ -184,4 +184,4 @@ const int16 Cx4::CosTable[512] = {
    32610,  32647,  32679,  32706,  32728,  32745,  32758,  32765
 };
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/cx4fn.cpp

@@ -243,4 +243,4 @@ uint8 bit    = 0x80;
   }
 }
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/cx4oam.cpp

@@ -220,4 +220,4 @@ uint16 mask2   = 0x3f3f;
   }
 }
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/cx4/cx4ops.cpp

@@ -223,4 +223,4 @@ void Cx4::op89() {
   str(1, 0xffffff);
 }
 
-#endif //ifdef CX4_CPP
+#endif

src/chip/dsp1/dsp1.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
-#define DSP1_CPP
+#include <../base.hpp>
+
+#define DSP1_CPP
+namespace SNES {
+
+DSP1 dsp1;
 
 #include "dsp1emu.cpp"
 
@@ -26,7 +30,7 @@ void DSP1::reset() {
  * of expected ranges
  *****/
 bool DSP1::addr_decode(uint16 addr) {
-  switch(cartridge.info.dsp1_mapper) {
+  switch(cartridge.dsp1_mapper()) {
     case Cartridge::DSP1LoROM1MB: {
     //$[20-3f]:[8000-bfff] = DR, $[20-3f]:[c000-ffff] = SR
       return (addr >= 0xc000);
@@ -46,12 +50,14 @@ bool DSP1::addr_decode(uint16 addr) {
   return 0;
 }
 
-uint8 DSP1::read(uint addr) {
+uint8 DSP1::read(unsigned addr) {
   return (addr_decode(addr) == 0) ? dsp1.getDr() : dsp1.getSr();
 }
 
-void DSP1::write(uint addr, uint8 data) {
+void DSP1::write(unsigned addr, uint8 data) {
   if(addr_decode(addr) == 0) {
     dsp1.setDr(data);
   }
 }
+};
+

src/chip/dsp1/dsp1.hpp

@@ -1,4 +1,4 @@
-#include "dsp1emu.h"
+#include "dsp1emu.hpp"
 
 class DSP1 : public Memory {
 private:
@@ -11,8 +11,8 @@ public:
   void power();
   void reset();
 
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 };
 
 extern DSP1 dsp1;

src/chip/dsp1/dsp1emu.cpp

@@ -1622,4 +1622,4 @@ const int16 Dsp1::SinTable[256] = {
 
 //////////////////////////////////////////////////////////////////
 
-#endif //ifdef DSP1_CPP
+#endif

src/chip/dsp2/dsp2.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
-#define DSP2_CPP
+#include <../base.hpp>
+
+#define DSP2_CPP
+namespace SNES {
+
+DSP2 dsp2;
 
 #include "dsp2_op.cpp"
 
@@ -29,8 +33,8 @@ void DSP2::reset() {
   status.op0dinlen       = 0;
 }
 
-uint8 DSP2::read(uint addr) {
-uint8 r = 0xff;
+uint8 DSP2::read(unsigned addr) {
+  uint8 r = 0xff;
   if(status.out_count) {
     r = status.output[status.out_index++];
     status.out_index &= 511;
@@ -41,7 +45,7 @@ uint8 r = 0xff;
   return r;
 }
 
-void DSP2::write(uint addr, uint8 data) {
+void DSP2::write(unsigned addr, uint8 data) {
   if(status.waiting_for_command) {
     status.command  = data;
     status.in_index = 0;
@@ -133,3 +137,5 @@ void DSP2::write(uint addr, uint8 data) {
 
 DSP2::DSP2() {}
 DSP2::~DSP2() {}
+};
+

src/chip/dsp2/dsp2.hpp

@@ -1,10 +1,10 @@
 class DSP2 : public Memory {
 public:
   struct {
-    bool   waiting_for_command;
-    uint   command;
-    uint   in_count,  in_index;
-    uint   out_count, out_index;
+    bool waiting_for_command;
+    unsigned command;
+    unsigned in_count,  in_index;
+    unsigned out_count, out_index;
 
     uint8  parameters[512];
     uint8  output[512];
@@ -26,8 +26,8 @@ public:
   void power();
   void reset();
 
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 
   DSP2();
   ~DSP2();

src/chip/dsp2/dsp2_op.cpp

@@ -174,4 +174,4 @@ uint8  pixelarray[512];
   }
 }
 
-#endif //ifdef DSP2_CPP
+#endif

src/chip/dsp3/dsp3.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
-#define DSP3_CPP
+#include <../base.hpp>
+
+#define DSP3_CPP
+namespace SNES {
+
+DSP3 dsp3;
 
 namespace DSP3i {
   #define bool8 uint8
@@ -21,14 +25,16 @@ void DSP3::reset() {
   DSP3i::DSP3_Reset();
 }
 
-uint8 DSP3::read(uint addr) {
+uint8 DSP3::read(unsigned addr) {
   DSP3i::dsp3_address = addr & 0xffff;
   DSP3i::DSP3GetByte();
   return DSP3i::dsp3_byte;
 }
 
-void DSP3::write(uint addr, uint8 data) {
+void DSP3::write(unsigned addr, uint8 data) {
   DSP3i::dsp3_address = addr & 0xffff;
   DSP3i::dsp3_byte = data;
   DSP3i::DSP3SetByte();
 }
+};
+

src/chip/dsp3/dsp3.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
 };
 
 extern DSP3 dsp3;

src/chip/dsp3/dsp3emu.c

@@ -1143,4 +1143,4 @@ void InitDSP3()
   DSP3_Reset();
 }
 
-#endif //ifdef DSP3_CPP
+#endif

src/chip/dsp4/dsp4.cpp

@@ -1,5 +1,9 @@
-#include "../../base.h"
-#define DSP4_CPP
+#include <../base.hpp>
+
+#define DSP4_CPP
+namespace SNES {
+
+DSP4 dsp4;
 
 namespace DSP4i {
   inline uint16 READ_WORD(uint8 *addr) {
@@ -34,7 +38,7 @@ void DSP4::reset() {
   DSP4i::InitDSP4();
 }
 
-uint8 DSP4::read(uint addr) {
+uint8 DSP4::read(unsigned addr) {
   addr &= 0xffff;
   if(addr < 0xc000) {
     DSP4i::dsp4_address = addr;
@@ -44,7 +48,7 @@ uint8 DSP4::read(uint addr) {
   return 0x80;
 }
 
-void DSP4::write(uint addr, uint8 data) {
+void DSP4::write(unsigned addr, uint8 data) {
   addr &= 0xffff;
   if(addr < 0xc000) {
     DSP4i::dsp4_address = addr;
@@ -52,3 +56,5 @@ void DSP4::write(uint addr, uint8 data) {
     DSP4i::DSP4SetByte();
   }
 }
+};
+

src/chip/dsp4/dsp4.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
 };
 
 extern DSP4 dsp4;

src/chip/dsp4/dsp4emu.c

@@ -2147,4 +2147,4 @@ void DSP4GetByte()
   }
 }
 
-#endif //ifdef DSP4_CPP
+#endif

src/chip/obc1/obc1.cpp

@@ -1,4 +1,9 @@
-#include "../../base.h"
+#include <../base.hpp>
+
+#define OBC1_CPP
+namespace SNES {
+
+OBC1 obc1;
 
 void OBC1::init() {}
 void OBC1::enable() {}
@@ -8,82 +13,66 @@ void OBC1::power() {
 }
 
 void OBC1::reset() {
-  for(uint i = 0x0000; i <= 0x1fff; i++) ram_write(i, 0xff);
+  for(unsigned i = 0x0000; i <= 0x1fff; i++) ram_write(i, 0xff);
 
   status.baseptr = (ram_read(0x1ff5) & 1) ? 0x1800 : 0x1c00;
   status.address = (ram_read(0x1ff6) & 0x7f);
   status.shift   = (ram_read(0x1ff6) & 3) << 1;
 }
 
-uint8 OBC1::read(uint addr) {
+uint8 OBC1::read(unsigned addr) {
   addr &= 0x1fff;
   if((addr & 0x1ff8) != 0x1ff0) return ram_read(addr);
 
-  switch(addr) {
-  case 0x1ff0:
-    return ram_read(status.baseptr + (status.address << 2) + 0);
-  case 0x1ff1:
-    return ram_read(status.baseptr + (status.address << 2) + 1);
-  case 0x1ff2:
-    return ram_read(status.baseptr + (status.address << 2) + 2);
-  case 0x1ff3:
-    return ram_read(status.baseptr + (status.address << 2) + 3);
-  case 0x1ff4:
-    return ram_read(status.baseptr + (status.address >> 2) + 0x200);
-  case 0x1ff5:
-  case 0x1ff6:
-  case 0x1ff7:
-    return ram_read(addr);
+  switch(addr) { default:  //never used, avoids compiler warning
+    case 0x1ff0: return ram_read(status.baseptr + (status.address << 2) + 0);
+    case 0x1ff1: return ram_read(status.baseptr + (status.address << 2) + 1);
+    case 0x1ff2: return ram_read(status.baseptr + (status.address << 2) + 2);
+    case 0x1ff3: return ram_read(status.baseptr + (status.address << 2) + 3);
+    case 0x1ff4: return ram_read(status.baseptr + (status.address >> 2) + 0x200);
+    case 0x1ff5: case 0x1ff6: case 0x1ff7: return ram_read(addr);
   }
-
-  return 0x00; //never used, avoids compiler warning
 }
 
-void OBC1::write(uint addr, uint8 data) {
+void OBC1::write(unsigned addr, uint8 data) {
   addr &= 0x1fff;
   if((addr & 0x1ff8) != 0x1ff0) return ram_write(addr, data);
 
   switch(addr) {
-  case 0x1ff0:
-    ram_write(status.baseptr + (status.address << 2) + 0, data);
-    break;
-  case 0x1ff1:
-    ram_write(status.baseptr + (status.address << 2) + 1, data);
-    break;
-  case 0x1ff2:
-    ram_write(status.baseptr + (status.address << 2) + 2, data);
-    break;
-  case 0x1ff3:
-    ram_write(status.baseptr + (status.address << 2) + 3, data);
-    break;
-  case 0x1ff4: {
-  uint8 temp;
-    temp = ram_read(status.baseptr + (status.address >> 2) + 0x200);
-    temp = (temp & ~(3 << status.shift)) | ((data & 3) << status.shift);
-    ram_write(status.baseptr + (status.address >> 2) + 0x200, temp);
-  } break;
-  case 0x1ff5:
-    status.baseptr = (data & 1) ? 0x1800 : 0x1c00;
-    ram_write(addr, data);
-    break;
-  case 0x1ff6:
-    status.address = (data & 0x7f);
-    status.shift   = (data & 3) << 1;
-    ram_write(addr, data);
-    break;
-  case 0x1ff7:
-    ram_write(addr, data);
-    break;
+    case 0x1ff0: ram_write(status.baseptr + (status.address << 2) + 0, data); break;
+    case 0x1ff1: ram_write(status.baseptr + (status.address << 2) + 1, data); break;
+    case 0x1ff2: ram_write(status.baseptr + (status.address << 2) + 2, data); break;
+    case 0x1ff3: ram_write(status.baseptr + (status.address << 2) + 3, data); break;
+    case 0x1ff4: {
+      uint8 temp = ram_read(status.baseptr + (status.address >> 2) + 0x200);
+      temp = (temp & ~(3 << status.shift)) | ((data & 3) << status.shift);
+      ram_write(status.baseptr + (status.address >> 2) + 0x200, temp);
+    } break;
+    case 0x1ff5: {
+      status.baseptr = (data & 1) ? 0x1800 : 0x1c00;
+      ram_write(addr, data);
+    } break;
+    case 0x1ff6: {
+      status.address = (data & 0x7f);
+      status.shift   = (data & 3) << 1;
+      ram_write(addr, data);
+    } break;
+    case 0x1ff7: {
+      ram_write(addr, data);
+    } break;
   }
 }
 
-uint8 OBC1::ram_read(uint addr) {
+uint8 OBC1::ram_read(unsigned addr) {
   return memory::cartram.read(addr & 0x1fff);
 }
 
-void OBC1::ram_write(uint addr, uint8 data) {
+void OBC1::ram_write(unsigned addr, uint8 data) {
   memory::cartram.write(addr & 0x1fff, data);
 }
 
 OBC1::OBC1() {}
-OBC1::~OBC1() {}
+OBC1::~OBC1() {}
+
+};
+

src/chip/obc1/obc1.hpp

@@ -5,15 +5,15 @@ public:
   void power();
   void reset();
 
-  uint8 read(uint addr);
-  void write(uint addr, uint8 data);
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
 
   OBC1();
   ~OBC1();
 
 private:
-  uint8 ram_read(uint addr);
-  void ram_write(uint addr, uint8 data);
+  uint8 ram_read(unsigned addr);
+  void ram_write(unsigned addr, uint8 data);
 
   struct {
     uint16 address;

src/chip/sa1/bus/bus.cpp

@@ -0,0 +1,164 @@
+#ifdef SA1_CPP
+
+SA1Bus sa1bus;
+
+namespace memory {
+  VectorSelectionPage vectorsp;
+  StaticRAM iram(2048);
+  MappedRAM &bwram = memory::cartram;
+  CC1BWRAM cc1bwram;
+  BitmapRAM bitmapram;
+}
+
+void SA1Bus::init() {
+  for(uint32_t i = 0x0000; i <= 0xffff; i++) {
+    map(i << 8, memory::memory_unmapped, 0);
+  }
+
+  for(uint16_t i = 0x2200; i <= 0x23ff; i++) {
+    memory::mmio.map(i, sa1);
+  }
+
+  map(MapLinear, 0x00, 0x3f, 0x0000, 0x07ff, memory::iram);
+  map(MapDirect, 0x00, 0x3f, 0x2200, 0x23ff, memory::mmio);
+  map(MapLinear, 0x00, 0x3f, 0x3000, 0x37ff, memory::iram);
+  map(MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::bwram);
+  map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::cartrom);
+  map(MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::bwram);
+  map(MapLinear, 0x60, 0x6f, 0x0000, 0xffff, memory::bitmapram);
+  map(MapLinear, 0x80, 0xbf, 0x0000, 0x07ff, memory::iram);
+  map(MapDirect, 0x80, 0xbf, 0x2200, 0x23ff, memory::mmio);
+  map(MapLinear, 0x80, 0xbf, 0x3000, 0x37ff, memory::iram);
+  map(MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::bwram);
+  map(MapLinear, 0x80, 0xbf, 0x8000, 0xffff, memory::cartrom);
+  map(MapLinear, 0xc0, 0xff, 0x0000, 0xffff, memory::cartrom);
+
+  bus.map(MapLinear, 0x00, 0x3f, 0x3000, 0x37ff, memory::iram);
+  bus.map(MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::cc1bwram);
+  bus.map(MapLinear, 0x00, 0x3f, 0x8000, 0xffff, memory::cartrom);
+  bus.map(MapLinear, 0x40, 0x4f, 0x0000, 0xffff, memory::cc1bwram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x3000, 0x37ff, memory::iram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::cc1bwram);
+  bus.map(MapLinear, 0x80, 0xbf, 0x8000, 0xffff, memory::cartrom);
+  bus.map(MapLinear, 0xc0, 0xff, 0x0000, 0xffff, memory::cartrom);
+
+  memory::vectorsp.sync();
+}
+
+//===================
+//VectorSelectionPage
+//===================
+
+//this class maps $00:[ff00-ffff] for the purpose of supporting:
+//$2209.d6 IVSW (S-CPU IRQ vector selection) (0 = cart, 1 = SA-1)
+//$2209.d4 NVSW (S-CPU NMI vector selection) (0 = cart, 1 = SA-1)
+//when set, vector addresses are over-ridden with SA-1 register settings:
+//SIV = S-CPU IRQ vector address override
+//SNV = S-CPU NMI vector address override
+//
+//$00:[ffea-ffeb|ffee-ffef] are special cased on read;
+//all other addresses return original mapped data.
+
+uint8_t VectorSelectionPage::read(unsigned addr) {
+  switch(0xff00 | (addr & 0xff)) {
+    case 0xffea: case 0xffeb: {
+      if(sa1.mmio.cpu_nvsw == true) return (sa1.mmio.snv >> ((addr & 1) << 3));
+    } break;
+
+    case 0xffee: case 0xffef: {
+      if(sa1.mmio.cpu_ivsw == true) return (sa1.mmio.siv >> ((addr & 1) << 3));
+    } break;
+  }
+
+  return access->read(addr);
+}
+
+void VectorSelectionPage::write(unsigned addr, uint8_t data) {
+  return access->write(addr, data);
+}
+
+//call this whenever bus is remapped.
+//note: S-CPU and SA-1 bus always share $00:[ff00-ffff] as cartridge ROM data;
+//the SA-1 MMC does not allow mapping these independently between processors.
+//this allows this class to be shared for both, caching only ones' access class.
+void VectorSelectionPage::sync() {
+  if(bus.page[0x00ff00 >> 8].access != this) {
+    //bus was re-mapped, hook access routine
+    access = bus.page[0x00ff00 >> 8].access;
+       bus.page[0x00ff00 >> 8].access = this;
+    sa1bus.page[0x00ff00 >> 8].access = this;
+  }
+}
+
+//========
+//CC1BWRAM
+//========
+
+unsigned CC1BWRAM::size() const {
+  return memory::cartram.size();
+}
+
+uint8_t CC1BWRAM::read(unsigned addr) {
+  if(dma) return sa1.dma_cc1_read(addr);
+  return memory::cartram.read(addr);
+}
+
+void CC1BWRAM::write(unsigned addr, uint8_t data) {
+  memory::cartram.write(addr, data);
+}
+
+//=========
+//BitmapRAM
+//=========
+
+unsigned BitmapRAM::size() const {
+  return 0x100000;
+}
+
+uint8_t BitmapRAM::read(unsigned addr) {
+  if(sa1.mmio.bbf == 0) {
+    //4bpp
+    unsigned shift = addr & 1;
+    addr = (addr >> 1) & (memory::cartram.size() - 1);
+    switch(shift) {
+      case 0: return (memory::cartram.read(addr) >> 0) & 15;
+      case 1: return (memory::cartram.read(addr) >> 4) & 15;
+    }
+  } else {
+    //2bpp
+    unsigned shift = addr & 3;
+    addr = (addr >> 2) & (memory::cartram.size() - 1);
+    switch(shift) {
+      case 0: return (memory::cartram.read(addr) >> 0) & 3;
+      case 1: return (memory::cartram.read(addr) >> 2) & 3;
+      case 2: return (memory::cartram.read(addr) >> 4) & 3;
+      case 3: return (memory::cartram.read(addr) >> 6) & 3;
+    }
+  }
+}
+
+void BitmapRAM::write(unsigned addr, uint8_t data) {
+  if(sa1.mmio.bbf == 0) {
+    //4bpp
+    uint8_t shift = addr & 1;
+    addr = (addr >> 1) & (memory::cartram.size() - 1);
+    switch(shift) {
+      case 0: data = (memory::cartram.read(addr) & 0xf0) | ((data & 15) << 0); break;
+      case 1: data = (memory::cartram.read(addr) & 0x0f) | ((data & 15) << 4); break;
+    }
+  } else {
+    //2bpp
+    uint8_t shift = addr & 3;
+    addr = (addr >> 2) & (memory::cartram.size() - 1);
+    switch(shift) {
+      case 0: data = (memory::cartram.read(addr) & 0xfc) | ((data &  3) << 0); break;
+      case 1: data = (memory::cartram.read(addr) & 0xf3) | ((data &  3) << 2); break;
+      case 2: data = (memory::cartram.read(addr) & 0xcf) | ((data &  3) << 4); break;
+      case 3: data = (memory::cartram.read(addr) & 0x3f) | ((data &  3) << 6); break;
+    }
+  }
+
+  memory::cartram.write(addr, data);
+}
+
+#endif

src/chip/sa1/bus/bus.hpp

@@ -0,0 +1,31 @@
+struct SA1Bus : Bus {
+  void init();
+};
+
+struct VectorSelectionPage : Memory {
+  alwaysinline uint8_t read(unsigned);
+  alwaysinline void write(unsigned, uint8_t);
+  void sync();
+  Memory *access;
+};
+
+struct CC1BWRAM : Memory {
+  unsigned size() const;
+  alwaysinline uint8_t read(unsigned);
+  alwaysinline void write(unsigned, uint8_t);
+  bool dma;
+};
+
+struct BitmapRAM : Memory {
+  unsigned size() const;
+  alwaysinline uint8_t read(unsigned);
+  alwaysinline void write(unsigned, uint8_t);
+};
+
+namespace memory {
+  extern VectorSelectionPage vectorsp;
+  extern StaticRAM iram;
+  extern MappedRAM &bwram;
+  extern CC1BWRAM cc1bwram;
+  extern BitmapRAM bitmapram;
+}

src/chip/sa1/dma/dma.cpp

@@ -0,0 +1,139 @@
+#ifdef SA1_CPP
+
+//====================
+//direct data transfer
+//====================
+
+void SA1::dma_normal() {
+  while(mmio.dtc--) {
+    uint8_t data = regs.mdr;
+    uint32_t dsa = mmio.dsa++;
+    uint32_t dda = mmio.dda++;
+
+    //source and destination cannot be the same
+    if(mmio.sd == DMA::SourceBWRAM && mmio.dd == DMA::DestBWRAM) continue;
+    if(mmio.sd == DMA::SourceIRAM  && mmio.dd == DMA::DestIRAM ) continue;
+
+    switch(mmio.sd) {
+      case DMA::SourceROM: {
+        if((dsa & 0x408000) == 0x008000 || (dsa & 0xc00000) == 0xc00000) {
+          data = sa1bus.read(dsa);
+        }
+      } break;
+
+      case DMA::SourceBWRAM: {
+        if((dsa & 0x40e000) == 0x006000 || (dsa & 0xf00000) == 0x400000) {
+          data = sa1bus.read(dsa);
+        }
+      } break;
+
+      case DMA::SourceIRAM: {
+        data = memory::iram.read(dsa & 0x07ff);
+      } break;
+    }
+
+    switch(mmio.dd) {
+      case DMA::DestBWRAM: {
+        if((dda & 0x40e000) == 0x006000 || (dda & 0xf00000) == 0x400000) {
+          sa1bus.write(dda, data);
+        }
+      } break;
+
+      case DMA::DestIRAM: {
+        memory::iram.write(dda & 0x07ff, data);
+      } break;
+    }
+  }
+
+  mmio.dma_irqfl = true;
+  if(mmio.dma_irqen) mmio.dma_irqcl = 0;
+}
+
+//((byte & 6) << 3) + (byte & 1) explanation:
+//transforms a byte index (0-7) into a planar index:
+//result[] = {  0,  1, 16, 17, 32, 33, 48, 49 };
+//works for 2bpp, 4bpp and 8bpp modes
+
+//===========================
+//type-1 character conversion
+//===========================
+
+void SA1::dma_cc1() {
+  memory::cc1bwram.dma = true;
+  mmio.chdma_irqfl = true;
+  if(mmio.chdma_irqen) {
+    mmio.chdma_irqcl = 0;
+    cpu.regs.irq = 1;
+  }
+}
+
+uint8_t SA1::dma_cc1_read(unsigned addr) {
+  //16 bytes/char (2bpp); 32 bytes/char (4bpp); 64 bytes/char (8bpp)
+  unsigned charmask = (1 << (6 - mmio.dmacb)) - 1;
+
+  if((addr & charmask) == 0) {
+    //buffer next character to I-RAM
+    unsigned bpp = 2 << (2 - mmio.dmacb);
+    unsigned bpl = (8 << mmio.dmasize) >> mmio.dmacb;
+    unsigned bwmask = memory::bwram.size() - 1;
+    unsigned tile = ((addr - mmio.dsa) & bwmask) >> (6 - mmio.dmacb);
+    unsigned ty = (tile >> mmio.dmasize);
+    unsigned tx = tile & ((1 << mmio.dmasize) - 1);
+    unsigned bwaddr = mmio.dsa + ty * 8 * bpl + tx * bpp;
+
+    for(unsigned y = 0; y < 8; y++) {
+      uint64_t data = 0;
+      for(unsigned byte = 0; byte < bpp; byte++) {
+        data |= (uint64_t)memory::bwram.read((bwaddr + byte) & bwmask) << (byte << 3);
+      }
+      bwaddr += bpl;
+
+      uint8_t out[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+      for(unsigned x = 0; x < 8; x++) {
+        out[0] |= (data & 1) << (7 - x); data >>= 1;
+        out[1] |= (data & 1) << (7 - x); data >>= 1;
+        if(mmio.dmacb == 2) continue;
+        out[2] |= (data & 1) << (7 - x); data >>= 1;
+        out[3] |= (data & 1) << (7 - x); data >>= 1;
+        if(mmio.dmacb == 1) continue;
+        out[4] |= (data & 1) << (7 - x); data >>= 1;
+        out[5] |= (data & 1) << (7 - x); data >>= 1;
+        out[6] |= (data & 1) << (7 - x); data >>= 1;
+        out[7] |= (data & 1) << (7 - x); data >>= 1;
+      }
+
+      for(unsigned byte = 0; byte < bpp; byte++) {
+        unsigned p = mmio.dda + (y << 1) + ((byte & 6) << 3) + (byte & 1);
+        memory::iram.write(p & 0x07ff, out[byte]);
+      }
+    }
+  }
+
+  return memory::iram.read((mmio.dda + (addr & charmask)) & 0x07ff);
+}
+
+//===========================
+//type-2 character conversion
+//===========================
+
+void SA1::dma_cc2() {
+  //select register file index (0-7 or 8-15)
+  const uint8_t *brf = &mmio.brf[(dma.line & 1) << 3];
+  unsigned bpp = 2 << (2 - mmio.dmacb);
+  unsigned addr = mmio.dda & 0x07ff;
+  addr &= ~((1 << (7 - mmio.dmacb)) - 1);
+  addr += (dma.line & 8) * bpp;
+  addr += (dma.line & 7) * 2;
+
+  for(unsigned byte = 0; byte < bpp; byte++) {
+    uint8_t output = 0;
+    for(unsigned bit = 0; bit < 8; bit++) {
+      output |= ((brf[bit] >> byte) & 1) << (7 - bit);
+    }
+    memory::iram.write(addr + ((byte & 6) << 3) + (byte & 1), output);
+  }
+
+  dma.line = (dma.line + 1) & 15;
+}
+
+#endif

src/chip/sa1/dma/dma.hpp

@@ -0,0 +1,11 @@
+struct DMA {
+  enum CDEN { DmaNormal = 0, DmaCharConversion = 1 };
+  enum SD { SourceROM = 0, SourceBWRAM = 1, SourceIRAM = 2 };
+  enum DD { DestIRAM = 0, DestBWRAM = 1 };
+  unsigned line;
+} dma;
+
+void dma_normal();
+void dma_cc1();
+uint8_t dma_cc1_read(unsigned addr);
+void dma_cc2();

src/chip/sa1/memory/memory.cpp

@@ -0,0 +1,39 @@
+#ifdef SA1_CPP
+
+//==========================
+//SA-1 opcode core functions
+//==========================
+
+void SA1::op_io() {
+  tick();
+  if(regs.wai) scheduler.sync_copcpu();
+}
+
+//ROM, I-RAM and MMIO registers are accessed at ~10.74MHz (2 clock ticks)
+//BW-RAM is accessed at ~5.37MHz (4 clock ticks)
+//tick() == 2 clock ticks
+//note: bus conflict delays are not emulated at this time
+
+#define is_bwram(addr) (\
+   ((addr & 0x40e000) == 0x006000) \
+|| ((addr & 0xf00000) == 0x400000) \
+|| ((addr & 0xf00000) == 0x600000) \
+)
+
+uint8_t SA1::op_read(unsigned addr) {
+  tick();
+  if(is_bwram(addr)) tick();
+  scheduler.sync_copcpu();
+  return sa1bus.read(addr);
+}
+
+void SA1::op_write(unsigned addr, uint8_t data) {
+  tick();
+  if(is_bwram(addr)) tick();
+  scheduler.sync_copcpu();
+  sa1bus.write(addr, data);
+}
+
+#undef is_bwram
+
+#endif

src/chip/sa1/memory/memory.hpp

@@ -0,0 +1,4 @@
+alwaysinline void op_io();
+alwaysinline uint8_t op_read(unsigned addr);
+alwaysinline void op_write(unsigned addr, uint8_t data);
+alwaysinline unsigned bus_speed(unsigned addr);

src/chip/sa1/mmio/mmio.cpp

@@ -0,0 +1,631 @@
+#ifdef SA1_CPP
+
+//BS-X flash carts, when present, are mapped to 0x400000+
+Memory& SA1::mmio_access(unsigned &addr) {
+  if(!memory::bsxflash.data()) return memory::cartrom;
+  if(addr < 0x400000) return memory::cartrom;
+  addr &= 0x3fffff;
+  return bsxflash;
+}
+
+//(CCNT) SA-1 control
+void SA1::mmio_w2200(uint8_t data) {
+  if(mmio.sa1_resb && !(data & 0x80)) {
+    //reset SA-1 CPU
+    regs.pc.w = mmio.crv;
+    regs.pc.b = 0x00;
+  }
+
+  mmio.sa1_irq  = (data & 0x80);
+  mmio.sa1_rdyb = (data & 0x40);
+  mmio.sa1_resb = (data & 0x20);
+  mmio.sa1_nmi  = (data & 0x10);
+  mmio.smeg     = (data & 0x0f);
+
+  if(mmio.sa1_irq) {
+    mmio.sa1_irqfl = true;
+    if(mmio.sa1_irqen) mmio.sa1_irqcl = 0;
+  }
+
+  if(mmio.sa1_nmi) {
+    mmio.sa1_nmifl = true;
+    if(mmio.sa1_nmien) mmio.sa1_nmicl = 0;
+  }
+}
+
+//(SIE) S-CPU interrupt enable
+void SA1::mmio_w2201(uint8_t data) {
+  if(!mmio.cpu_irqen && (data & 0x80)) {
+    if(mmio.cpu_irqfl) {
+      mmio.cpu_irqcl = 0;
+      cpu.regs.irq = 1;
+    }
+  }
+
+  if(!mmio.chdma_irqen && (data & 0x20)) {
+    if(mmio.chdma_irqfl) {
+      mmio.chdma_irqcl = 0;
+      cpu.regs.irq = 1;
+    }
+  }
+
+  mmio.cpu_irqen   = (data & 0x80);
+  mmio.chdma_irqen = (data & 0x20);
+}
+
+//(SIC) S-CPU interrupt clear
+void SA1::mmio_w2202(uint8_t data) {
+  mmio.cpu_irqcl   = (data & 0x80);
+  mmio.chdma_irqcl = (data & 0x20);
+
+  if(mmio.cpu_irqcl  ) mmio.cpu_irqfl   = false;
+  if(mmio.chdma_irqcl) mmio.chdma_irqfl = false;
+
+  if(!mmio.cpu_irqfl && !mmio.chdma_irqfl) cpu.regs.irq = 0;
+}
+
+//(CRV) SA-1 reset vector
+void SA1::mmio_w2203(uint8_t data) { mmio.crv = (mmio.crv & 0xff00) | data; }
+void SA1::mmio_w2204(uint8_t data) { mmio.crv = (data << 8) | (mmio.crv & 0xff); }
+
+//(CNV) SA-1 NMI vector
+void SA1::mmio_w2205(uint8_t data) { mmio.cnv = (mmio.cnv & 0xff00) | data; }
+void SA1::mmio_w2206(uint8_t data) { mmio.cnv = (data << 8) | (mmio.cnv & 0xff); }
+
+//(CIV) SA-1 IRQ vector
+void SA1::mmio_w2207(uint8_t data) { mmio.civ = (mmio.civ & 0xff00) | data; }
+void SA1::mmio_w2208(uint8_t data) { mmio.civ = (data << 8) | (mmio.civ & 0xff); }
+
+//(SCNT) S-CPU control
+void SA1::mmio_w2209(uint8_t data) {
+  mmio.cpu_irq  = (data & 0x80);
+  mmio.cpu_ivsw = (data & 0x40);
+  mmio.cpu_nvsw = (data & 0x10);
+  mmio.cmeg     = (data & 0x0f);
+
+  if(mmio.cpu_irq) {
+    mmio.cpu_irqfl = true;
+    if(mmio.cpu_irqen) {
+      mmio.cpu_irqcl = 0;
+      cpu.regs.irq = 1;
+    }
+  }
+}
+
+//(CIE) SA-1 interrupt enable
+void SA1::mmio_w220a(uint8_t data) {
+  if(!mmio.sa1_irqen   && (data & 0x80) && mmio.sa1_irqfl  ) mmio.sa1_irqcl   = 0;
+  if(!mmio.timer_irqen && (data & 0x40) && mmio.timer_irqfl) mmio.timer_irqcl = 0;
+  if(!mmio.dma_irqen   && (data & 0x20) && mmio.dma_irqfl  ) mmio.dma_irqcl   = 0;
+  if(!mmio.sa1_nmien   && (data & 0x10) && mmio.sa1_nmifl  ) mmio.sa1_nmicl   = 0;
+
+  mmio.sa1_irqen   = (data & 0x80);
+  mmio.timer_irqen = (data & 0x40);
+  mmio.dma_irqen   = (data & 0x20);
+  mmio.sa1_nmien   = (data & 0x10);
+}
+
+//(CIC) SA-1 interrupt clear
+void SA1::mmio_w220b(uint8_t data) {
+  mmio.sa1_irqcl   = (data & 0x80);
+  mmio.timer_irqcl = (data & 0x40);
+  mmio.dma_irqcl   = (data & 0x20);
+  mmio.sa1_nmicl   = (data & 0x10);
+
+  if(mmio.sa1_irqcl)   mmio.sa1_irqfl   = false;
+  if(mmio.timer_irqcl) mmio.timer_irqfl = false;
+  if(mmio.dma_irqcl)   mmio.dma_irqfl   = false;
+  if(mmio.sa1_nmicl)   mmio.sa1_nmifl   = false;
+}
+
+//(SNV) S-CPU NMI vector
+void SA1::mmio_w220c(uint8_t data) { mmio.snv = (mmio.snv & 0xff00) | data;      }
+void SA1::mmio_w220d(uint8_t data) { mmio.snv = (data << 8) | (mmio.snv & 0xff); }
+
+//(SIV) S-CPU IRQ vector
+void SA1::mmio_w220e(uint8_t data) { mmio.siv = (mmio.siv & 0xff00) | data;      }
+void SA1::mmio_w220f(uint8_t data) { mmio.siv = (data << 8) | (mmio.siv & 0xff); }
+
+//(TMC) H/V timer control
+void SA1::mmio_w2210(uint8_t data) {
+  mmio.hvselb = (data & 0x80);
+  mmio.ven    = (data & 0x02);
+  mmio.hen    = (data & 0x01);
+}
+
+//(CTR) SA-1 timer restart
+void SA1::mmio_w2211(uint8_t data) {
+  status.vcounter = 0;
+  status.hcounter = 0;
+}
+
+//(HCNT) H-count
+void SA1::mmio_w2212(uint8_t data) { mmio.hcnt = (mmio.hcnt & 0xff00) | (data << 0); }
+void SA1::mmio_w2213(uint8_t data) { mmio.hcnt = (mmio.hcnt & 0x00ff) | (data << 8); }
+
+//(VCNT) V-count
+void SA1::mmio_w2214(uint8_t data) { mmio.vcnt = (mmio.vcnt & 0xff00) | (data << 0); }
+void SA1::mmio_w2215(uint8_t data) { mmio.vcnt = (mmio.vcnt & 0x00ff) | (data << 8); }
+
+//(CXB) Super MMC bank C
+void SA1::mmio_w2220(uint8_t data) {
+  mmio.cbmode = (data & 0x80);
+  mmio.cb     = (data & 0x07);
+
+  unsigned addr = mmio.cb << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.cbmode == 0) {
+       bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, memory::cartrom, 0x000000);
+    sa1bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, memory::cartrom, 0x000000);
+  } else {
+       bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, access, addr);
+
+  memory::vectorsp.sync();
+}
+
+//(DXB) Super MMC bank D
+void SA1::mmio_w2221(uint8_t data) {
+  mmio.dbmode = (data & 0x80);
+  mmio.db     = (data & 0x07);
+
+  unsigned addr = mmio.db << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.dbmode == 0) {
+       bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, memory::cartrom, 0x100000);
+    sa1bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, memory::cartrom, 0x100000);
+  } else {
+       bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0x20, 0x3f, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, access, addr);
+}
+
+//(EXB) Super MMC bank E
+void SA1::mmio_w2222(uint8_t data) {
+  mmio.ebmode = (data & 0x80);
+  mmio.eb     = (data & 0x07);
+
+  unsigned addr = mmio.eb << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.ebmode == 0) {
+       bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom, 0x200000);
+    sa1bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom, 0x200000);
+  } else {
+       bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, access, addr);
+}
+
+//(FXB) Super MMC bank F
+void SA1::mmio_w2223(uint8_t data) {
+  mmio.fbmode = (data & 0x80);
+  mmio.fb     = (data & 0x07);
+
+  unsigned addr = mmio.fb << 20;
+  Memory &access = mmio_access(addr);
+
+  if(mmio.fbmode == 0) {
+       bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, memory::cartrom, 0x300000);
+    sa1bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, memory::cartrom, 0x300000);
+  } else {
+       bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, access, addr);
+    sa1bus.map(Bus::MapLinear, 0xa0, 0xbf, 0x8000, 0xffff, access, addr);
+  }
+
+     bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, access, addr);
+  sa1bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, access, addr);
+}
+
+//(BMAPS) S-CPU BW-RAM address mapping
+void SA1::mmio_w2224(uint8_t data) {
+  mmio.sbm = (data & 0x1f);
+
+  bus.map(Bus::MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::cc1bwram, mmio.sbm * 0x2000, 0x2000);
+  bus.map(Bus::MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::cc1bwram, mmio.sbm * 0x2000, 0x2000);
+}
+
+//(BMAP) SA-1 BW-RAM address mapping
+void SA1::mmio_w2225(uint8_t data) {
+  mmio.sw46 = (data & 0x80);
+  mmio.cbm  = (data & 0x7f);
+
+  if(mmio.sw46 == 0) {
+    //$[40-43]:[0000-ffff] x  32 projection
+    sa1bus.map(Bus::MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::bwram, (mmio.cbm & 0x1f) * 0x2000, 0x2000);
+    sa1bus.map(Bus::MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::bwram, (mmio.cbm & 0x1f) * 0x2000, 0x2000);
+  } else {
+    //$[60-6f]:[0000-ffff] x 128 projection
+    sa1bus.map(Bus::MapLinear, 0x00, 0x3f, 0x6000, 0x7fff, memory::bitmapram, mmio.cbm * 0x2000, 0x2000);
+    sa1bus.map(Bus::MapLinear, 0x80, 0xbf, 0x6000, 0x7fff, memory::bitmapram, mmio.cbm * 0x2000, 0x2000);
+  }
+}
+
+//(SWBE) S-CPU BW-RAM write enable
+void SA1::mmio_w2226(uint8_t data) {
+  mmio.swen = (data & 0x80);
+}
+
+//(CWBE) SA-1 BW-RAM write enable
+void SA1::mmio_w2227(uint8_t data) {
+  mmio.cwen = (data & 0x80);
+}
+
+//(BWPA) BW-RAM write-protected area
+void SA1::mmio_w2228(uint8_t data) {
+  mmio.bwp = (data & 0x0f);
+}
+
+//(SIWP) S-CPU I-RAM write protection
+void SA1::mmio_w2229(uint8_t data) {
+  mmio.siwp = data;
+}
+
+//(CIWP) SA-1 I-RAM write protection
+void SA1::mmio_w222a(uint8_t data) {
+  mmio.ciwp = data;
+}
+
+//(DCNT) DMA control
+void SA1::mmio_w2230(uint8_t data) {
+  mmio.dmaen = (data & 0x80);
+  mmio.dprio = (data & 0x40);
+  mmio.cden  = (data & 0x20);
+  mmio.cdsel = (data & 0x10);
+  mmio.dd    = (data & 0x04);
+  mmio.sd    = (data & 0x03);
+
+  if(mmio.dmaen == 0) dma.line = 0;
+}
+
+//(CDMA) character conversion DMA parameters
+void SA1::mmio_w2231(uint8_t data) {
+  mmio.chdend  = (data & 0x80);
+  mmio.dmasize = (data >> 2) & 7;
+  mmio.dmacb   = (data & 0x03);
+
+  if(mmio.chdend) memory::cc1bwram.dma = false;
+  if(mmio.dmasize > 5) mmio.dmasize = 5;
+  if(mmio.dmacb   > 2) mmio.dmacb   = 2;
+}
+
+//(SDA) DMA source device start address
+void SA1::mmio_w2232(uint8_t data) { mmio.dsa = (mmio.dsa & 0xffff00) | (data <<  0); }
+void SA1::mmio_w2233(uint8_t data) { mmio.dsa = (mmio.dsa & 0xff00ff) | (data <<  8); }
+void SA1::mmio_w2234(uint8_t data) { mmio.dsa = (mmio.dsa & 0x00ffff) | (data << 16); }
+
+//(DDA) DMA destination start address
+void SA1::mmio_w2235(uint8_t data) {
+  mmio.dda = (mmio.dda & 0xffff00) | (data <<  0);
+}
+
+void SA1::mmio_w2236(uint8_t data) {
+  mmio.dda = (mmio.dda & 0xff00ff) | (data <<  8);
+
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 0 && mmio.dd == DMA::DestIRAM) {
+      dma_normal();
+    } else if(mmio.cden == 1 && mmio.cdsel == 1) {
+      dma_cc1();
+    }
+  }
+}
+
+void SA1::mmio_w2237(uint8_t data) {
+  mmio.dda = (mmio.dda & 0x00ffff) | (data << 16);
+
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 0 && mmio.dd == DMA::DestBWRAM) {
+      dma_normal();
+    }
+  }
+}
+
+//(DTC) DMA terminal counter
+void SA1::mmio_w2238(uint8_t data) { mmio.dtc = (mmio.dtc & 0xff00) | (data << 0); }
+void SA1::mmio_w2239(uint8_t data) { mmio.dtc = (mmio.dtc & 0x00ff) | (data << 8); }
+
+//(BBF) BW-RAM bitmap format
+void SA1::mmio_w223f(uint8_t data) {
+  mmio.bbf = (data & 0x80);
+}
+
+//(BRF) bitmap register files
+void SA1::mmio_w2240(uint8_t data) { mmio.brf[ 0] = data; }
+void SA1::mmio_w2241(uint8_t data) { mmio.brf[ 1] = data; }
+void SA1::mmio_w2242(uint8_t data) { mmio.brf[ 2] = data; }
+void SA1::mmio_w2243(uint8_t data) { mmio.brf[ 3] = data; }
+void SA1::mmio_w2244(uint8_t data) { mmio.brf[ 4] = data; }
+void SA1::mmio_w2245(uint8_t data) { mmio.brf[ 5] = data; }
+void SA1::mmio_w2246(uint8_t data) { mmio.brf[ 6] = data; }
+void SA1::mmio_w2247(uint8_t data) { mmio.brf[ 7] = data;
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 1 && mmio.cdsel == 0) {
+      dma_cc2();
+    }
+  }
+}
+
+void SA1::mmio_w2248(uint8_t data) { mmio.brf[ 8] = data; }
+void SA1::mmio_w2249(uint8_t data) { mmio.brf[ 9] = data; }
+void SA1::mmio_w224a(uint8_t data) { mmio.brf[10] = data; }
+void SA1::mmio_w224b(uint8_t data) { mmio.brf[11] = data; }
+void SA1::mmio_w224c(uint8_t data) { mmio.brf[12] = data; }
+void SA1::mmio_w224d(uint8_t data) { mmio.brf[13] = data; }
+void SA1::mmio_w224e(uint8_t data) { mmio.brf[14] = data; }
+void SA1::mmio_w224f(uint8_t data) { mmio.brf[15] = data;
+  if(mmio.dmaen == true) {
+    if(mmio.cden == 1 && mmio.cdsel == 0) {
+      dma_cc2();
+    }
+  }
+}
+
+//(MCNT) arithmetic control
+void SA1::mmio_w2250(uint8_t data) {
+  mmio.acm = (data & 0x02);
+  mmio.md  = (data & 0x01);
+
+  if(mmio.acm) mmio.mr = 0;
+}
+
+//(MAL) multiplicand / dividend low
+void SA1::mmio_w2251(uint8_t data) {
+  mmio.ma = (mmio.ma & 0xff00) | data;
+}
+
+//(MAH) multiplicand / dividend high
+void SA1::mmio_w2252(uint8_t data) {
+  mmio.ma = (data << 8) | (mmio.ma & 0x00ff);
+}
+
+//(MBL) multiplier / divisor low
+void SA1::mmio_w2253(uint8_t data) {
+  mmio.mb = (mmio.mb & 0xff00) | data;
+}
+
+//(MBH) multiplier / divisor high
+//multiplication / cumulative sum only resets MB
+//division resets both MA and MB
+void SA1::mmio_w2254(uint8_t data) {
+  mmio.mb = (data << 8) | (mmio.mb & 0x00ff);
+
+  if(mmio.acm == 0) {
+    if(mmio.md == 0) {
+      //signed multiplication
+      mmio.mr = (int16_t)mmio.ma * (int16_t)mmio.mb;
+      mmio.mb = 0;
+    } else {
+      //unsigned division
+      if(mmio.mb == 0) {
+        mmio.mr = 0;
+      } else {
+        int16_t  quotient  = (int16_t)mmio.ma / (uint16_t)mmio.mb;
+        uint16_t remainder = (int16_t)mmio.ma % (uint16_t)mmio.mb;
+        mmio.mr = (remainder << 16) | quotient;
+      }
+      mmio.ma = 0;
+      mmio.mb = 0;
+    }
+  } else {
+    //sigma (accumulative multiplication)
+    mmio.mr += (int16_t)mmio.ma * (int16_t)mmio.mb;
+    mmio.overflow = (mmio.mr >= (1ULL << 40));
+    mmio.mr &= (1ULL << 40) - 1;
+    mmio.mb = 0;
+  }
+}
+
+//(VBD) variable-length bit processing
+void SA1::mmio_w2258(uint8_t data) {
+  mmio.hl = (data & 0x80);
+  mmio.vb = (data & 0x0f);
+  if(mmio.vb == 0) mmio.vb = 16;
+
+  if(mmio.hl == 0) {
+    //fixed mode
+    mmio.vbit += mmio.vb;
+    mmio.va += (mmio.vbit >> 3);
+    mmio.vbit &= 7;
+  }
+}
+
+//(VDA) variable-length bit game pak ROM start address
+void SA1::mmio_w2259(uint8_t data) { mmio.va = (mmio.va & 0xffff00) | (data <<  0); }
+void SA1::mmio_w225a(uint8_t data) { mmio.va = (mmio.va & 0xff00ff) | (data <<  8); }
+void SA1::mmio_w225b(uint8_t data) { mmio.va = (mmio.va & 0x00ffff) | (data << 16); mmio.vbit = 0; }
+
+//(SFR) S-CPU flag read
+uint8_t SA1::mmio_r2300() {
+  uint8_t data;
+  data  = mmio.cpu_irqfl   << 7;
+  data |= mmio.cpu_ivsw    << 6;
+  data |= mmio.chdma_irqfl << 5;
+  data |= mmio.cpu_nvsw    << 4;
+  data |= mmio.cmeg;
+  return data;
+}
+
+//(CFR) SA-1 flag read
+uint8_t SA1::mmio_r2301() {
+  uint8_t data;
+  data  = mmio.sa1_irqfl   << 7;
+  data |= mmio.timer_irqfl << 6;
+  data |= mmio.dma_irqfl   << 5;
+  data |= mmio.sa1_nmifl   << 4;
+  data |= mmio.smeg;
+  return data;
+}
+
+//(HCR) hcounter read
+uint8_t SA1::mmio_r2302() {
+  //latch counters
+  mmio.hcr = status.hcounter >> 2;
+  mmio.vcr = status.vcounter;
+                            return mmio.hcr >> 0; }
+uint8_t SA1::mmio_r2303() { return mmio.hcr >> 8; }
+
+//(VCR) vcounter read
+uint8_t SA1::mmio_r2304() { return mmio.vcr >> 0; }
+uint8_t SA1::mmio_r2305() { return mmio.vcr >> 8; }
+
+//(MR) arithmetic result
+uint8_t SA1::mmio_r2306() { return mmio.mr >>  0; }
+uint8_t SA1::mmio_r2307() { return mmio.mr >>  8; }
+uint8_t SA1::mmio_r2308() { return mmio.mr >> 16; }
+uint8_t SA1::mmio_r2309() { return mmio.mr >> 24; }
+uint8_t SA1::mmio_r230a() { return mmio.mr >> 32; }
+
+//(OF) arithmetic overflow flag
+uint8_t SA1::mmio_r230b() { return mmio.overflow << 7; }
+
+//(VDPL) variable-length data read port low
+uint8_t SA1::mmio_r230c() {
+  uint32_t data = (sa1bus.read(mmio.va + 0) <<  0)
+                | (sa1bus.read(mmio.va + 1) <<  8)
+                | (sa1bus.read(mmio.va + 2) << 16);
+  data >>= mmio.vbit;
+  return data >> 0;
+}
+
+//(VDPH) variable-length data read port high
+uint8_t SA1::mmio_r230d() {
+  uint32_t data = (sa1bus.read(mmio.va + 0) <<  0)
+                | (sa1bus.read(mmio.va + 1) <<  8)
+                | (sa1bus.read(mmio.va + 2) << 16);
+  data >>= mmio.vbit;
+
+  if(mmio.hl == 1) {
+    //auto-increment mode
+    mmio.vbit += mmio.vb;
+    mmio.va += (mmio.vbit >> 3);
+    mmio.vbit &= 7;
+  }
+
+  return data >> 8;
+}
+
+//(VC) version code register
+uint8_t SA1::mmio_r230e() {
+  return 0x01;  //true value unknown
+}
+
+uint8_t SA1::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    case 0x2300: return mmio_r2300();
+    case 0x2301: return mmio_r2301();
+    case 0x2302: return mmio_r2302();
+    case 0x2303: return mmio_r2303();
+    case 0x2304: return mmio_r2304();
+    case 0x2305: return mmio_r2305();
+    case 0x2306: return mmio_r2306();
+    case 0x2307: return mmio_r2307();
+    case 0x2308: return mmio_r2308();
+    case 0x2309: return mmio_r2309();
+    case 0x230a: return mmio_r230a();
+    case 0x230b: return mmio_r230b();
+    case 0x230c: return mmio_r230c();
+    case 0x230d: return mmio_r230d();
+    case 0x230e: return mmio_r230e();
+  }
+
+  return 0x00;
+}
+
+void SA1::mmio_write(unsigned addr, uint8_t data) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    case 0x2200: return mmio_w2200(data);
+    case 0x2201: return mmio_w2201(data);
+    case 0x2202: return mmio_w2202(data);
+    case 0x2203: return mmio_w2203(data);
+    case 0x2204: return mmio_w2204(data);
+    case 0x2205: return mmio_w2205(data);
+    case 0x2206: return mmio_w2206(data);
+    case 0x2207: return mmio_w2207(data);
+    case 0x2208: return mmio_w2208(data);
+    case 0x2209: return mmio_w2209(data);
+    case 0x220a: return mmio_w220a(data);
+    case 0x220b: return mmio_w220b(data);
+    case 0x220c: return mmio_w220c(data);
+    case 0x220d: return mmio_w220d(data);
+    case 0x220e: return mmio_w220e(data);
+    case 0x220f: return mmio_w220f(data);
+
+    case 0x2210: return mmio_w2210(data);
+    case 0x2211: return mmio_w2211(data);
+    case 0x2212: return mmio_w2212(data);
+    case 0x2213: return mmio_w2213(data);
+    case 0x2214: return mmio_w2214(data);
+    case 0x2215: return mmio_w2215(data);
+
+    case 0x2220: return mmio_w2220(data);
+    case 0x2221: return mmio_w2221(data);
+    case 0x2222: return mmio_w2222(data);
+    case 0x2223: return mmio_w2223(data);
+    case 0x2224: return mmio_w2224(data);
+    case 0x2225: return mmio_w2225(data);
+    case 0x2226: return mmio_w2226(data);
+    case 0x2227: return mmio_w2227(data);
+    case 0x2228: return mmio_w2228(data);
+    case 0x2229: return mmio_w2229(data);
+    case 0x222a: return mmio_w222a(data);
+
+    case 0x2230: return mmio_w2230(data);
+    case 0x2231: return mmio_w2231(data);
+    case 0x2232: return mmio_w2232(data);
+    case 0x2233: return mmio_w2233(data);
+    case 0x2234: return mmio_w2234(data);
+    case 0x2235: return mmio_w2235(data);
+    case 0x2236: return mmio_w2236(data);
+    case 0x2237: return mmio_w2237(data);
+    case 0x2238: return mmio_w2238(data);
+    case 0x2239: return mmio_w2239(data);
+
+    case 0x223f: return mmio_w223f(data);
+    case 0x2240: return mmio_w2240(data);
+    case 0x2241: return mmio_w2241(data);
+    case 0x2242: return mmio_w2242(data);
+    case 0x2243: return mmio_w2243(data);
+    case 0x2244: return mmio_w2244(data);
+    case 0x2245: return mmio_w2245(data);
+    case 0x2246: return mmio_w2246(data);
+    case 0x2247: return mmio_w2247(data);
+    case 0x2248: return mmio_w2248(data);
+    case 0x2249: return mmio_w2249(data);
+    case 0x224a: return mmio_w224a(data);
+    case 0x224b: return mmio_w224b(data);
+    case 0x224c: return mmio_w224c(data);
+    case 0x224d: return mmio_w224d(data);
+    case 0x224e: return mmio_w224e(data);
+    case 0x224f: return mmio_w224f(data);
+
+    case 0x2250: return mmio_w2250(data);
+    case 0x2251: return mmio_w2251(data);
+    case 0x2252: return mmio_w2252(data);
+    case 0x2253: return mmio_w2253(data);
+    case 0x2254: return mmio_w2254(data);
+
+    case 0x2258: return mmio_w2258(data);
+    case 0x2259: return mmio_w2259(data);
+    case 0x225a: return mmio_w225a(data);
+    case 0x225b: return mmio_w225b(data);
+  }
+}
+
+#endif

src/chip/sa1/mmio/mmio.hpp

@@ -0,0 +1,256 @@
+uint8_t mmio_read(unsigned addr);
+void mmio_write(unsigned addr, uint8_t data);
+Memory& mmio_access(unsigned &addr);
+
+struct MMIO {
+  //$2200 CCNT
+  bool sa1_irq;
+  bool sa1_rdyb;
+  bool sa1_resb;
+  bool sa1_nmi;
+  uint8_t smeg;
+
+  //$2201 SIE
+  bool cpu_irqen;
+  bool chdma_irqen;
+
+  //$2202 SIC
+  bool cpu_irqcl;
+  bool chdma_irqcl;
+
+  //$2203,$2204 CRV
+  uint16_t crv;
+
+  //$2205,$2206 CNV
+  uint16_t cnv;
+
+  //$2207,$2208 CIV
+  uint16_t civ;
+
+  //$2209 SCNT
+  bool cpu_irq;
+  bool cpu_ivsw;
+  bool cpu_nvsw;
+  uint8_t cmeg;
+
+  //$220a CIE
+  bool sa1_irqen;
+  bool timer_irqen;
+  bool dma_irqen;
+  bool sa1_nmien;
+
+  //$220b CIC
+  bool sa1_irqcl;
+  bool timer_irqcl;
+  bool dma_irqcl;
+  bool sa1_nmicl;
+
+  //$220c,$220d SNV
+  uint16_t snv;
+
+  //$220e,$220f SIV
+  uint16_t siv;
+
+  //$2210 TMC
+  bool hvselb;
+  bool ven;
+  bool hen;
+
+  //$2212,$2213
+  uint16_t hcnt;
+
+  //$2214,$2215
+  uint16_t vcnt;
+
+  //$2220 CXB
+  bool cbmode;
+  uint8_t cb;
+
+  //$2221 DXB
+  bool dbmode;
+  uint8_t db;
+
+  //$2222 EXB
+  bool ebmode;
+  uint8_t eb;
+
+  //$2223 FXB
+  bool fbmode;
+  uint8_t fb;
+
+  //$2224 BMAPS
+  uint8_t sbm;
+
+  //$2225 BMAP
+  bool sw46;
+  uint8_t cbm;
+
+  //$2226 SBWE
+  bool swen;
+
+  //$2227 CBWE
+  bool cwen;
+
+  //$2228 BWPA
+  uint8_t bwp;
+
+  //$2229 SIWP
+  uint8_t siwp;
+
+  //$222a CIWP
+  uint8_t ciwp;
+
+  //$2230 DCNT
+  bool dmaen;
+  bool dprio;
+  bool cden;
+  bool cdsel;
+  bool dd;
+  uint8_t sd;
+
+  //$2231 CDMA
+  bool chdend;
+  uint8_t dmasize;
+  uint8_t dmacb;
+
+  //$2232-$2234 SDA
+  uint32_t dsa;
+
+  //$2235-$2237 DDA
+  uint32_t dda;
+
+  //$2238,$2239 DTC
+  uint16_t dtc;
+
+  //$223f BBF
+  bool bbf;
+
+  //$2240-224f BRF
+  uint8_t brf[16];
+
+  //$2250 MCNT
+  bool acm;
+  bool md;
+
+  //$2251,$2252 MA
+  uint16_t ma;
+
+  //$2253,$2254 MB
+  uint16_t mb;
+
+  //$2258 VBD
+  bool hl;
+  uint8_t vb;
+
+  //$2259-$225b VDA
+  uint32_t va;
+  uint8_t vbit;
+
+  //$2300 SFR
+  bool cpu_irqfl;
+  bool chdma_irqfl;
+
+  //$2301 CFR
+  bool sa1_irqfl;
+  bool timer_irqfl;
+  bool dma_irqfl;
+  bool sa1_nmifl;
+
+  //$2302,$2303 HCR
+  uint16_t hcr;
+
+  //$2304,$2305 VCR
+  uint16_t vcr;
+
+  //$2306-230a MR
+  uint64_t mr;
+
+  //$230b OF
+  bool overflow;
+} mmio;
+
+void mmio_w2200(uint8_t);  //CCNT
+void mmio_w2201(uint8_t);  //SIE
+void mmio_w2202(uint8_t);  //SIC
+void mmio_w2203(uint8_t);  //CRVL
+void mmio_w2204(uint8_t);  //CRVH
+void mmio_w2205(uint8_t);  //CNVL
+void mmio_w2206(uint8_t);  //CNVH
+void mmio_w2207(uint8_t);  //CIVL
+void mmio_w2208(uint8_t);  //CIVH
+void mmio_w2209(uint8_t);  //SCNT
+void mmio_w220a(uint8_t);  //CIE
+void mmio_w220b(uint8_t);  //CIC
+void mmio_w220c(uint8_t);  //SNVL
+void mmio_w220d(uint8_t);  //SNVH
+void mmio_w220e(uint8_t);  //SIVL
+void mmio_w220f(uint8_t);  //SIVH
+void mmio_w2210(uint8_t);  //TMC
+void mmio_w2211(uint8_t);  //CTR
+void mmio_w2212(uint8_t);  //HCNTL
+void mmio_w2213(uint8_t);  //HCNTH
+void mmio_w2214(uint8_t);  //VCNTL
+void mmio_w2215(uint8_t);  //VCNTH
+void mmio_w2220(uint8_t);  //CXB
+void mmio_w2221(uint8_t);  //DXB
+void mmio_w2222(uint8_t);  //EXB
+void mmio_w2223(uint8_t);  //FXB
+void mmio_w2224(uint8_t);  //BMAPS
+void mmio_w2225(uint8_t);  //BMAP
+void mmio_w2226(uint8_t);  //SBWE
+void mmio_w2227(uint8_t);  //CBWE
+void mmio_w2228(uint8_t);  //BWPA
+void mmio_w2229(uint8_t);  //SIWP
+void mmio_w222a(uint8_t);  //CIWP
+void mmio_w2230(uint8_t);  //DCNT
+void mmio_w2231(uint8_t);  //CDMA
+void mmio_w2232(uint8_t);  //SDAL
+void mmio_w2233(uint8_t);  //SDAH
+void mmio_w2234(uint8_t);  //SDAB
+void mmio_w2235(uint8_t);  //DDAL
+void mmio_w2236(uint8_t);  //DDAH
+void mmio_w2237(uint8_t);  //DDAB
+void mmio_w2238(uint8_t);  //DTCL
+void mmio_w2239(uint8_t);  //DTCH
+void mmio_w223f(uint8_t);  //BBF
+void mmio_w2240(uint8_t);  //BRF0
+void mmio_w2241(uint8_t);  //BRF1
+void mmio_w2242(uint8_t);  //BRF2
+void mmio_w2243(uint8_t);  //BRF3
+void mmio_w2244(uint8_t);  //BRF4
+void mmio_w2245(uint8_t);  //BRF5
+void mmio_w2246(uint8_t);  //BRF6
+void mmio_w2247(uint8_t);  //BRF7
+void mmio_w2248(uint8_t);  //BRF8
+void mmio_w2249(uint8_t);  //BRF9
+void mmio_w224a(uint8_t);  //BRFA
+void mmio_w224b(uint8_t);  //BRFB
+void mmio_w224c(uint8_t);  //BRFC
+void mmio_w224d(uint8_t);  //BRFD
+void mmio_w224e(uint8_t);  //BRFE
+void mmio_w224f(uint8_t);  //BRFF
+void mmio_w2250(uint8_t);  //MCNT
+void mmio_w2251(uint8_t);  //MAL
+void mmio_w2252(uint8_t);  //MAH
+void mmio_w2253(uint8_t);  //MBL
+void mmio_w2254(uint8_t);  //MBH
+void mmio_w2258(uint8_t);  //VBD
+void mmio_w2259(uint8_t);  //VDAL
+void mmio_w225a(uint8_t);  //VDAH
+void mmio_w225b(uint8_t);  //VDAB
+
+uint8_t mmio_r2300();  //SFR
+uint8_t mmio_r2301();  //CFR
+uint8_t mmio_r2302();  //HCRL
+uint8_t mmio_r2303();  //HCRH
+uint8_t mmio_r2304();  //VCRL
+uint8_t mmio_r2305();  //VCRH
+uint8_t mmio_r2306();  //MR [00-07]
+uint8_t mmio_r2307();  //MR [08-15]
+uint8_t mmio_r2308();  //MR [16-23]
+uint8_t mmio_r2309();  //MR [24-31]
+uint8_t mmio_r230a();  //MR [32-40]
+uint8_t mmio_r230b();  //OF
+uint8_t mmio_r230c();  //VDPL
+uint8_t mmio_r230d();  //VDPH
+uint8_t mmio_r230e();  //VC

src/chip/sa1/sa1.cpp

@@ -0,0 +1,318 @@
+#include <../base.hpp>
+
+#define SA1_CPP
+namespace SNES {
+
+SA1 sa1;
+
+#include "bus/bus.cpp"
+#include "dma/dma.cpp"
+#include "memory/memory.cpp"
+#include "mmio/mmio.cpp"
+
+void SA1::enter() {
+  while(true) {
+    while(mmio.sa1_rdyb || mmio.sa1_resb) {
+      //SA-1 co-processor is asleep
+      tick();
+      scheduler.sync_copcpu();
+    }
+
+    if(status.interrupt_pending) {
+      status.interrupt_pending = false;
+      interrupt(status.interrupt_vector);
+    }
+
+    (this->*opcode_table[op_readpc()])();
+  }
+}
+
+void SA1::last_cycle() {
+  if(mmio.sa1_nmi && !mmio.sa1_nmicl) {
+    status.interrupt_pending = true;
+    status.interrupt_vector  = mmio.cnv;
+    mmio.sa1_nmifl = true;
+    mmio.sa1_nmicl = 1;
+    regs.wai = false;
+  } else if(!regs.p.i) {
+    if(mmio.timer_irqen && !mmio.timer_irqcl) {
+      status.interrupt_pending = true;
+      status.interrupt_vector  = mmio.civ;
+      mmio.timer_irqfl = true;
+      regs.wai = false;
+    } else if(mmio.dma_irqen && !mmio.dma_irqcl) {
+      status.interrupt_pending = true;
+      status.interrupt_vector  = mmio.civ;
+      mmio.dma_irqfl = true;
+      regs.wai = false;
+    } else if(mmio.sa1_irq && !mmio.sa1_irqcl) {
+      status.interrupt_pending = true;
+      status.interrupt_vector  = mmio.civ;
+      mmio.sa1_irqfl = true;
+      regs.wai = false;
+    }
+  }
+}
+
+void SA1::interrupt(uint16_t vector) {
+  op_read(regs.pc.d);
+  op_io();
+  if(!regs.e) op_writestack(regs.pc.b);
+  op_writestack(regs.pc.h);
+  op_writestack(regs.pc.l);
+  op_writestack(regs.e ? (regs.p & ~0x10) : regs.p);
+  regs.pc.w = vector;
+  regs.pc.b = 0x00;
+  regs.p.i  = 1;
+  regs.p.d  = 0;
+}
+
+bool SA1::interrupt_pending() {
+  return status.interrupt_pending;
+}
+
+void SA1::tick() {
+  scheduler.addclocks_cop(2);
+
+  //adjust counters:
+  //note that internally, status counters are in clocks;
+  //whereas MMIO register counters are in dots (4 clocks = 1 dot)
+  if(mmio.hvselb == 0) {
+    //HV timer
+    status.hcounter += 2;
+    if(status.hcounter >= 1364) {
+      status.hcounter = 0;
+      if(++status.vcounter >= status.scanlines) status.vcounter = 0;
+    }
+  } else {
+    //linear timer
+    status.hcounter += 2;
+    status.vcounter += (status.hcounter >> 11);
+    status.hcounter &= 0x07ff;
+    status.vcounter &= 0x01ff;
+  }
+
+  //test counters for timer IRQ
+  switch((mmio.ven << 1) + (mmio.hen << 0)) {
+    case 0: break;
+    case 1: if(status.hcounter == (mmio.hcnt << 2)) trigger_irq(); break;
+    case 2: if(status.vcounter == mmio.vcnt && status.hcounter == 0) trigger_irq(); break;
+    case 3: if(status.vcounter == mmio.hcnt && status.hcounter == (mmio.hcnt << 2)) trigger_irq(); break;
+  }
+}
+
+void SA1::trigger_irq() {
+  mmio.timer_irqfl = true;
+  if(mmio.timer_irqen) mmio.timer_irqcl = 0;
+}
+
+void SA1::init() {
+}
+
+void SA1::enable() {
+}
+
+void SA1::power() {
+  regs.a = regs.x = regs.y = 0x0000;
+  regs.s = 0x01ff;
+
+  reset();
+}
+
+void SA1::reset() {
+  memory::vectorsp.access = 0;
+  memory::cc1bwram.dma = false;
+  for(unsigned addr = 0; addr < memory::iram.size(); addr++) {
+    memory::iram.write(addr, 0x00);
+  }
+  sa1bus.init();
+
+  regs.pc.d = 0x000000;
+  regs.x.h  = 0x00;
+  regs.y.h  = 0x00;
+  regs.s.h  = 0x01;
+  regs.d    = 0x0000;
+  regs.db   = 0x00;
+  regs.p    = 0x34;
+  regs.e    = 1;
+  regs.mdr  = 0x00;
+  regs.wai  = false;
+  update_table();
+
+  status.interrupt_pending = false;
+  status.interrupt_vector  = 0x0000;
+
+  status.scanlines = (system.region() == System::NTSC ? 262 : 312);
+  status.vcounter  = 0;
+  status.hcounter  = 0;
+
+  dma.line = 0;
+
+  //$2200 CCNT
+  mmio.sa1_irq  = false;
+  mmio.sa1_rdyb = false;
+  mmio.sa1_resb = true;
+  mmio.sa1_nmi  = false;
+  mmio.smeg     = 0;
+
+  //$2201 SIE
+  mmio.cpu_irqen   = false;
+  mmio.chdma_irqen = false;
+
+  //$2202 SIC
+  mmio.cpu_irqcl   = false;
+  mmio.chdma_irqcl = false;
+
+  //$2203,$2204 CRV
+  mmio.crv = 0x0000;
+
+  //$2205,$2206 CNV
+  mmio.cnv = 0x0000;
+
+  //$2207,$2208 CIV
+  mmio.civ = 0x0000;
+
+  //$2209 SCNT
+  mmio.cpu_irq  = false;
+  mmio.cpu_ivsw = false;
+  mmio.cpu_nvsw = false;
+  mmio.cmeg     = 0;
+
+  //$220a CIE
+  mmio.sa1_irqen   = false;
+  mmio.timer_irqen = false;
+  mmio.dma_irqen   = false;
+  mmio.sa1_nmien   = false;
+
+  //$220b CIC
+  mmio.sa1_irqcl   = false;
+  mmio.timer_irqcl = false;
+  mmio.dma_irqcl   = false;
+  mmio.sa1_nmicl   = false;
+
+  //$220c,$220d SNV
+  mmio.snv = 0x0000;
+
+  //$220e,$220f SIV
+  mmio.siv = 0x0000;
+
+  //$2210
+  mmio.hvselb = false;
+  mmio.ven    = false;
+  mmio.hen    = false;
+
+  //$2212,$2213 HCNT
+  mmio.hcnt = 0x0000;
+
+  //$2214,$2215 VCNT
+  mmio.vcnt = 0x0000;
+
+  //$2220-2223 CXB, DXB, EXB, FXB
+  mmio.cbmode = 0;
+  mmio.dbmode = 0;
+  mmio.ebmode = 0;
+  mmio.fbmode = 0;
+
+  mmio.cb = 0x00;
+  mmio.db = 0x01;
+  mmio.eb = 0x02;
+  mmio.fb = 0x03;
+
+  //$2224 BMAPS
+  mmio.sbm = 0x00;
+
+  //$2225 BMAP
+  mmio.sw46 = false;
+  mmio.cbm  = 0x00;
+
+  //$2226 SWBE
+  mmio.swen = false;
+
+  //$2227 CWBE
+  mmio.cwen = false;
+
+  //$2228 BWPA
+  mmio.bwp = 0x0f;
+
+  //$2229 SIWP
+  mmio.siwp = 0x00;
+
+  //$222a CIWP
+  mmio.ciwp = 0x00;
+
+  //$2230 DCNT
+  mmio.dmaen = false;
+  mmio.dprio = false;
+  mmio.cden  = false;
+  mmio.cdsel = false;
+  mmio.dd    = 0;
+  mmio.sd    = 0;
+
+  //$2231 CDMA
+  mmio.chdend  = false;
+  mmio.dmasize = 0;
+  mmio.dmacb   = 0;
+
+  //$2232-$2234 SDA
+  mmio.dsa = 0x000000;
+
+  //$2235-$2237 DDA
+  mmio.dda = 0x000000;
+
+  //$2238,$2239 DTC
+  mmio.dtc = 0x0000;
+
+  //$223f BBF
+  mmio.bbf = 0;
+
+  //$2240-$224f BRF
+  for(unsigned i = 0; i < 16; i++) {
+    mmio.brf[i] = 0x00;
+  }
+
+  //$2250 MCNT
+  mmio.acm = 0;
+  mmio.md  = 0;
+
+  //$2251,$2252 MA
+  mmio.ma = 0x0000;
+
+  //$2253,$2254 MB
+  mmio.mb = 0x0000;
+
+  //$2258 VBD
+  mmio.hl = false;
+  mmio.vb = 16;
+
+  //$2259-$225b
+  mmio.va   = 0x000000;
+  mmio.vbit = 0;
+
+  //$2300 SFR
+  mmio.cpu_irqfl   = false;
+  mmio.chdma_irqfl = false;
+
+  //$2301 CFR
+  mmio.sa1_irqfl   = false;
+  mmio.timer_irqfl = false;
+  mmio.dma_irqfl   = false;
+  mmio.sa1_nmifl   = false;
+
+  //$2302,$2303 HCR
+  mmio.hcr = 0x0000;
+
+  //$2304,$2305 VCR
+  mmio.vcr = 0x0000;
+
+  //$2306-$230a MR
+  mmio.mr = 0;
+
+  //$230b
+  mmio.overflow = false;
+}
+
+SA1::SA1() {
+}
+
+};
+

src/chip/sa1/sa1.hpp

@@ -0,0 +1,35 @@
+#include "bus/bus.hpp"
+
+class SA1 : public CPUcore, public MMIO {
+public:
+  #include "dma/dma.hpp"
+  #include "memory/memory.hpp"
+  #include "mmio/mmio.hpp"
+
+  struct Status {
+    bool interrupt_pending;
+    uint16_t interrupt_vector;
+
+    uint16_t scanlines;
+    uint16_t vcounter;
+    uint16_t hcounter;
+  } status;
+
+  void enter();
+  void interrupt(uint16_t vector);
+  void tick();
+
+  alwaysinline void trigger_irq();
+  alwaysinline void last_cycle();
+  alwaysinline bool interrupt_pending();
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  SA1();
+};
+
+extern SA1 sa1;
+extern SA1Bus sa1bus;

src/chip/sdd1/sdd1.cpp

@@ -1,12 +1,26 @@
-#include "../../base.h"
-#define SDD1_CPP
+#include <../base.hpp>
+
+#define SDD1_CPP
+namespace SNES {
+
+SDD1 sdd1;
 
 #include "sdd1emu.cpp"
 
 void SDD1::init() {}
 
 void SDD1::enable() {
-  for(int i = 0x4800; i <= 0x4807; i++) memory::mmio.map(i, *this);
+  //hook S-CPU DMA MMIO registers to gather information for struct dma[];
+  //buffer address and transfer size information for use in SDD1::read()
+  for(unsigned i = 0x4300; i <= 0x437f; i++) {
+    cpu_mmio[i & 0x7f] = memory::mmio.mmio[i - 0x2000];
+    memory::mmio.map(i, *this);
+  }
+
+  //hook S-DD1 MMIO registers
+  for(unsigned i = 0x4800; i <= 0x4807; i++) {
+    memory::mmio.map(i, *this);
+  }
 }
 
 void SDD1::power() {
@@ -14,97 +28,135 @@ void SDD1::power() {
 }
 
 void SDD1::reset() {
-  sdd1.dma_active = false;
+  sdd1_enable = 0x00;
+  xfer_enable = 0x00;
 
-  regs.r4800 = 0x00;
-  regs.r4801 = 0x00;
+  mmc[0] = 0 << 20;
+  mmc[1] = 1 << 20;
+  mmc[2] = 2 << 20;
+  mmc[3] = 3 << 20;
 
-  regs.r4804 = 0x00;
-  regs.r4805 = 0x01;
-  regs.r4806 = 0x02;
-  regs.r4807 = 0x03;
+  for(unsigned i = 0; i < 8; i++) {
+    dma[i].addr = 0;
+    dma[i].size = 0;
+  }
 
-  bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, memory::cartrom, (regs.r4804 & 7) << 20);
-  bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, memory::cartrom, (regs.r4805 & 7) << 20);
-  bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, memory::cartrom, (regs.r4806 & 7) << 20);
-  bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, memory::cartrom, (regs.r4807 & 7) << 20);
+  buffer.ready = false;
+
+  bus.map(Bus::MapDirect, 0xc0, 0xff, 0x0000, 0xffff, *this);
 }
 
-uint8 SDD1::mmio_read(uint addr) {
-  switch(addr & 0xffff) {
-    case 0x4804: return regs.r4804;
-    case 0x4805: return regs.r4805;
-    case 0x4806: return regs.r4806;
-    case 0x4807: return regs.r4807;
+uint8 SDD1::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+
+  if((addr & 0x4380) == 0x4300) {
+    return cpu_mmio[addr & 0x7f]->mmio_read(addr);
+  }
+
+  switch(addr) {
+    case 0x4804: return (mmc[0] >> 20) & 7;
+    case 0x4805: return (mmc[1] >> 20) & 7;
+    case 0x4806: return (mmc[2] >> 20) & 7;
+    case 0x4807: return (mmc[3] >> 20) & 7;
   }
 
   return cpu.regs.mdr;
 }
 
-void SDD1::mmio_write(uint addr, uint8 data) {
-  switch(addr & 0xffff) {
-    case 0x4800: {
-      regs.r4800 = data;
-    } break;
+void SDD1::mmio_write(unsigned addr, uint8 data) {
+  addr &= 0xffff;
 
-    case 0x4801: {
-      regs.r4801 = data;
-    } break;
+  if((addr & 0x4380) == 0x4300) {
+    unsigned channel = (addr >> 4) & 7;
+    switch(addr & 15) {
+      case 2: dma[channel].addr = (dma[channel].addr & 0xffff00) + (data <<  0); break;
+      case 3: dma[channel].addr = (dma[channel].addr & 0xff00ff) + (data <<  8); break;
+      case 4: dma[channel].addr = (dma[channel].addr & 0x00ffff) + (data << 16); break;
 
-    case 0x4804: {
-      if(regs.r4804 != data) {
-        regs.r4804 = data;
-        bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4804 & 7) << 20);
-      }
-    } break;
+      case 5: dma[channel].size = (dma[channel].size &   0xff00) + (data <<  0); break;
+      case 6: dma[channel].size = (dma[channel].size &   0x00ff) + (data <<  8); break;
+    }
+    return cpu_mmio[addr & 0x7f]->mmio_write(addr, data);
+  }
 
-    case 0x4805: {
-      if(regs.r4805 != data) {
-        regs.r4805 = data;
-        bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4805 & 7) << 20);
-      }
-    } break;
+  switch(addr) {
+    case 0x4800: sdd1_enable = data; break;
+    case 0x4801: xfer_enable = data; break;
 
-    case 0x4806: {
-      if(regs.r4806 != data) {
-        regs.r4806 = data;
-        bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4806 & 7) << 20);
-      }
-    } break;
-
-    case 0x4807: {
-      if(regs.r4807 != data) {
-        regs.r4807 = data;
-        bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff,
-          memory::cartrom, (regs.r4807 & 7) << 20);
-      }
-    } break;
+    case 0x4804: mmc[0] = (data & 7) << 20; break;
+    case 0x4805: mmc[1] = (data & 7) << 20; break;
+    case 0x4806: mmc[2] = (data & 7) << 20; break;
+    case 0x4807: mmc[3] = (data & 7) << 20; break;
   }
 }
 
-void SDD1::dma_begin(uint8 channel, uint32 addr, uint16 length) {
-  if(regs.r4800 & (1 << channel) && regs.r4801 & (1 << channel)) {
-    regs.r4801 &= ~(1 << channel);
-    sdd1.dma_active   = true;
-    sdd1.buffer_index = 0;
-    sdd1.buffer_size  = length;
-    sdd1emu.decompress(addr, (length) ? length : 65536, sdd1.buffer);
-  }
+//SDD1::read() is mapped to $[c0-ff]:[0000-ffff]
+//the design is meant to be as close to the hardware design as possible, thus this code
+//avoids adding S-DD1 hooks inside S-CPU::DMA emulation.
+//
+//the real S-DD1 cannot see $420b (DMA enable) writes, as they are not placed on the bus.
+//however, $43x0-$43xf writes (DMAx channel settings) most likely do appear on the bus.
+//the S-DD1 also requires fixed addresses for transfers, which wouldn't be necessary if
+//it could see $420b writes (eg it would know when the transfer should begin.)
+//
+//the hardware needs a way to distinguish program code after $4801 writes from DMA
+//decompression that follows soon after.
+//
+//the only plausible design for hardware would be for the S-DD1 to spy on DMAx settings,
+//and begin spooling decompression on writes to $4801 that activate a channel. after that,
+//it feeds decompressed data only when the ROM read address matches the DMA channel address.
+//
+//the actual S-DD1 transfer can occur on any channel, but it is most likely limited to
+//one transfer per $420b write (for spooling purposes). however, this is not known for certain.
+uint8 SDD1::read(unsigned addr) {
+  if(sdd1_enable & xfer_enable) {
+    //at least one channel has S-DD1 decompression enabled ...
+    for(unsigned i = 0; i < 8; i++) {
+      if(sdd1_enable & xfer_enable & (1 << i)) {
+        //S-DD1 always uses fixed transfer mode, so address will not change during transfer
+        if(addr == dma[i].addr) {
+          if(!buffer.ready) {
+            //first byte read for channel performs full decompression.
+            //this really should stream byte-by-byte, but it's not necessary since the size is known
+            buffer.offset = 0;
+            buffer.size = dma[i].size ? dma[i].size : 65536;
+
+            //sdd1emu calls this function; it needs to access uncompressed data;
+            //so temporarily disable decompression mode for decompress() call.
+            uint8 temp = sdd1_enable;
+            sdd1_enable = false;
+            sdd1emu.decompress(addr, buffer.size, buffer.data);
+            sdd1_enable = temp;
+
+            buffer.ready = true;
+          }
+
+          //fetch a decompressed byte; once buffer is depleted, disable channel and invalidate buffer
+          uint8 data = buffer.data[(uint16)buffer.offset++];
+          if(buffer.offset >= buffer.size) {
+            buffer.ready = false;
+            xfer_enable &= ~(1 << i);
+          }
+
+          return data;
+        }  //address matched
+      }  //channel enabled
+    }  //channel loop
+  }  //S-DD1 decompressor enabled
+
+  //S-DD1 decompression mode inactive; return ROM data
+  return memory::cartrom.read(mmc[(addr >> 20) & 3] + (addr & 0x0fffff));
 }
 
-bool SDD1::dma_active() {
-  return sdd1.dma_active;
+void SDD1::write(unsigned addr, uint8 data) {
 }
 
-uint8 SDD1::dma_read() {
-  if(--sdd1.buffer_size == 0) sdd1.dma_active = false;
-
-//sdd1.buffer[] is 65536 bytes, and sdd1.buffer_index
-//is of type uint16, so no buffer overflow is possible
-  return sdd1.buffer[sdd1.buffer_index++];
+SDD1::SDD1() {
+  buffer.data = new uint8[65536];
 }
 
-SDD1::SDD1() {}
+SDD1::~SDD1() {
+  delete[] buffer.data;
+}
+};
+

src/chip/sdd1/sdd1.h

@@ -1,39 +0,0 @@
-#include "sdd1emu.h"
-
-class SDD1 : public MMIO {
-public:
-  void init();
-  void enable();
-  void power();
-  void reset();
-
-  uint8 mmio_read (uint addr);
-  void  mmio_write(uint addr, uint8 data);
-
-  void  dma_begin(uint8 channel, uint32 addr, uint16 length);
-  bool  dma_active();
-  uint8 dma_read();
-
-  SDD1();
-
-private:
-  SDD1emu sdd1emu;
-
-  struct {
-    uint8  buffer[65536]; //pointer to decompressed S-DD1 data, max DMA length is 65536
-    uint16 buffer_index;  //DMA read index into S-DD1 decompression buffer
-    uint16 buffer_size;
-    bool   dma_active;
-  } sdd1;
-
-  struct {
-    uint8 r4800;
-    uint8 r4801;
-    uint8 r4804;
-    uint8 r4805;
-    uint8 r4806;
-    uint8 r4807;
-  } regs;
-};
-
-extern SDD1 sdd1;

src/chip/sdd1/sdd1.hpp

@@ -0,0 +1,40 @@
+#include "sdd1emu.hpp"
+
+class SDD1 : public MMIO, public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read(unsigned addr);
+  void mmio_write(unsigned addr, uint8 data);
+
+  uint8 read(unsigned addr);
+  void write(unsigned addr, uint8 data);
+
+  SDD1();
+  ~SDD1();
+
+private:
+  MMIO *cpu_mmio[0x80];  //bus spying hooks to glean information for struct dma[]
+
+  uint8 sdd1_enable;     //channel bit-mask
+  uint8 xfer_enable;     //channel bit-mask
+  unsigned mmc[4];       //memory map controller ROM indices
+
+  struct {
+    unsigned addr;       //$43x2-$43x4 -- DMA transfer address
+    uint16 size;         //$43x5-$43x6 -- DMA transfer size
+  } dma[8];
+
+  SDD1emu sdd1emu;
+  struct {
+    uint8 *data;         //pointer to decompressed S-DD1 data (65536 bytes)
+    uint16 offset;       //read index into S-DD1 decompression buffer
+    unsigned size;       //length of data buffer; reads decrement counter, set ready to false at 0
+    bool ready;          //true when data[] is valid; false to invoke sdd1emu.decompress()
+  } buffer;
+};
+
+extern SDD1 sdd1;

src/chip/sdd1/sdd1emu.cpp

@@ -30,7 +30,7 @@ understood.
 
 ************************************************************************/
 
-#define SDD1_read(__addr) (bus.read(__addr))
+#define SDD1_read(__addr) (sdd1.read(__addr))
 
 ////////////////////////////////////////////////////
 
@@ -448,4 +448,4 @@ SDD1emu::SDD1emu() :
 
 ///////////////////////////////////////////////////////////
 
-#endif //ifdef SDD1_CPP
+#endif

src/chip/sgb/sgb.cpp

@@ -0,0 +1,66 @@
+#include <../base.hpp>
+
+#define SGB_CPP
+namespace SNES {
+
+SuperGameBoy sgb;
+
+void SuperGameBoy::enter() {
+  while(true) {
+    if(sgb_run) {
+      unsigned samples = sgb_run(samplebuffer, 16);
+      scheduler.addclocks_cop(samples * 10);
+      scheduler.sync_copcpu();
+    } else {
+      scheduler.addclocks_cop(64 * 1024 * 1024);
+      scheduler.sync_copcpu();
+    }
+  }
+}
+
+uint8_t SuperGameBoy::read(unsigned addr) {
+  addr &= 0xffff;
+  if(sgb_read) return sgb_read(addr);
+  return 0x00;
+}
+
+void SuperGameBoy::write(unsigned addr, uint8_t data) {
+  addr &= 0xffff;
+  if(sgb_write) return sgb_write(addr, data);
+}
+
+void SuperGameBoy::init() {
+  if(libsgb.open("SuperGameBoy")) {
+    sgb_init  = libsgb.sym("sgb_init");
+    sgb_term  = libsgb.sym("sgb_term");
+    sgb_power = libsgb.sym("sgb_power");
+    sgb_reset = libsgb.sym("sgb_reset");
+    sgb_read  = libsgb.sym("sgb_read");
+    sgb_write = libsgb.sym("sgb_write");
+    sgb_run   = libsgb.sym("sgb_run");
+  }
+}
+
+void SuperGameBoy::enable() {
+}
+
+void SuperGameBoy::power() {
+  bus.map(Bus::MapDirect, 0x00, 0x3f, 0x6000, 0x7fff, *this);
+  bus.map(Bus::MapDirect, 0x80, 0xbf, 0x6000, 0x7fff, *this);
+
+  if(sgb_init) {
+    sgb_init(SGB2,
+      memory::gbrom.data(), memory::gbrom.size(),
+      memory::gbram.data(), memory::gbram.size()
+    );
+  }
+
+  if(sgb_power) sgb_power();
+}
+
+void SuperGameBoy::reset() {
+  if(sgb_reset) sgb_reset();
+}
+
+};
+

src/chip/sgb/sgb.hpp

@@ -0,0 +1,28 @@
+class SuperGameBoy : public Memory {
+public:
+  void enter();
+
+  uint8_t read(unsigned addr);
+  void write(unsigned addr, uint8_t data);
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+private:
+  library libsgb;
+  uint32_t samplebuffer[4096];
+
+  enum { SGB1 = 0, SGB2 = 1 };
+  function<bool (bool, uint8_t*, unsigned, uint8_t*, unsigned)> sgb_init;
+  function<void ()> sgb_term;
+  function<void ()> sgb_power;
+  function<void ()> sgb_reset;
+  function<uint8_t (unsigned)> sgb_read;
+  function<void (unsigned, uint8_t)> sgb_write;
+  function<unsigned (uint32_t*, unsigned)> sgb_run;
+};
+
+extern SuperGameBoy sgb;
+

src/chip/spc7110/decomp.cpp

@@ -0,0 +1,511 @@
+#ifdef SPC7110_CPP
+
+uint8 SPC7110Decomp::read() {
+  if(decomp_buffer_length == 0) {
+    //decompress at least (decomp_buffer_size / 2) bytes to the buffer
+    switch(decomp_mode) {
+      case 0: mode0(false); break;
+      case 1: mode1(false); break;
+      case 2: mode2(false); break;
+      default: return 0x00;
+    }
+  }
+
+  uint8 data = decomp_buffer[decomp_buffer_rdoffset++];
+  decomp_buffer_rdoffset &= decomp_buffer_size - 1;
+  decomp_buffer_length--;
+  return data;
+}
+
+void SPC7110Decomp::write(uint8 data) {
+  decomp_buffer[decomp_buffer_wroffset++] = data;
+  decomp_buffer_wroffset &= decomp_buffer_size - 1;
+  decomp_buffer_length++;
+}
+
+uint8 SPC7110Decomp::dataread() {
+  unsigned size = memory::cartrom.size() - 0x100000;
+  while(decomp_offset >= size) decomp_offset -= size;
+  return memory::cartrom.read(0x100000 + decomp_offset++);
+}
+
+void SPC7110Decomp::init(unsigned mode, unsigned offset, unsigned index) {
+  decomp_mode = mode;
+  decomp_offset = offset;
+
+  decomp_buffer_rdoffset = 0;
+  decomp_buffer_wroffset = 0;
+  decomp_buffer_length   = 0;
+
+  //reset context states
+  for(unsigned i = 0; i < 32; i++) {
+    context[i].index  = 0;
+    context[i].invert = 0;
+  }
+
+  switch(decomp_mode) {
+    case 0: mode0(true); break;
+    case 1: mode1(true); break;
+    case 2: mode2(true); break;
+  }
+
+  //decompress up to requested output data index
+  while(index--) read();
+}
+
+//
+
+void SPC7110Decomp::mode0(bool init) {
+  static uint8 val, in, span;
+  static int out, inverts, lps, in_count;
+
+  if(init == true) {
+    out = inverts = lps = 0;
+    span = 0xff;
+    val = dataread();
+    in = dataread();
+    in_count = 8;
+    return;
+  }
+
+  while(decomp_buffer_length < (decomp_buffer_size >> 1)) {
+    for(unsigned bit = 0; bit < 8; bit++) {
+      //get context
+      uint8 mask = (1 << (bit & 3)) - 1;
+      uint8 con = mask + ((inverts & mask) ^ (lps & mask));
+      if(bit > 3) con += 15;
+
+      //get prob and mps
+      unsigned prob = probability(con);
+      unsigned mps = (((out >> 15) & 1) ^ context[con].invert);
+
+      //get bit
+      unsigned flag_lps;
+      if(val <= span - prob) { //mps
+        span = span - prob;
+        out = (out << 1) + mps;
+        flag_lps = 0;
+      } else { //lps
+        val = val - (span - (prob - 1));
+        span = prob - 1;
+        out = (out << 1) + 1 - mps;
+        flag_lps = 1;
+      }
+
+      //renormalize
+      unsigned shift = 0;
+      while(span < 0x7f) {
+        shift++;
+
+        span = (span << 1) + 1;
+        val = (val << 1) + (in >> 7);
+
+        in <<= 1;
+        if(--in_count == 0) {
+          in = dataread();
+          in_count = 8;
+        }
+      }
+
+      //update processing info
+      lps = (lps << 1) + flag_lps;
+      inverts = (inverts << 1) + context[con].invert;
+
+      //update context state
+      if(flag_lps & toggle_invert(con)) context[con].invert ^= 1;
+      if(flag_lps) context[con].index = next_lps(con);
+      else if(shift) context[con].index = next_mps(con);
+    }
+
+    //save byte
+    write(out);
+  }
+}
+
+void SPC7110Decomp::mode1(bool init) {
+  static int pixelorder[4], realorder[4];
+  static uint8 in, val, span;
+  static int out, inverts, lps, in_count;
+
+  if(init == true) {
+    for(unsigned i = 0; i < 4; i++) pixelorder[i] = i;
+    out = inverts = lps = 0;
+    span = 0xff;
+    val = dataread();
+    in = dataread();
+    in_count = 8;
+    return;
+  }
+
+  while(decomp_buffer_length < (decomp_buffer_size >> 1)) {
+    for(unsigned pixel = 0; pixel < 8; pixel++) {
+      //get first symbol context
+      unsigned a = ((out >> (1 * 2)) & 3);
+      unsigned b = ((out >> (7 * 2)) & 3);
+      unsigned c = ((out >> (8 * 2)) & 3);
+      unsigned con = (a == b) ? (b != c) : (b == c) ? 2 : 4 - (a == c);
+
+      //update pixel order
+      unsigned m, n;
+      for(m = 0; m < 4; m++) if(pixelorder[m] == a) break;
+      for(n = m; n > 0; n--) pixelorder[n] = pixelorder[n - 1];
+      pixelorder[0] = a;
+
+      //calculate the real pixel order
+      for(m = 0; m < 4; m++) realorder[m] = pixelorder[m];
+
+      //rotate reference pixel c value to top
+      for(m = 0; m < 4; m++) if(realorder[m] == c) break;
+      for(n = m; n > 0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = c;
+
+      //rotate reference pixel b value to top
+      for(m = 0; m < 4; m++) if(realorder[m] == b) break;
+      for(n = m; n > 0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = b;
+
+      //rotate reference pixel a value to top
+      for(m = 0; m < 4; m++) if(realorder[m] == a) break;
+      for(n = m; n > 0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = a;
+
+      //get 2 symbols
+      for(unsigned bit = 0; bit < 2; bit++) {
+        //get prob
+        unsigned prob = probability(con);
+
+        //get symbol
+        unsigned flag_lps;
+        if(val <= span - prob) { //mps
+          span = span - prob;
+          flag_lps = 0;
+        } else { //lps
+          val = val - (span - (prob - 1));
+          span = prob - 1;
+          flag_lps = 1;
+        }
+
+        //renormalize
+        unsigned shift = 0;
+        while(span < 0x7f) {
+          shift++;
+
+          span = (span << 1) + 1;
+          val = (val << 1) + (in >> 7);
+
+          in <<= 1;
+          if(--in_count == 0) {
+            in = dataread();
+            in_count = 8;
+          }
+        }
+
+        //update processing info
+        lps = (lps << 1) + flag_lps;
+        inverts = (inverts << 1) + context[con].invert;
+
+        //update context state
+        if(flag_lps & toggle_invert(con)) context[con].invert ^= 1;
+        if(flag_lps) context[con].index = next_lps(con);
+        else if(shift) context[con].index = next_mps(con);
+
+        //get next context
+        con = 5 + (con << 1) + ((lps ^ inverts) & 1);
+      }
+
+      //get pixel
+      b = realorder[(lps ^ inverts) & 3];
+      out = (out << 2) + b;
+    }
+
+    //turn pixel data into bitplanes
+    unsigned data = morton_2x8(out);
+    write(data >> 8);
+    write(data >> 0);
+  }
+}
+
+void SPC7110Decomp::mode2(bool init) {
+  static int pixelorder[16], realorder[16];
+  static uint8 bitplanebuffer[16], buffer_index;
+  static uint8 in, val, span;
+  static int out0, out1, inverts, lps, in_count;
+
+  if(init == true) {
+    for(unsigned i = 0; i < 16; i++) pixelorder[i] = i;
+    buffer_index = 0;
+    out0 = out1 = inverts = lps = 0;
+    span = 0xff;
+    val = dataread();
+    in = dataread();
+    in_count = 8;
+    return;
+  }
+
+  while(decomp_buffer_length < (decomp_buffer_size >> 1)) {
+    for(unsigned pixel = 0; pixel < 8; pixel++) {
+      //get first symbol context
+      unsigned a = ((out0 >> (0 * 4)) & 15);
+      unsigned b = ((out0 >> (7 * 4)) & 15);
+      unsigned c = ((out1 >> (0 * 4)) & 15);
+      unsigned con = 0;
+      unsigned refcon = (a == b) ? (b != c) : (b == c) ? 2 : 4 - (a == c);
+
+      //update pixel order
+      unsigned m, n;
+      for(m = 0; m < 16; m++) if(pixelorder[m] == a) break;
+      for(n = m; n >  0; n--) pixelorder[n] = pixelorder[n - 1];
+      pixelorder[0] = a;
+
+      //calculate the real pixel order
+      for(m = 0; m < 16; m++) realorder[m] = pixelorder[m];
+
+      //rotate reference pixel c value to top
+      for(m = 0; m < 16; m++) if(realorder[m] == c) break;
+      for(n = m; n >  0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = c;
+
+      //rotate reference pixel b value to top
+      for(m = 0; m < 16; m++) if(realorder[m] == b) break;
+      for(n = m; n >  0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = b;
+
+      //rotate reference pixel a value to top
+      for(m = 0; m < 16; m++) if(realorder[m] == a) break;
+      for(n = m; n >  0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = a;
+
+      //get 4 symbols
+      for(unsigned bit = 0; bit < 4; bit++) {
+        //get prob
+        unsigned prob = probability(con);
+
+        //get symbol
+        unsigned flag_lps;
+        if(val <= span - prob) { //mps
+          span = span - prob;
+          flag_lps = 0;
+        } else { //lps
+          val = val - (span - (prob - 1));
+          span = prob - 1;
+          flag_lps = 1;
+        }
+
+        //renormalize
+        unsigned shift = 0;
+        while(span < 0x7f) {
+          shift++;
+
+          span = (span << 1) + 1;
+          val = (val << 1) + (in >> 7);
+
+          in <<= 1;
+          if(--in_count == 0) {
+            in = dataread();
+            in_count = 8;
+          }
+        }
+
+        //update processing info
+        lps = (lps << 1) + flag_lps;
+        unsigned invertbit = context[con].invert;
+        inverts = (inverts << 1) + invertbit;
+
+        //update context state
+        if(flag_lps & toggle_invert(con)) context[con].invert ^= 1;
+        if(flag_lps) context[con].index = next_lps(con);
+        else if(shift) context[con].index = next_mps(con);
+
+        //get next context
+        con = mode2_context_table[con][flag_lps ^ invertbit] + (con == 1 ? refcon : 0);
+      }
+
+      //get pixel
+      b = realorder[(lps ^ inverts) & 0x0f];
+      out1 = (out1 << 4) + ((out0 >> 28) & 0x0f);
+      out0 = (out0 << 4) + b;
+    }
+
+    //convert pixel data into bitplanes
+    unsigned data = morton_4x8(out0);
+    write(data >> 24);
+    write(data >> 16);
+    bitplanebuffer[buffer_index++] = data >> 8;
+    bitplanebuffer[buffer_index++] = data >> 0;
+
+    if(buffer_index == 16) {
+      for(unsigned i = 0; i < 16; i++) write(bitplanebuffer[i]);
+      buffer_index = 0;
+    }
+  }
+}
+
+//
+
+const uint8 SPC7110Decomp::evolution_table[53][4] = {
+//{ prob, nextlps, nextmps, toggle invert },
+
+  { 0x5a,  1,  1, 1 },
+  { 0x25,  6,  2, 0 },
+  { 0x11,  8,  3, 0 },
+  { 0x08, 10,  4, 0 },
+  { 0x03, 12,  5, 0 },
+  { 0x01, 15,  5, 0 },
+
+  { 0x5a,  7,  7, 1 },
+  { 0x3f, 19,  8, 0 },
+  { 0x2c, 21,  9, 0 },
+  { 0x20, 22, 10, 0 },
+  { 0x17, 23, 11, 0 },
+  { 0x11, 25, 12, 0 },
+  { 0x0c, 26, 13, 0 },
+  { 0x09, 28, 14, 0 },
+  { 0x07, 29, 15, 0 },
+  { 0x05, 31, 16, 0 },
+  { 0x04, 32, 17, 0 },
+  { 0x03, 34, 18, 0 },
+  { 0x02, 35,  5, 0 },
+
+  { 0x5a, 20, 20, 1 },
+  { 0x48, 39, 21, 0 },
+  { 0x3a, 40, 22, 0 },
+  { 0x2e, 42, 23, 0 },
+  { 0x26, 44, 24, 0 },
+  { 0x1f, 45, 25, 0 },
+  { 0x19, 46, 26, 0 },
+  { 0x15, 25, 27, 0 },
+  { 0x11, 26, 28, 0 },
+  { 0x0e, 26, 29, 0 },
+  { 0x0b, 27, 30, 0 },
+  { 0x09, 28, 31, 0 },
+  { 0x08, 29, 32, 0 },
+  { 0x07, 30, 33, 0 },
+  { 0x05, 31, 34, 0 },
+  { 0x04, 33, 35, 0 },
+  { 0x04, 33, 36, 0 },
+  { 0x03, 34, 37, 0 },
+  { 0x02, 35, 38, 0 },
+  { 0x02, 36,  5, 0 },
+
+  { 0x58, 39, 40, 1 },
+  { 0x4d, 47, 41, 0 },
+  { 0x43, 48, 42, 0 },
+  { 0x3b, 49, 43, 0 },
+  { 0x34, 50, 44, 0 },
+  { 0x2e, 51, 45, 0 },
+  { 0x29, 44, 46, 0 },
+  { 0x25, 45, 24, 0 },
+
+  { 0x56, 47, 48, 1 },
+  { 0x4f, 47, 49, 0 },
+  { 0x47, 48, 50, 0 },
+  { 0x41, 49, 51, 0 },
+  { 0x3c, 50, 52, 0 },
+  { 0x37, 51, 43, 0 },
+};
+
+const uint8 SPC7110Decomp::mode2_context_table[32][2] = {
+//{ next 0, next 1 },
+
+  {  1,  2 },
+
+  {  3,  8 },
+  { 13, 14 },
+
+  { 15, 16 },
+  { 17, 18 },
+  { 19, 20 },
+  { 21, 22 },
+  { 23, 24 },
+  { 25, 26 },
+  { 25, 26 },
+  { 25, 26 },
+  { 25, 26 },
+  { 25, 26 },
+  { 27, 28 },
+  { 29, 30 },
+
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+
+  { 31, 31 },
+};
+
+uint8 SPC7110Decomp::probability  (unsigned n) { return evolution_table[context[n].index][0]; }
+uint8 SPC7110Decomp::next_lps     (unsigned n) { return evolution_table[context[n].index][1]; }
+uint8 SPC7110Decomp::next_mps     (unsigned n) { return evolution_table[context[n].index][2]; }
+bool  SPC7110Decomp::toggle_invert(unsigned n) { return evolution_table[context[n].index][3]; }
+
+unsigned SPC7110Decomp::morton_2x8(unsigned data) {
+  //reverse morton lookup: de-interleave two 8-bit values
+  //15, 13, 11,  9,  7,  5,  3,  1 -> 15- 8
+  //14, 12, 10,  8,  6,  4,  2,  0 ->  7- 0
+  return morton16[0][(data >>  0) & 255] + morton16[1][(data >>  8) & 255];
+}
+
+unsigned SPC7110Decomp::morton_4x8(unsigned data) {
+  //reverse morton lookup: de-interleave four 8-bit values
+  //31, 27, 23, 19, 15, 11,  7,  3 -> 31-24
+  //30, 26, 22, 18, 14, 10,  6,  2 -> 23-16
+  //29, 25, 21, 17, 13,  9,  5,  1 -> 15- 8
+  //28, 24, 20, 16, 12,  8,  4,  0 ->  7- 0
+  return morton32[0][(data >>  0) & 255] + morton32[1][(data >>  8) & 255]
+       + morton32[2][(data >> 16) & 255] + morton32[3][(data >> 24) & 255];
+}
+
+//
+
+void SPC7110Decomp::reset() {
+  //mode 3 is invalid; this is treated as a special case to always return 0x00
+  //set to mode 3 so that reading decomp port before starting first decomp will return 0x00
+  decomp_mode = 3;
+
+  decomp_buffer_rdoffset = 0;
+  decomp_buffer_wroffset = 0;
+  decomp_buffer_length   = 0;
+}
+
+SPC7110Decomp::SPC7110Decomp() {
+  decomp_buffer = new uint8_t[decomp_buffer_size];
+  reset();
+
+  //initialize reverse morton lookup tables
+  for(unsigned i = 0; i < 256; i++) {
+    #define map(x, y) (((i >> x) & 1) << y)
+    //2x8-bit
+    morton16[1][i] = map(7, 15) + map(6,  7) + map(5, 14) + map(4,  6)
+                   + map(3, 13) + map(2,  5) + map(1, 12) + map(0,  4);
+    morton16[0][i] = map(7, 11) + map(6,  3) + map(5, 10) + map(4,  2)
+                   + map(3,  9) + map(2,  1) + map(1,  8) + map(0,  0);
+    //4x8-bit
+    morton32[3][i] = map(7, 31) + map(6, 23) + map(5, 15) + map(4,  7)
+                   + map(3, 30) + map(2, 22) + map(1, 14) + map(0,  6);
+    morton32[2][i] = map(7, 29) + map(6, 21) + map(5, 13) + map(4,  5)
+                   + map(3, 28) + map(2, 20) + map(1, 12) + map(0,  4);
+    morton32[1][i] = map(7, 27) + map(6, 19) + map(5, 11) + map(4,  3)
+                   + map(3, 26) + map(2, 18) + map(1, 10) + map(0,  2);
+    morton32[0][i] = map(7, 25) + map(6, 17) + map(5,  9) + map(4,  1)
+                   + map(3, 24) + map(2, 16) + map(1,  8) + map(0,  0);
+    #undef map
+  }
+}
+
+SPC7110Decomp::~SPC7110Decomp() {
+  delete[] decomp_buffer;
+}
+
+#endif

src/chip/spc7110/decomp.hpp

@@ -0,0 +1,45 @@
+class SPC7110Decomp {
+public:
+  uint8 read();
+  void init(unsigned mode, unsigned offset, unsigned index);
+  void reset();
+
+  SPC7110Decomp();
+  ~SPC7110Decomp();
+
+private:
+  unsigned decomp_mode;
+  unsigned decomp_offset;
+
+  //read() will spool chunks half the size of decomp_buffer_size
+  enum { decomp_buffer_size = 64 }; //must be >= 64, and must be a power of two
+  uint8 *decomp_buffer;
+  unsigned decomp_buffer_rdoffset;
+  unsigned decomp_buffer_wroffset;
+  unsigned decomp_buffer_length;
+
+  void write(uint8 data);
+  uint8 dataread();
+
+  void mode0(bool init);
+  void mode1(bool init);
+  void mode2(bool init);
+
+  static const uint8 evolution_table[53][4];
+  static const uint8 mode2_context_table[32][2];
+
+  struct ContextState {
+    uint8 index;
+    uint8 invert;
+  } context[32];
+
+  uint8 probability(unsigned n);
+  uint8 next_lps(unsigned n);
+  uint8 next_mps(unsigned n);
+  bool toggle_invert(unsigned n);
+
+  unsigned morton16[2][256];
+  unsigned morton32[4][256];
+  unsigned morton_2x8(unsigned data);
+  unsigned morton_4x8(unsigned data);
+};

src/chip/spc7110/spc7110.cpp

@@ -0,0 +1,677 @@
+#include <../base.hpp>
+
+#define SPC7110_CPP
+namespace SNES {
+
+SPC7110 spc7110;
+
+#include "decomp.cpp"
+
+const unsigned SPC7110::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+void SPC7110::init() {}
+
+void SPC7110::enable() {
+  uint16_t limit = (cartridge.has_spc7110rtc() ? 0x4842 : 0x483f);
+  for(uint16_t i = 0x4800; i <= limit; i++) memory::mmio.map(i, *this);
+}
+
+void SPC7110::power() {
+  reset();
+}
+
+void SPC7110::reset() {
+  r4801 = 0x00;
+  r4802 = 0x00;
+  r4803 = 0x00;
+  r4804 = 0x00;
+  r4805 = 0x00;
+  r4806 = 0x00;
+  r4807 = 0x00;
+  r4808 = 0x00;
+  r4809 = 0x00;
+  r480a = 0x00;
+  r480b = 0x00;
+  r480c = 0x00;
+
+  decomp.reset();
+
+  r4811 = 0x00;
+  r4812 = 0x00;
+  r4813 = 0x00;
+  r4814 = 0x00;
+  r4815 = 0x00;
+  r4816 = 0x00;
+  r4817 = 0x00;
+  r4818 = 0x00;
+
+  r481x = 0x00;
+  r4814_latch = false;
+  r4815_latch = false;
+
+  r4820 = 0x00;
+  r4821 = 0x00;
+  r4822 = 0x00;
+  r4823 = 0x00;
+  r4824 = 0x00;
+  r4825 = 0x00;
+  r4826 = 0x00;
+  r4827 = 0x00;
+  r4828 = 0x00;
+  r4829 = 0x00;
+  r482a = 0x00;
+  r482b = 0x00;
+  r482c = 0x00;
+  r482d = 0x00;
+  r482e = 0x00;
+  r482f = 0x00;
+
+  r4830 = 0x00;
+  mmio_write(0x4831, 0);
+  mmio_write(0x4832, 1);
+  mmio_write(0x4833, 2);
+  r4834 = 0x00;
+
+  r4840 = 0x00;
+  r4841 = 0x00;
+  r4842 = 0x00;
+
+  if(cartridge.has_spc7110rtc()) {
+    rtc_state = RTCS_Inactive;
+    rtc_mode  = RTCM_Linear;
+    rtc_index = 0;
+  }
+}
+
+unsigned SPC7110::datarom_addr(unsigned addr) {
+  unsigned size = memory::cartrom.size() - 0x100000;
+  while(addr >= size) addr -= size;
+  return addr + 0x100000;
+}
+
+unsigned SPC7110::data_pointer()   { return r4811 + (r4812 << 8) + (r4813 << 16); }
+unsigned SPC7110::data_adjust()    { return r4814 + (r4815 << 8); }
+unsigned SPC7110::data_increment() { return r4816 + (r4817 << 8); }
+void SPC7110::set_data_pointer(unsigned addr) { r4811 = addr; r4812 = addr >> 8; r4813 = addr >> 16; }
+void SPC7110::set_data_adjust(unsigned addr)  { r4814 = addr; r4815 = addr >> 8; }
+
+void SPC7110::update_time(int offset) {
+  time_t rtc_time
+  = (memory::cartrtc.read(16) <<  0)
+  | (memory::cartrtc.read(17) <<  8)
+  | (memory::cartrtc.read(18) << 16)
+  | (memory::cartrtc.read(19) << 24);
+  time_t current_time = time(0) - offset;
+
+  //sizeof(time_t) is platform-dependent; though memory::cartrtc needs to be platform-agnostic.
+  //yet platforms with 32-bit signed time_t will overflow every ~68 years. handle this by
+  //accounting for overflow at the cost of 1-bit precision (to catch underflow). this will allow
+  //memory::cartrtc timestamp to remain valid for up to ~34 years from the last update, even if
+  //time_t overflows. calculation should be valid regardless of number representation, time_t size,
+  //or whether time_t is signed or unsigned.
+  time_t diff
+  = (current_time >= rtc_time)
+  ? (current_time - rtc_time)
+  : (std::numeric_limits<time_t>::max() - rtc_time + current_time + 1);  //compensate for overflow
+  if(diff > std::numeric_limits<time_t>::max() / 2) diff = 0;            //compensate for underflow
+
+  bool update = true;
+  if(memory::cartrtc.read(13) & 1) update = false;  //do not update if CR0 timer disable flag is set
+  if(memory::cartrtc.read(15) & 3) update = false;  //do not update if CR2 timer disable flags are set
+
+  if(diff > 0 && update == true) {
+    unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
+    unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
+    unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
+    unsigned day     = memory::cartrtc.read( 6) + memory::cartrtc.read( 7) * 10;
+    unsigned month   = memory::cartrtc.read( 8) + memory::cartrtc.read( 9) * 10;
+    unsigned year    = memory::cartrtc.read(10) + memory::cartrtc.read(11) * 10;
+    unsigned weekday = memory::cartrtc.read(12);
+
+    day--;
+    month--;
+    year += (year >= 90) ? 1900 : 2000;  //range = 1990-2089
+
+    second += diff;
+    while(second >= 60) {
+      second -= 60;
+
+      minute++;
+      if(minute < 60) continue;
+      minute = 0;
+
+      hour++;
+      if(hour < 24) continue;
+      hour = 0;
+
+      day++;
+      weekday = (weekday + 1) % 7;
+      unsigned days = months[month % 12];
+      if(days == 28) {
+        bool leapyear = false;
+        if((year % 4) == 0) {
+          leapyear = true;
+          if((year % 100) == 0 && (year % 400) != 0) leapyear = false;
+        }
+        if(leapyear) days++;
+      }
+      if(day < days) continue;
+      day = 0;
+
+      month++;
+      if(month < 12) continue;
+      month = 0;
+
+      year++;
+    }
+
+    day++;
+    month++;
+    year %= 100;
+
+    memory::cartrtc.write( 0, second % 10);
+    memory::cartrtc.write( 1, second / 10);
+    memory::cartrtc.write( 2, minute % 10);
+    memory::cartrtc.write( 3, minute / 10);
+    memory::cartrtc.write( 4, hour % 10);
+    memory::cartrtc.write( 5, hour / 10);
+    memory::cartrtc.write( 6, day % 10);
+    memory::cartrtc.write( 7, day / 10);
+    memory::cartrtc.write( 8, month % 10);
+    memory::cartrtc.write( 9, month / 10);
+    memory::cartrtc.write(10, year % 10);
+    memory::cartrtc.write(11, (year / 10) % 10);
+    memory::cartrtc.write(12, weekday % 7);
+  }
+
+  memory::cartrtc.write(16, current_time >>  0);
+  memory::cartrtc.write(17, current_time >>  8);
+  memory::cartrtc.write(18, current_time >> 16);
+  memory::cartrtc.write(19, current_time >> 24);
+}
+
+uint8 SPC7110::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    //==================
+    //decompression unit
+    //==================
+
+    case 0x4800: {
+      uint16 counter = (r4809 + (r480a << 8));
+      counter--;
+      r4809 = counter;
+      r480a = counter >> 8;
+      return decomp.read();
+    }
+    case 0x4801: return r4801;
+    case 0x4802: return r4802;
+    case 0x4803: return r4803;
+    case 0x4804: return r4804;
+    case 0x4805: return r4805;
+    case 0x4806: return r4806;
+    case 0x4807: return r4807;
+    case 0x4808: return r4808;
+    case 0x4809: return r4809;
+    case 0x480a: return r480a;
+    case 0x480b: return r480b;
+    case 0x480c: {
+      uint8 status = r480c;
+      r480c &= 0x7f;
+      return status;
+    }
+
+    //==============
+    //data port unit
+    //==============
+
+    case 0x4810: {
+      if(r481x != 0x07) return 0x00;
+
+      unsigned addr = data_pointer();
+      unsigned adjust = data_adjust();
+      if(r4818 & 8) adjust = (int16)adjust;  //16-bit sign extend
+
+      unsigned adjustaddr = addr;
+      if(r4818 & 2) {
+        adjustaddr += adjust;
+        set_data_adjust(adjust + 1);
+      }
+
+      uint8 data = memory::cartrom.read(datarom_addr(adjustaddr));
+      if(!(r4818 & 2)) {
+        unsigned increment = (r4818 & 1) ? data_increment() : 1;
+        if(r4818 & 4) increment = (int16)increment;  //16-bit sign extend
+
+        if((r4818 & 16) == 0) {
+          set_data_pointer(addr + increment);
+        } else {
+          set_data_adjust(adjust + increment);
+        }
+      }
+
+      return data;
+    }
+    case 0x4811: return r4811;
+    case 0x4812: return r4812;
+    case 0x4813: return r4813;
+    case 0x4814: return r4814;
+    case 0x4815: return r4815;
+    case 0x4816: return r4816;
+    case 0x4817: return r4817;
+    case 0x4818: return r4818;
+    case 0x481a: {
+      if(r481x != 0x07) return 0x00;
+
+      unsigned addr = data_pointer();
+      unsigned adjust = data_adjust();
+      if(r4818 & 8) adjust = (int16)adjust;  //16-bit sign extend
+
+      uint8 data = memory::cartrom.read(datarom_addr(addr + adjust));
+      if((r4818 & 0x60) == 0x60) {
+        if((r4818 & 16) == 0) {
+          set_data_pointer(addr + adjust);
+        } else {
+          set_data_adjust(adjust + adjust);
+        }
+      }
+
+      return data;
+    }
+
+    //=========
+    //math unit
+    //=========
+
+    case 0x4820: return r4820;
+    case 0x4821: return r4821;
+    case 0x4822: return r4822;
+    case 0x4823: return r4823;
+    case 0x4824: return r4824;
+    case 0x4825: return r4825;
+    case 0x4826: return r4826;
+    case 0x4827: return r4827;
+    case 0x4828: return r4828;
+    case 0x4829: return r4829;
+    case 0x482a: return r482a;
+    case 0x482b: return r482b;
+    case 0x482c: return r482c;
+    case 0x482d: return r482d;
+    case 0x482e: return r482e;
+    case 0x482f: {
+      uint8 status = r482f;
+      r482f &= 0x7f;
+      return status;
+    }
+
+    //===================
+    //memory mapping unit
+    //===================
+
+    case 0x4830: return r4830;
+    case 0x4831: return r4831;
+    case 0x4832: return r4832;
+    case 0x4833: return r4833;
+    case 0x4834: return r4834;
+
+    //====================
+    //real-time clock unit
+    //====================
+
+    case 0x4840: return r4840;
+    case 0x4841: {
+      if(rtc_state == RTCS_Inactive || rtc_state == RTCS_ModeSelect) return 0x00;
+
+      r4842 = 0x80;
+      uint8 data = memory::cartrtc.read(rtc_index);
+      rtc_index = (rtc_index + 1) & 15;
+      return data;
+    }
+    case 0x4842: {
+      uint8 status = r4842;
+      r4842 &= 0x7f;
+      return status;
+    }
+  }
+
+  return cpu.regs.mdr;
+}
+
+void SPC7110::mmio_write(unsigned addr, uint8 data) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    //==================
+    //decompression unit
+    //==================
+
+    case 0x4801: r4801 = data; break;
+    case 0x4802: r4802 = data; break;
+    case 0x4803: r4803 = data; break;
+    case 0x4804: r4804 = data; break;
+    case 0x4805: r4805 = data; break;
+    case 0x4806: {
+      r4806 = data;
+
+      unsigned table   = (r4801 + (r4802 << 8) + (r4803 << 16));
+      unsigned index   = (r4804 << 2);
+      unsigned length  = (r4809 + (r480a << 8));
+      unsigned addr    = datarom_addr(table + index);
+      unsigned mode    = (memory::cartrom.read(addr + 0));
+      unsigned offset  = (memory::cartrom.read(addr + 1) << 16)
+                       + (memory::cartrom.read(addr + 2) <<  8)
+                       + (memory::cartrom.read(addr + 3) <<  0);
+
+      decomp.init(mode, offset, (r4805 + (r4806 << 8)) << mode);
+      r480c = 0x80;
+    } break;
+
+    case 0x4807: r4807 = data; break;
+    case 0x4808: r4808 = data; break;
+    case 0x4809: r4809 = data; break;
+    case 0x480a: r480a = data; break;
+    case 0x480b: r480b = data; break;
+
+    //==============
+    //data port unit
+    //==============
+
+    case 0x4811: r4811 = data; r481x |= 0x01; break;
+    case 0x4812: r4812 = data; r481x |= 0x02; break;
+    case 0x4813: r4813 = data; r481x |= 0x04; break;
+    case 0x4814: {
+      r4814 = data;
+      r4814_latch = true;
+      if(!r4815_latch) break;
+      if(!(r4818 & 2)) break;
+      if(r4818 & 0x10) break;
+
+      if((r4818 & 0x60) == 0x20) {
+        unsigned increment = data_adjust() & 0xff;
+        if(r4818 & 8) increment = (int8)increment;  //8-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      } else if((r4818 & 0x60) == 0x40) {
+        unsigned increment = data_adjust();
+        if(r4818 & 8) increment = (int16)increment;  //16-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      }
+    } break;
+    case 0x4815: {
+      r4815 = data;
+      r4815_latch = true;
+      if(!r4814_latch) break;
+      if(!(r4818 & 2)) break;
+      if(r4818 & 0x10) break;
+
+      if((r4818 & 0x60) == 0x20) {
+        unsigned increment = data_adjust() & 0xff;
+        if(r4818 & 8) increment = (int8)increment;  //8-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      } else if((r4818 & 0x60) == 0x40) {
+        unsigned increment = data_adjust();
+        if(r4818 & 8) increment = (int16)increment;  //16-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      }
+    } break;
+    case 0x4816: r4816 = data; break;
+    case 0x4817: r4817 = data; break;
+    case 0x4818: {
+      if(r481x != 0x07) break;
+
+      r4818 = data;
+      r4814_latch = r4815_latch = false;
+    } break;
+
+    //=========
+    //math unit
+    //=========
+
+    case 0x4820: r4820 = data; break;
+    case 0x4821: r4821 = data; break;
+    case 0x4822: r4822 = data; break;
+    case 0x4823: r4823 = data; break;
+    case 0x4824: r4824 = data; break;
+    case 0x4825: {
+      r4825 = data;
+
+      if(r482e & 1) {
+        //signed 16-bit x 16-bit multiplication
+        int16 r0 = (int16)(r4824 + (r4825 << 8));
+        int16 r1 = (int16)(r4820 + (r4821 << 8));
+
+        signed result = r0 * r1;
+        r4828 = result;
+        r4829 = result >> 8;
+        r482a = result >> 16;
+        r482b = result >> 24;
+      } else {
+        //unsigned 16-bit x 16-bit multiplication
+        uint16 r0 = (uint16)(r4824 + (r4825 << 8));
+        uint16 r1 = (uint16)(r4820 + (r4821 << 8));
+
+        unsigned result = r0 * r1;
+        r4828 = result;
+        r4829 = result >> 8;
+        r482a = result >> 16;
+        r482b = result >> 24;
+      }
+
+      r482f = 0x80;
+    } break;
+    case 0x4826: r4826 = data; break;
+    case 0x4827: {
+      r4827 = data;
+
+      if(r482e & 1) {
+        //signed 32-bit x 16-bit division
+        int32 dividend = (int32)(r4820 + (r4821 << 8) + (r4822 << 16) + (r4823 << 24));
+        int16 divisor  = (int16)(r4826 + (r4827 << 8));
+
+        int32 quotient;
+        int16 remainder;
+
+        if(divisor) {
+          quotient  = (int32)(dividend / divisor);
+          remainder = (int32)(dividend % divisor);
+        } else {
+          //illegal division by zero
+          quotient  = 0;
+          remainder = dividend & 0xffff;
+        }
+
+        r4828 = quotient;
+        r4829 = quotient >> 8;
+        r482a = quotient >> 16;
+        r482b = quotient >> 24;
+
+        r482c = remainder;
+        r482d = remainder >> 8;
+      } else {
+        //unsigned 32-bit x 16-bit division
+        uint32 dividend = (uint32)(r4820 + (r4821 << 8) + (r4822 << 16) + (r4823 << 24));
+        uint16 divisor  = (uint16)(r4826 + (r4827 << 8));
+
+        uint32 quotient;
+        uint16 remainder;
+
+        if(divisor) {
+          quotient  = (uint32)(dividend / divisor);
+          remainder = (uint16)(dividend % divisor);
+        } else {
+          //illegal division by zero
+          quotient  = 0;
+          remainder = dividend & 0xffff;
+        }
+
+        r4828 = quotient;
+        r4829 = quotient >> 8;
+        r482a = quotient >> 16;
+        r482b = quotient >> 24;
+
+        r482c = remainder;
+        r482d = remainder >> 8;
+      }
+
+      r482f = 0x80;
+    } break;
+
+    case 0x482e: {
+      //reset math unit
+      r4820 = r4821 = r4822 = r4823 = 0;
+      r4824 = r4825 = r4826 = r4827 = 0;
+      r4828 = r4829 = r482a = r482b = 0;
+      r482c = r482d = 0;
+
+      r482e = data;
+    } break;
+
+    //===================
+    //memory mapping unit
+    //===================
+
+    case 0x4830: r4830 = data; break;
+
+    case 0x4831: {
+      r4831 = data;
+      dx_offset = datarom_addr((data & 7) * 0x100000);
+    } break;
+
+    case 0x4832: {
+      r4832 = data;
+      ex_offset = datarom_addr((data & 7) * 0x100000);
+    } break;
+
+    case 0x4833: {
+      r4833 = data;
+      fx_offset = datarom_addr((data & 7) * 0x100000);
+    } break;
+
+    case 0x4834: r4834 = data; break;
+
+    //====================
+    //real-time clock unit
+    //====================
+
+    case 0x4840: {
+      r4840 = data;
+      if(!(r4840 & 1)) {
+        //disable RTC
+        rtc_state = RTCS_Inactive;
+        update_time();
+      } else {
+        //enable RTC
+        r4842 = 0x80;
+        rtc_state = RTCS_ModeSelect;
+      }
+    } break;
+
+    case 0x4841: {
+      r4841 = data;
+
+      switch(rtc_state) {
+        case RTCS_ModeSelect: {
+          if(data == RTCM_Linear || data == RTCM_Indexed) {
+            r4842 = 0x80;
+            rtc_state = RTCS_IndexSelect;
+            rtc_mode  = (RTC_Mode)data;
+            rtc_index = 0;
+          }
+        } break;
+
+        case RTCS_IndexSelect: {
+          r4842 = 0x80;
+          rtc_index = data & 15;
+          if(rtc_mode == RTCM_Linear) rtc_state = RTCS_Write;
+        } break;
+
+        case RTCS_Write: {
+          r4842 = 0x80;
+
+          //control register 0
+          if(rtc_index == 13) {
+            //increment second counter
+            if(data & 2) update_time(+1);
+
+            //round minute counter
+            if(data & 8) {
+              update_time();
+
+              unsigned second = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
+              //clear seconds
+              memory::cartrtc.write(0, 0);
+              memory::cartrtc.write(1, 0);
+
+              if(second >= 30) update_time(+60);
+            }
+          }
+
+          //control register 2
+          if(rtc_index == 15) {
+            //disable timer and clear second counter
+            if((data & 1) && !(memory::cartrtc.read(15) & 1)) {
+              update_time();
+
+              //clear seconds
+              memory::cartrtc.write(0, 0);
+              memory::cartrtc.write(1, 0);
+            }
+
+            //disable timer
+            if((data & 2) && !(memory::cartrtc.read(15) & 2)) {
+              update_time();
+            }
+          }
+
+          memory::cartrtc.write(rtc_index, data & 15);
+          rtc_index = (rtc_index + 1) & 15;
+        } break;
+      } //switch(rtc_state)
+    } break;
+  }
+}
+
+uint8 SPC7110::read(unsigned addr) {
+  //$[00-0f|80-8f]:[8000-ffff], $[c0-cf]:[0000-ffff] mapped directly to memory::cartrom
+
+  if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
+    //$[00|30]:[6000-7fff]
+    return memory::cartram.read(addr & 0x1fff);
+  }
+
+  if((addr & 0xff0000) == 0x500000) {
+    //$[50]:[0000-ffff]
+    return mmio_read(0x4800);
+  }
+
+  if((addr & 0xf00000) == 0xd00000) {
+    //$[d0-df]:[0000-ffff]
+    return memory::cartrom.read(dx_offset + (addr & 0x0fffff));
+  }
+
+  if((addr & 0xf00000) == 0xe00000) {
+    //$[e0-ef]:[0000-ffff]
+    return memory::cartrom.read(ex_offset + (addr & 0x0fffff));
+  }
+
+  if((addr & 0xf00000) == 0xf00000) {
+    //$[f0-ff]:[0000-ffff]
+    return memory::cartrom.read(fx_offset + (addr & 0x0fffff));
+  }
+
+  return cpu.regs.mdr;
+}
+
+void SPC7110::write(unsigned addr, uint8 data) {
+  if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
+    //$[00|30]:[6000-7fff]
+    if(r4830 & 0x80) memory::cartram.write(addr & 0x1fff, data);
+    return;
+  }
+}
+
+SPC7110::SPC7110() {
+}
+
+};
+

src/chip/spc7110/spc7110.hpp

@@ -0,0 +1,133 @@
+/*****
+ * SPC7110 emulator - version 0.03 (2008-08-10)
+ * Copyright (c) 2008, byuu and neviksti
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * The software is provided "as is" and the author disclaims all warranties
+ * with regard to this software including all implied warranties of
+ * merchantibility and fitness, in no event shall the author be liable for
+ * any special, direct, indirect, or consequential damages or any damages
+ * whatsoever resulting from loss of use, data or profits, whether in an
+ * action of contract, negligence or other tortious action, arising out of
+ * or in connection with the use or performance of this software.
+ *****/
+
+#include "decomp.hpp"
+
+class SPC7110 : public MMIO, public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  unsigned datarom_addr(unsigned addr);
+
+  unsigned data_pointer();
+  unsigned data_adjust();
+  unsigned data_increment();
+  void set_data_pointer(unsigned addr);
+  void set_data_adjust(unsigned addr);
+
+  void update_time(int offset = 0);
+  time_t create_time();
+
+  uint8 mmio_read (unsigned addr);
+  void  mmio_write(unsigned addr, uint8 data);
+
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
+
+  //spc7110decomp
+  void decomp_init();
+  uint8 decomp_read();
+
+  SPC7110();
+
+private:
+  //==================
+  //decompression unit
+  //==================
+  uint8 r4801; //compression table low
+  uint8 r4802; //compression table high
+  uint8 r4803; //compression table bank
+  uint8 r4804; //compression table index
+  uint8 r4805; //decompression buffer index low
+  uint8 r4806; //decompression buffer index high
+  uint8 r4807; //???
+  uint8 r4808; //???
+  uint8 r4809; //compression length low
+  uint8 r480a; //compression length high
+  uint8 r480b; //decompression control register
+  uint8 r480c; //decompression status
+
+  SPC7110Decomp decomp;
+
+  //==============
+  //data port unit
+  //==============
+  uint8 r4811; //data pointer low
+  uint8 r4812; //data pointer high
+  uint8 r4813; //data pointer bank
+  uint8 r4814; //data adjust low
+  uint8 r4815; //data adjust high
+  uint8 r4816; //data increment low
+  uint8 r4817; //data increment high
+  uint8 r4818; //data port control register
+
+  uint8 r481x;
+
+  bool r4814_latch;
+  bool r4815_latch;
+
+  //=========
+  //math unit
+  //=========
+  uint8 r4820; //16-bit multiplicand B0, 32-bit dividend B0
+  uint8 r4821; //16-bit multiplicand B1, 32-bit dividend B1
+  uint8 r4822; //32-bit dividend B2
+  uint8 r4823; //32-bit dividend B3
+  uint8 r4824; //16-bit multiplier B0
+  uint8 r4825; //16-bit multiplier B1
+  uint8 r4826; //16-bit divisor B0
+  uint8 r4827; //16-bit divisor B1
+  uint8 r4828; //32-bit product B0, 32-bit quotient B0
+  uint8 r4829; //32-bit product B1, 32-bit quotient B1
+  uint8 r482a; //32-bit product B2, 32-bit quotient B2
+  uint8 r482b; //32-bit product B3, 32-bit quotient B3
+  uint8 r482c; //16-bit remainder B0
+  uint8 r482d; //16-bit remainder B1
+  uint8 r482e; //math control register
+  uint8 r482f; //math status
+
+  //===================
+  //memory mapping unit
+  //===================
+  uint8 r4830; //SRAM write enable
+  uint8 r4831; //$[d0-df]:[0000-ffff] mapping
+  uint8 r4832; //$[e0-ef]:[0000-ffff] mapping
+  uint8 r4833; //$[f0-ff]:[0000-ffff] mapping
+  uint8 r4834; //???
+
+  unsigned dx_offset;
+  unsigned ex_offset;
+  unsigned fx_offset;
+
+  //====================
+  //real-time clock unit
+  //====================
+  uint8 r4840; //RTC latch
+  uint8 r4841; //RTC index/data port
+  uint8 r4842; //RTC status
+
+  enum RTC_State { RTCS_Inactive, RTCS_ModeSelect, RTCS_IndexSelect, RTCS_Write } rtc_state;
+  enum RTC_Mode  { RTCM_Linear = 0x03, RTCM_Indexed = 0x0c } rtc_mode;
+  unsigned rtc_index;
+
+  static const unsigned months[12];
+};
+
+extern SPC7110 spc7110;

src/chip/srtc/srtc.cpp

@@ -1,189 +1,232 @@
-/*
-  S-RTC chip emulation
-  Used by Hudson Soft in Dai Kaijuu Monogatari II and Far East of Eden Zero.
-  Currently, only the former is supported by bsnes.
-
-  Original S-RTC emulation code via John Weidman/SNES9x
-  Rewritten for compatibility with bsnes via byuu
-
-  The S-RTC is a real-time clock chip that was added to the above two carts
-  to allow the games to maintain the current time, even when the game was not
-  powered on. Thus allowing special events at certain times, and on certain
-  dates. Hudson Soft called this the PLG (Player's Life Gameplay System).
-
-  This chip is a special case to the term 'emulation' itself.
-  There are a few different ways to go about emulating this chip, and each
-  result in a different style of emulation.
-
-  The first is to simply return the current PC system time when the S-RTC is
-  read from. This emulates the original S-RTC in the sense that it always
-  returns the true current time, ignoring the speed that the SNES itself is
-  running at. The downside to this method is that you lose the ability to set
-  the time to whatever you choose inside the game itself. It will always return
-  the true time, regardless. This can be overcome by changing the PC system time,
-  which actually adds a greater degree of control over event timing, very useful
-  for emulation. It also has a timeshifting flaw discussed below.
-
-  The second is to run the S-RTC relative to the SNES speed. This means that
-  if the emulator is sped up (via fast forward key, frameskipping, etc), or
-  slowed down (via slowdown key, system bottlenecking, etc); the time increments
-  slower, thus ~60 frames on the SNES equal one second. Without this, timeshifting
-  will occur between the S-RTC and the real SNES.
-
-  The third and final method is to save a copy of the local system time when the
-  S-RTC is initially set, and compare the current system time against this value
-  when setting the S-RTC time. This overcomes the first methods' shortcoming of
-  not allowing the player to set the time in-game, however a new problem arises.
-  You now have to save the time when the RTC was initially set to both savestates
-  and to save-game data. This would require an extra file, or the breaking of
-  perhaps the only standard format (.srm savegame backups) in the entire SNES
-  emulation scene. You also give up the control of being able to override the
-  RTC clock at will via the PC system time outside of emulation.
-  The first method has another advantage over the third: Dai Kaijuu Monogatari II
-  only allows dates in the range of the years 1996-2199. The first method gets
-  around this limitation. But who knows, maybe it will break something in the
-  game if the date exceeds 2199... I guess we'll worry about that in two hundred
-  years from now.
-
-  For my implementation, I chose to go with the first method. Both for simplicity
-  and because I did not wish to create a new method for saving the system time
-  whenever the RTC is set.
-*/
-
-#include "../../base.h"
-
-void SRTC::set_time() {
-time_t rawtime;
-tm *t;
-  ::time(&rawtime);
-  t = localtime(&rawtime);
-
-//see srtc.h for format of srtc.data[]
-  srtc.data[0]  = t->tm_sec % 10;
-  srtc.data[1]  = t->tm_sec / 10;
-  srtc.data[2]  = t->tm_min % 10;
-  srtc.data[3]  = t->tm_min / 10;
-  srtc.data[4]  = t->tm_hour % 10;
-  srtc.data[5]  = t->tm_hour / 10;
-  srtc.data[6]  = t->tm_mday % 10;
-  srtc.data[7]  = t->tm_mday / 10;
-  srtc.data[8]  = t->tm_mon + 1;
-  srtc.data[9]  = t->tm_year % 10;
-  srtc.data[10] = (t->tm_year / 10) % 10;
-  srtc.data[11] = 9 + (t->tm_year / 100);
-  srtc.data[12] = t->tm_wday;
-}
-
-void SRTC::init() {}
-
-void SRTC::enable() {
-  memory::mmio.map(0x2800, *this);
-  memory::mmio.map(0x2801, *this);
-}
-
-void SRTC::power() {
-  memset(&srtc, 0, sizeof(srtc));
-  reset();
-}
-
-void SRTC::reset() {
-  srtc.index = -1;
-  srtc.mode  = SRTC_READ;
-}
-
-uint8 SRTC::mmio_read(uint addr) {
-  switch(addr & 0xffff) {
-
-  case 0x2800: {
-    if(srtc.mode == SRTC_READ) {
-      if(srtc.index < 0) {
-        set_time();
-        srtc.index++;
-        return 0x0f; //send start message
-      } else if(srtc.index > MAX_SRTC_INDEX) {
-        srtc.index = -1;
-        return 0x0f; //send finished message
-      } else {
-        return srtc.data[srtc.index++];
-      }
-    } else {
-      return 0x00;
-    }
-  } break;
-
-  case 0x2801: {
-  } break;
-
-  }
-
-  return cpu.regs.mdr;
-}
-
-//Please see notes above about the implementation of the S-RTC
-//Writes are stored the srtc.data[] array, but they are ignored
-//as reads will refresh the data array with the current system
-//time. The write method is only here for the sake of faux
-//emulation of the real hardware.
-void SRTC::mmio_write(uint addr, uint8 data) {
-  switch(addr & 0xffff) {
-
-  case 0x2800: {
-  } break;
-
-  case 0x2801: {
-    data &= 0x0f; //only the low four bits are used
-
-    if(data >= 0x0d) {
-      switch(data) {
-      case 0x0d:
-        srtc.mode  = SRTC_READ;
-        srtc.index = -1;
-        break;
-      case 0x0e:
-        srtc.mode = SRTC_COMMAND;
-        break;
-      case 0x0f:
-      //unknown behaviour
-        break;
-      }
-      return;
-    }
-
-    if(srtc.mode == SRTC_WRITE) {
-      if(srtc.index >= 0 && srtc.index < MAX_SRTC_INDEX) {
-        srtc.data[srtc.index++] = data;
-
-        if(srtc.index == MAX_SRTC_INDEX) {
-        //all S-RTC data has been loaded by program
-          srtc.data[srtc.index++] = 0x00; //day_of_week
-        }
-      }
-    } else if(srtc.mode == SRTC_COMMAND) {
-      switch(data) {
-      case SRTC_COMMAND_CLEAR:
-        memset(srtc.data, 0, MAX_SRTC_INDEX + 1);
-        srtc.index = -1;
-        srtc.mode  = SRTC_READY;
-        break;
-      case SRTC_COMMAND_WRITE:
-        srtc.index = 0;
-        srtc.mode  = SRTC_WRITE;
-        break;
-      default:
-      //unknown behaviour
-        srtc.mode  = SRTC_READY;
-        break;
-      }
-    } else {
-      if(srtc.mode == SRTC_READ) {
-      //ignore writes while in read mode
-      } else if(srtc.mode == SRTC_READY) {
-      //unknown behaviour
-      }
-    }
-  } break;
-
-  }
-}
-
-SRTC::SRTC() {}
+#include <../base.hpp>
+
+#define SRTC_CPP
+namespace SNES {
+
+SRTC srtc;
+
+const unsigned SRTC::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+void SRTC::init() {
+}
+
+void SRTC::enable() {
+  memory::mmio.map(0x2800, *this);
+  memory::mmio.map(0x2801, *this);
+}
+
+void SRTC::power() {
+  reset();
+}
+
+void SRTC::reset() {
+  rtc_mode = RTCM_Read;
+  rtc_index = -1;
+  update_time();
+}
+
+void SRTC::update_time() {
+  time_t rtc_time
+  = (memory::cartrtc.read(16) <<  0)
+  | (memory::cartrtc.read(17) <<  8)
+  | (memory::cartrtc.read(18) << 16)
+  | (memory::cartrtc.read(19) << 24);
+  time_t current_time = time(0);
+
+  //sizeof(time_t) is platform-dependent; though memory::cartrtc needs to be platform-agnostic.
+  //yet platforms with 32-bit signed time_t will overflow every ~68 years. handle this by
+  //accounting for overflow at the cost of 1-bit precision (to catch underflow). this will allow
+  //memory::cartrtc timestamp to remain valid for up to ~34 years from the last update, even if
+  //time_t overflows. calculation should be valid regardless of number representation, time_t size,
+  //or whether time_t is signed or unsigned.
+  time_t diff
+  = (current_time >= rtc_time)
+  ? (current_time - rtc_time)
+  : (std::numeric_limits<time_t>::max() - rtc_time + current_time + 1);  //compensate for overflow
+  if(diff > std::numeric_limits<time_t>::max() / 2) diff = 0;            //compensate for underflow
+
+  if(diff > 0) {
+    unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
+    unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
+    unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
+    unsigned day     = memory::cartrtc.read( 6) + memory::cartrtc.read( 7) * 10;
+    unsigned month   = memory::cartrtc.read( 8);
+    unsigned year    = memory::cartrtc.read( 9) + memory::cartrtc.read(10) * 10 + memory::cartrtc.read(11) * 100;
+    unsigned weekday = memory::cartrtc.read(12);
+
+    day--;
+    month--;
+    year += 1000;
+
+    second += diff;
+    while(second >= 60) {
+      second -= 60;
+
+      minute++;
+      if(minute < 60) continue;
+      minute = 0;
+
+      hour++;
+      if(hour < 24) continue;
+      hour = 0;
+
+      day++;
+      weekday = (weekday + 1) % 7;
+      unsigned days = months[month % 12];
+      if(days == 28) {
+        bool leapyear = false;
+        if((year % 4) == 0) {
+          leapyear = true;
+          if((year % 100) == 0 && (year % 400) != 0) leapyear = false;
+        }
+        if(leapyear) days++;
+      }
+      if(day < days) continue;
+      day = 0;
+
+      month++;
+      if(month < 12) continue;
+      month = 0;
+
+      year++;
+    }
+
+    day++;
+    month++;
+    year -= 1000;
+
+    memory::cartrtc.write( 0, second % 10);
+    memory::cartrtc.write( 1, second / 10);
+    memory::cartrtc.write( 2, minute % 10);
+    memory::cartrtc.write( 3, minute / 10);
+    memory::cartrtc.write( 4, hour % 10);
+    memory::cartrtc.write( 5, hour / 10);
+    memory::cartrtc.write( 6, day % 10);
+    memory::cartrtc.write( 7, day / 10);
+    memory::cartrtc.write( 8, month);
+    memory::cartrtc.write( 9, year % 10);
+    memory::cartrtc.write(10, (year / 10) % 10);
+    memory::cartrtc.write(11, year / 100);
+    memory::cartrtc.write(12, weekday % 7);
+  }
+
+  memory::cartrtc.write(16, current_time >>  0);
+  memory::cartrtc.write(17, current_time >>  8);
+  memory::cartrtc.write(18, current_time >> 16);
+  memory::cartrtc.write(19, current_time >> 24);
+}
+
+//returns day of week for specified date
+//eg 0 = Sunday, 1 = Monday, ... 6 = Saturday
+//usage: weekday(2008, 1, 1) returns weekday of January 1st, 2008
+unsigned SRTC::weekday(unsigned year, unsigned month, unsigned day) {
+  unsigned y = 1900, m = 1;  //epoch is 1900-01-01
+  unsigned sum = 0;          //number of days passed since epoch
+
+  year = max(1900, year);
+  month = max(1, min(12, month));
+  day = max(1, min(31, day));
+
+  while(y < year) {
+    bool leapyear = false;
+    if((y % 4) == 0) {
+      leapyear = true;
+      if((y % 100) == 0 && (y % 400) != 0) leapyear = false;
+    }
+    sum += leapyear ? 366 : 365;
+    y++;
+  }
+
+  while(m < month) {
+    unsigned days = months[m - 1];
+    if(days == 28) {
+      bool leapyear = false;
+      if((y % 4) == 0) {
+        leapyear = true;
+        if((y % 100) == 0 && (y % 400) != 0) leapyear = false;
+      }
+      if(leapyear) days++;
+    }
+    sum += days;
+    m++;
+  }
+
+  sum += day - 1;
+  return (sum + 1) % 7;  //1900-01-01 was a Monday
+}
+
+uint8 SRTC::mmio_read(unsigned addr) {
+  addr &= 0xffff;
+
+  if(addr == 0x2800) {
+    if(rtc_mode != RTCM_Read) return 0x00;
+
+    if(rtc_index < 0) {
+      update_time();
+      rtc_index++;
+      return 0x0f;
+    } else if(rtc_index > 12) {
+      rtc_index = -1;
+      return 0x0f;
+    } else {
+      return memory::cartrtc.read(rtc_index++);
+    }
+  }
+
+  return cpu.regs.mdr;
+}
+
+void SRTC::mmio_write(unsigned addr, uint8 data) {
+  addr &= 0xffff;
+
+  if(addr == 0x2801) {
+    data &= 0x0f;  //only the low four bits are used
+
+    if(data == 0x0d) {
+      rtc_mode = RTCM_Read;
+      rtc_index = -1;
+      return;
+    }
+
+    if(data == 0x0e) {
+      rtc_mode = RTCM_Command;
+      return;
+    }
+
+    if(data == 0x0f) return;  //unknown behavior
+
+    if(rtc_mode == RTCM_Write) {
+      if(rtc_index >= 0 && rtc_index < 12) {
+        memory::cartrtc.write(rtc_index++, data);
+
+        if(rtc_index == 12) {
+          //day of week is automatically calculated and written
+          unsigned day   = memory::cartrtc.read( 6) + memory::cartrtc.read( 7) * 10;
+          unsigned month = memory::cartrtc.read( 8);
+          unsigned year  = memory::cartrtc.read( 9) + memory::cartrtc.read(10) * 10 + memory::cartrtc.read(11) * 100;
+          year += 1000;
+
+          memory::cartrtc.write(rtc_index++, weekday(year, month, day));
+        }
+      }
+    } else if(rtc_mode == RTCM_Command) {
+      if(data == 0) {
+        rtc_mode = RTCM_Write;
+        rtc_index = 0;
+      } else if(data == 4) {
+        rtc_mode = RTCM_Ready;
+        rtc_index = -1;
+        for(unsigned i = 0; i < 13; i++) memory::cartrtc.write(i, 0);
+      } else {
+        //unknown behavior
+        rtc_mode = RTCM_Ready;
+      }
+    }
+  }
+}
+
+SRTC::SRTC() {
+}
+
+};
+

src/chip/srtc/srtc.h

@@ -1,52 +0,0 @@
-class SRTC : public MMIO {
-public:
-enum { MAX_SRTC_INDEX = 0x0c };
-
-enum {
-  SRTC_READ = 0,
-  SRTC_WRITE,
-  SRTC_COMMAND,
-  SRTC_READY
-};
-
-enum {
-  SRTC_COMMAND_WRITE = 0,
-  SRTC_COMMAND_CLEAR = 4
-};
-
-/******************************
-[srtc.data structure]
-Index  Description   Range
------  -----------   -----
-    0  Seconds low   0-9
-    1  Seconds high  0-5
-    2  Minutes low   0-9
-    3  Minutes high  0-5
-    4  Hour low      0-9
-    5  Hour high     0-2
-    6  Day low       0-9
-    7  Day high      0-3
-    8  Month         1-12
-    9  Year ones     0-9
-   10  Year tens     0-9
-   11  Year hundreds 9-11 (9=19xx, 10=20xx, 11=21xx)
-   12  Day of week   0-6  (0=Sunday, ...)
-******************************/
-struct {
-  int8  index;
-  uint8 mode;
-  uint8 data[MAX_SRTC_INDEX + 1];
-} srtc;
-  void  set_time();
-  void  init();
-  void  enable();
-  void  power();
-  void  reset();
-
-  uint8 mmio_read (uint addr);
-  void  mmio_write(uint addr, uint8 data);
-
-  SRTC();
-};
-
-extern SRTC srtc;

src/chip/srtc/srtc.hpp

@@ -0,0 +1,22 @@
+class SRTC : public MMIO {
+public:
+  void update_time();
+  unsigned weekday(unsigned year, unsigned month, unsigned day);
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read (unsigned addr);
+  void  mmio_write(unsigned addr, uint8 data);
+
+  SRTC();
+
+private:
+  static const unsigned months[12];
+  enum RTC_Mode { RTCM_Ready, RTCM_Command, RTCM_Read, RTCM_Write } rtc_mode;
+  signed rtc_index;
+};
+
+extern SRTC srtc;

src/chip/st010/st010.cpp

@@ -1,7 +1,11 @@
-#include "../../base.h"
+#include <../base.hpp>
+
 #define ST010_CPP
+namespace SNES {
+
+ST010 st010;
 
-#include "st010_data.h"
+#include "st010_data.hpp"
 #include "st010_op.cpp"
 
 int16 ST010::sin(int16 theta) {
@@ -62,11 +66,11 @@ void ST010::reset() {
 
 //
 
-uint8 ST010::read(uint addr) {
+uint8 ST010::read(unsigned addr) {
   return readb(addr);
 }
 
-void ST010::write(uint addr, uint8 data) {
+void ST010::write(unsigned addr, uint8 data) {
   writeb(addr, data);
 
   if((addr & 0xfff) == 0x0021 && (data & 0x80)) {
@@ -84,3 +88,5 @@ void ST010::write(uint addr, uint8 data) {
     ram[0x0021] &= ~0x80;
   }
 }
+};
+

src/chip/st010/st010.hpp

@@ -5,8 +5,8 @@ public:
   void power();
   void reset();
 
-  uint8 read (uint addr);
-  void  write(uint addr, uint8 data);
+  uint8 read (unsigned addr);
+  void  write(unsigned addr, uint8 data);
 
 private:
   uint8 ram[0x1000];

src/chip/st010/st010_op.cpp

@@ -258,4 +258,4 @@ int16 x1, y1;
   writew(0x0012, y1);
 }
 
-#endif //ifdef ST010_CPP
+#endif

src/clean.bat

@@ -1 +1 @@
-@make platform=win compiler=mingw32-gcc clean
+@mingw32-make clean

src/clean.sh

@@ -1 +0,0 @@
-make platform=x compiler=gcc clean

src/config/config.cpp

@@ -1,130 +0,0 @@
-namespace config {
-
-configuration& config() {
-  static configuration config;
-  return config;
-}
-
-integral_setting File::autodetect_type(config(), "file.autodetect_type",
-  "Auto-detect file type by inspecting file header, rather than by file extension.\n"
-  "In other words, if a .zip file is renamed to .smc, it will still be correctly\n"
-  "identified as a .zip file. However, there is an infinitesimal (1:~500,000,000)\n"
-  "chance of a false detection when loading an uncompressed image file, if this\n"
-  "option is enabled.",
-  integral_setting::boolean, false);
-
-integral_setting File::bypass_patch_crc32(config(), "file.bypass_patch_crc32",
-  "UPS patches contain CRC32s to validate that a patch was applied successfully.\n"
-  "By default, if this validation fails, said patch will not be applied.\n"
-  "Setting this option to true will bypass the validation,\n"
-  "which may or may not result in a working image.\n"
-  "Enabling this option is strongly discouraged.",
-  integral_setting::boolean, false);
-
-string file_updatepath(const char *req_file, const char *req_path) {
-  string file(req_file);
-  replace(file, "\\", "/");
-  if(!req_path || strlen(req_path) == 0) { return file; }
-
-  string path(req_path);
-  replace(path, "\\", "/");
-  if(!strend(path, "/")) { strcat(path, "/"); }
-
-  if(strbegin(path, "./")) {
-    ltrim(path(), "./");
-    string temp;
-    strcpy(temp, config::path.base);
-    strcat(temp, path);
-    strcpy(path, temp);
-  }
-
-  lstring part;
-  split(part, "/", file);
-  strcat(path, part[count(part) - 1]);
-  return path;
-}
-
-string_setting Path::base("path.base", "Path that bsnes resides in", "");
-string_setting Path::user("path.user", "Path to user folder", "");
-
-string_setting Path::rom(config(), "path.rom",
-  "Default path to look for ROM files in (\"\" = use default directory)", "");
-string_setting Path::patch(config(), "path.patch",
-  "Default path for all UPS patch files (\"\" = use current directory)", "");
-string_setting Path::save(config(), "path.save",
-  "Default path for all save RAM files (\"\" = use current directory)", "");
-string_setting Path::cheat(config(), "path.cheat",
-  "Default path for all cheat files (\"\" = use current directory)", "");
-string_setting Path::bsx(config(), "path.bsx", "", "");
-string_setting Path::st(config(), "path.st", "", "");
-
-integral_setting SNES::controller_port0(config(), "snes.controller_port_1",
-  "Controller attached to SNES port 1", integral_setting::decimal, ::SNES::Input::DeviceIDJoypad1);
-integral_setting SNES::controller_port1(config(), "snes.controller_port_2",
-  "Controller attached to SNES port 2", integral_setting::decimal, ::SNES::Input::DeviceIDJoypad2);
-
-integral_setting CPU::ntsc_clock_rate(config(), "cpu.ntsc_clock_rate",
-  "NTSC S-CPU clock rate (in hz)", integral_setting::decimal, 21477272);
-integral_setting CPU::pal_clock_rate(config(), "cpu.pal_clock_rate",
-  "PAL S-CPU clock rate (in hz)", integral_setting::decimal, 21281370);
-integral_setting CPU::wram_init_value(config(), "cpu.wram_init_value",
-  "Value to initialize 128k WRAM to upon power cycle.\n"
-  "Note that on real hardware, this value is undefined; meaning it can vary\n"
-  "per power-on, and per SNES unit. Such randomness is undesirable for an\n"
-  "emulator, so a static value is needed. There is also some form of pattern\n"
-  "to the randomness that has yet to be determined, which some games rely upon.\n"
-  "A value of 0x55 is safe for all known commercial software, and should be used.\n"
-  "However, some software written for SNES copiers, or backup units, relies on\n"
-  "WRAM being initialized to 0x00; which was a side-effect of the BIOS program\n"
-  "which executed on these copiers. Using 0x00 will therefore fix many homebrew\n"
-  "programs, but *will* break some poorly programmed commercial software titles,\n"
-  "which do not properly initialize WRAM upon power cycle.\n",
-  integral_setting::hex, 0x55);
-
-integral_setting CPU::hdma_enable("cpu.hdma_enable",
-  "Enable HDMA effects", integral_setting::boolean, true);
-
-integral_setting SMP::ntsc_clock_rate(config(), "smp.ntsc_clock_rate",
-  "NTSC S-SMP clock rate (in hz)", integral_setting::decimal, 24606720);
-integral_setting SMP::pal_clock_rate(config(), "smp.pal_clock_rate",
-  "PAL S-SMP clock rate (in hz)", integral_setting::decimal, 24606720);
-
-integral_setting PPU::Hack::render_scanline_position(config(), "ppu.hack.render_scanline_position",
-  "Approximate HCLOCK position to render at for scanline-based renderers",
-  integral_setting::decimal, 512);
-integral_setting PPU::Hack::obj_cache(config(), "ppu.hack.obj_cache",
-  "Cache OAM OBJ attributes one scanline before rendering\n"
-  "This is technically closer to the actual operation of the SNES,\n"
-  "but can cause problems in some games if enabled",
-  integral_setting::boolean, false);
-integral_setting PPU::Hack::oam_address_invalidation(config(), "ppu.hack.oam_address_invalidation",
-  "OAM access address changes during active display, as the S-PPU reads\n"
-  "data to render the display. Thusly, the address retrieved when accessing\n"
-  "OAM during active display is unpredictable. Unfortunately, the exact\n"
-  "algorithm for this is completely unknown at this time. It is more hardware\n"
-  "accurate to enable this setting, but one must *not* rely on the actual\n"
-  "address to match hardware under emulation.",
-  integral_setting::boolean, true);
-integral_setting PPU::Hack::cgram_address_invalidation(config(), "ppu.hack.cgram_address_invalidation",
-  "CGRAM access address changes during active display (excluding hblank), as\n"
-  "the S-PPU reads data to render the display. Thusly, as with OAM, the access\n"
-  "address is unpredictable. Again, enabling this setting is more hardware\n"
-  "accurate, but one must *not* rely on the actual address to match hardware\n"
-  "under emulation.",
-  integral_setting::boolean, true);
-
-integral_setting PPU::opt_enable("ppu.opt_enable", "Enable offset-per-tile effects", integral_setting::boolean, true);
-integral_setting PPU::bg1_pri0_enable("ppu.bg1_pri0_enable", "Enable BG1 Priority 0", integral_setting::boolean, true);
-integral_setting PPU::bg1_pri1_enable("ppu.bg1_pri1_enable", "Enable BG1 Priority 1", integral_setting::boolean, true);
-integral_setting PPU::bg2_pri0_enable("ppu.bg2_pri0_enable", "Enable BG2 Priority 0", integral_setting::boolean, true);
-integral_setting PPU::bg2_pri1_enable("ppu.bg2_pri1_enable", "Enable BG2 Priority 1", integral_setting::boolean, true);
-integral_setting PPU::bg3_pri0_enable("ppu.bg3_pri0_enable", "Enable BG3 Priority 0", integral_setting::boolean, true);
-integral_setting PPU::bg3_pri1_enable("ppu.bg3_pri1_enable", "Enable BG3 Priority 1", integral_setting::boolean, true);
-integral_setting PPU::bg4_pri0_enable("ppu.bg4_pri0_enable", "Enable BG4 Priority 0", integral_setting::boolean, true);
-integral_setting PPU::bg4_pri1_enable("ppu.bg4_pri1_enable", "Enable BG4 Priority 1", integral_setting::boolean, true);
-integral_setting PPU::oam_pri0_enable("ppu.oam_pri0_enable", "Enable OAM Priority 0", integral_setting::boolean, true);
-integral_setting PPU::oam_pri1_enable("ppu.oam_pri1_enable", "Enable OAM Priority 1", integral_setting::boolean, true);
-integral_setting PPU::oam_pri2_enable("ppu.oam_pri2_enable", "Enable OAM Priority 2", integral_setting::boolean, true);
-integral_setting PPU::oam_pri3_enable("ppu.oam_pri3_enable", "Enable OAM Priority 3", integral_setting::boolean, true);
-
-} //namespace config

src/config/config.h

@@ -1,49 +0,0 @@
-namespace config {
-
-extern configuration& config();
-
-string file_updatepath(const char*, const char*);
-
-extern struct File {
-  static integral_setting autodetect_type;
-  static integral_setting bypass_patch_crc32;
-} file;
-
-extern struct Path {
-  static string_setting base, user, rom, patch, save, cheat;
-  static string_setting bsx, st;
-} path;
-
-extern struct SNES {
-  static integral_setting controller_port0;
-  static integral_setting controller_port1;
-} snes;
-
-extern struct CPU {
-  static integral_setting ntsc_clock_rate, pal_clock_rate;
-  static integral_setting wram_init_value;
-  static integral_setting hdma_enable;
-} cpu;
-
-extern struct SMP {
-  static integral_setting ntsc_clock_rate, pal_clock_rate;
-} smp;
-
-extern struct PPU {
-  struct Hack {
-    static integral_setting render_scanline_position;
-    static integral_setting obj_cache;
-    static integral_setting oam_address_invalidation;
-    static integral_setting cgram_address_invalidation;
-  } hack;
-
-  static integral_setting opt_enable;
-  static integral_setting bg1_pri0_enable, bg1_pri1_enable;
-  static integral_setting bg2_pri0_enable, bg2_pri1_enable;
-  static integral_setting bg3_pri0_enable, bg3_pri1_enable;
-  static integral_setting bg4_pri0_enable, bg4_pri1_enable;
-  static integral_setting oam_pri0_enable, oam_pri1_enable;
-  static integral_setting oam_pri2_enable, oam_pri3_enable;
-} ppu;
-
-};

src/cpu/core/bpp.sh

@@ -0,0 +1,3 @@
+clear
+bpp opcode_functions.cpp opcode_functions.bpp
+bpp opcode_headers.hpp opcode_headers.bpp

src/cpu/core/core.cpp

@@ -0,0 +1,51 @@
+#include <../base.hpp>
+
+#define CPUCORE_CPP
+namespace SNES {
+
+#include "opcode_algorithms.cpp"
+#include "opcode_functions.cpp"
+#include "opcode_tables.cpp"
+#include "disasm/disasm.cpp"
+
+//immediate, 2-cycle opcodes with I/O cycle will become bus read
+//when an IRQ is to be triggered immediately after opcode completion.
+//this affects the following opcodes:
+//  clc, cld, cli, clv, sec, sed, sei,
+//  tax, tay, txa, txy, tya, tyx,
+//  tcd, tcs, tdc, tsc, tsx, txs,
+//  inc, inx, iny, dec, dex, dey,
+//  asl, lsr, rol, ror, nop, xce.
+alwaysinline void CPUcore::op_io_irq() {
+  if(interrupt_pending()) {
+    //modify I/O cycle to bus read cycle, do not increment PC
+    op_read(regs.pc.d);
+  } else {
+    op_io();
+  }
+}
+
+alwaysinline void CPUcore::op_io_cond2() {
+  if(regs.d.l != 0x00) {
+    op_io();
+  }
+}
+
+alwaysinline void CPUcore::op_io_cond4(uint16 x, uint16 y) {
+  if(!regs.p.x || (x & 0xff00) != (y & 0xff00)) {
+    op_io();
+  }
+}
+
+alwaysinline void CPUcore::op_io_cond6(uint16 addr) {
+  if(regs.e && (regs.pc.w & 0xff00) != (addr & 0xff00)) {
+    op_io();
+  }
+}
+
+CPUcore::CPUcore() {
+  initialize_opcode_table();
+}
+
+};
+

src/cpu/core/core.hpp

@@ -1,54 +1,79 @@
-  CPUReg24 aa, rd;
-  uint8_t dp, sp;
-
-  void op_irq();
-
-  inline bool in_opcode() { return status.in_opcode; }
-
-  //op_read
-  void op_adc_b();
-  void op_adc_w();
-  void op_and_b();
-  void op_and_w();
-  void op_bit_b();
-  void op_bit_w();
-  void op_cmp_b();
-  void op_cmp_w();
-  void op_cpx_b();
-  void op_cpx_w();
-  void op_cpy_b();
-  void op_cpy_w();
-  void op_eor_b();
-  void op_eor_w();
-  void op_lda_b();
-  void op_lda_w();
-  void op_ldx_b();
-  void op_ldx_w();
-  void op_ldy_b();
-  void op_ldy_w();
-  void op_ora_b();
-  void op_ora_w();
-  void op_sbc_b();
-  void op_sbc_w();
-  //op_rmw
-  void op_inc_b();
-  void op_inc_w();
-  void op_dec_b();
-  void op_dec_w();
-  void op_asl_b();
-  void op_asl_w();
-  void op_lsr_b();
-  void op_lsr_w();
-  void op_rol_b();
-  void op_rol_w();
-  void op_ror_b();
-  void op_ror_w();
-  void op_trb_b();
-  void op_trb_w();
-  void op_tsb_b();
-  void op_tsb_w();
+class CPUcore {
+public:
+  #include "registers.hpp"
+  #include "memory.hpp"
+  #include "opcode_headers.hpp"
+  #include "disasm/disasm.hpp"
 
-  void op_io_irq();
-  void op_io_cond2();
-  void op_io_cond4(uint16 x, uint16 y);
-  void op_io_cond6(uint16 addr);
+  regs_t regs;
+  reg24_t aa, rd;
+  uint8_t sp, dp;
+
+  virtual void op_io() = 0;
+  virtual uint8_t op_read(uint32_t addr) = 0;
+  virtual void op_write(uint32_t addr, uint8_t data) = 0;
+  virtual void last_cycle() = 0;
+  virtual bool interrupt_pending() = 0;
+
+  void op_io_irq();
+  void op_io_cond2();
+  void op_io_cond4(uint16 x, uint16 y);
+  void op_io_cond6(uint16 addr);
+
+  void op_adc_b();
+  void op_adc_w();
+  void op_and_b();
+  void op_and_w();
+  void op_bit_b();
+  void op_bit_w();
+  void op_cmp_b();
+  void op_cmp_w();
+  void op_cpx_b();
+  void op_cpx_w();
+  void op_cpy_b();
+  void op_cpy_w();
+  void op_eor_b();
+  void op_eor_w();
+  void op_lda_b();
+  void op_lda_w();
+  void op_ldx_b();
+  void op_ldx_w();
+  void op_ldy_b();
+  void op_ldy_w();
+  void op_ora_b();
+  void op_ora_w();
+  void op_sbc_b();
+  void op_sbc_w();
+
+  void op_inc_b();
+  void op_inc_w();
+  void op_dec_b();
+  void op_dec_w();
+  void op_asl_b();
+  void op_asl_w();
+  void op_lsr_b();
+  void op_lsr_w();
+  void op_rol_b();
+  void op_rol_w();
+  void op_ror_b();
+  void op_ror_w();
+  void op_trb_b();
+  void op_trb_w();
+  void op_tsb_b();
+  void op_tsb_w();
+
+  void (CPUcore::**opcode_table)();
+  void (CPUcore::*op_table[256 * 5])();
+  void initialize_opcode_table();
+  void update_table();
+
+  enum {
+    table_EM =    0,  // 8-bit accumulator,  8-bit index (emulation mode)
+    table_MX =  256,  // 8-bit accumulator,  8-bit index
+    table_Mx =  512,  // 8-bit accumulator, 16-bit index
+    table_mX =  768,  //16-bit accumulator,  8-bit index
+    table_mx = 1024,  //16-bit accumulator, 16-bit index
+  };
+
+  CPUcore();
+};

src/cpu/core/disasm/disasm.cpp

@@ -0,0 +1,479 @@
+uint8 CPUcore::dreadb(uint32 addr) {
+  if((addr & 0x40ffff) >= 0x2000 && (addr & 0x40ffff) <= 0x5fff) {
+    //$[00-3f|80-bf]:[2000-5fff]
+    //do not read MMIO registers within debugger
+    return 0x00;
+  }
+  return bus.read(addr);
+}
+
+uint16 CPUcore::dreadw(uint32 addr) {
+  uint16 r;
+  r  = dreadb((addr + 0) & 0xffffff) <<  0;
+  r |= dreadb((addr + 1) & 0xffffff) <<  8;
+  return r;
+}
+
+uint32 CPUcore::dreadl(uint32 addr) {
+  uint32 r;
+  r  = dreadb((addr + 0) & 0xffffff) <<  0;
+  r |= dreadb((addr + 1) & 0xffffff) <<  8;
+  r |= dreadb((addr + 2) & 0xffffff) << 16;
+  return r;
+}
+
+uint32 CPUcore::decode(uint8 offset_type, uint32 addr) {
+  uint32 r = 0;
+
+  switch(offset_type) {
+    case OPTYPE_DP:
+      r = (regs.d + (addr & 0xffff)) & 0xffff;
+      break;
+    case OPTYPE_DPX:
+      r = (regs.d + regs.x + (addr & 0xffff)) & 0xffff;
+      break;
+    case OPTYPE_DPY:
+      r = (regs.d + regs.y + (addr & 0xffff)) & 0xffff;
+      break;
+    case OPTYPE_IDP:
+      addr = (regs.d + (addr & 0xffff)) & 0xffff;
+      r = (regs.db << 16) + dreadw(addr);
+      break;
+    case OPTYPE_IDPX:
+      addr = (regs.d + regs.x + (addr & 0xffff)) & 0xffff;
+      r = (regs.db << 16) + dreadw(addr);
+      break;
+    case OPTYPE_IDPY:
+      addr = (regs.d + (addr & 0xffff)) & 0xffff;
+      r = (regs.db << 16) + dreadw(addr) + regs.y;
+      break;
+    case OPTYPE_ILDP:
+      addr = (regs.d + (addr & 0xffff)) & 0xffff;
+      r = dreadl(addr);
+      break;
+    case OPTYPE_ILDPY:
+      addr = (regs.d + (addr & 0xffff)) & 0xffff;
+      r = dreadl(addr) + regs.y;
+      break;
+    case OPTYPE_ADDR:
+      r = (regs.db << 16) + (addr & 0xffff);
+      break;
+    case OPTYPE_ADDR_PC:
+      r = (regs.pc.b << 16) + (addr & 0xffff);
+      break;
+    case OPTYPE_ADDRX:
+      r = (regs.db << 16) + (addr & 0xffff) + regs.x;
+      break;
+    case OPTYPE_ADDRY:
+      r = (regs.db << 16) + (addr & 0xffff) + regs.y;
+      break;
+    case OPTYPE_IADDR_PC:
+      r = (regs.pc.b << 16) + (addr & 0xffff);
+      break;
+    case OPTYPE_IADDRX:
+      r = (regs.pc.b << 16) + ((addr + regs.x) & 0xffff);
+      break;
+    case OPTYPE_ILADDR:
+      r = addr;
+      break;
+    case OPTYPE_LONG:
+      r = addr;
+      break;
+    case OPTYPE_LONGX:
+      r = (addr + regs.x);
+      break;
+    case OPTYPE_SR:
+      r = (regs.s + (addr & 0xff)) & 0xffff;
+      break;
+    case OPTYPE_ISRY:
+      addr = (regs.s + (addr & 0xff)) & 0xffff;
+      r = (regs.db << 16) + dreadw(addr) + regs.y;
+      break;
+    case OPTYPE_RELB:
+      r  = (regs.pc.b << 16) + ((regs.pc.w + 2) & 0xffff);
+      r += int8(addr);
+      break;
+    case OPTYPE_RELW:
+      r  = (regs.pc.b << 16) + ((regs.pc.w + 3) & 0xffff);
+      r += int16(addr);
+      break;
+  }
+
+  return(r & 0xffffff);
+}
+
+void CPUcore::disassemble_opcode(char *output) {
+  static reg24_t pc;
+  char t[256];
+  char *s = output;
+
+  if(false /* in_opcode() == true */) {
+    strcpy(s, "?????? <CPU within opcode>");
+    return;
+  }
+
+  pc.d = regs.pc.d;
+  sprintf(s, "%.6x ", (uint32)pc.d);
+
+  uint8 op  = dreadb(pc.d); pc.w++;
+  uint8 op0 = dreadb(pc.d); pc.w++;
+  uint8 op1 = dreadb(pc.d); pc.w++;
+  uint8 op2 = dreadb(pc.d);
+
+  #define op8  ((op0))
+  #define op16 ((op0) | (op1 << 8))
+  #define op24 ((op0) | (op1 << 8) | (op2 << 16))
+  #define a8   (regs.e || regs.p.m)
+  #define x8   (regs.e || regs.p.x)
+
+  switch(op) {
+    case 0x00: sprintf(t, "brk #$%.2x               ", op8); break;
+    case 0x01: sprintf(t, "ora ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x02: sprintf(t, "cop #$%.2x               ", op8); break;
+    case 0x03: sprintf(t, "ora $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x04: sprintf(t, "tsb $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x05: sprintf(t, "ora $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x06: sprintf(t, "asl $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x07: sprintf(t, "ora [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x08: sprintf(t, "php                    "); break;
+    case 0x09: if(a8)sprintf(t, "ora #$%.2x               ", op8);
+               else  sprintf(t, "ora #$%.4x             ", op16); break;
+    case 0x0a: sprintf(t, "asl a                  "); break;
+    case 0x0b: sprintf(t, "phd                    "); break;
+    case 0x0c: sprintf(t, "tsb $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x0d: sprintf(t, "ora $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x0e: sprintf(t, "asl $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x0f: sprintf(t, "ora $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x10: sprintf(t, "bpl $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x11: sprintf(t, "ora ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x12: sprintf(t, "ora ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x13: sprintf(t, "ora ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x14: sprintf(t, "trb $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x15: sprintf(t, "ora $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x16: sprintf(t, "asl $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x17: sprintf(t, "ora [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x18: sprintf(t, "clc                    "); break;
+    case 0x19: sprintf(t, "ora $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x1a: sprintf(t, "inc                    "); break;
+    case 0x1b: sprintf(t, "tcs                    "); break;
+    case 0x1c: sprintf(t, "trb $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x1d: sprintf(t, "ora $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x1e: sprintf(t, "asl $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x1f: sprintf(t, "ora $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0x20: sprintf(t, "jsr $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR_PC, op16)); break;
+    case 0x21: sprintf(t, "and ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x22: sprintf(t, "jsl $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x23: sprintf(t, "and $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x24: sprintf(t, "bit $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x25: sprintf(t, "and $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x26: sprintf(t, "rol $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x27: sprintf(t, "and [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x28: sprintf(t, "plp                    "); break;
+    case 0x29: if(a8)sprintf(t, "and #$%.2x               ", op8);
+               else  sprintf(t, "and #$%.4x             ", op16); break;
+    case 0x2a: sprintf(t, "rol a                  "); break;
+    case 0x2b: sprintf(t, "pld                    "); break;
+    case 0x2c: sprintf(t, "bit $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x2d: sprintf(t, "and $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x2e: sprintf(t, "rol $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x2f: sprintf(t, "and $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x30: sprintf(t, "bmi $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x31: sprintf(t, "and ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x32: sprintf(t, "and ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x33: sprintf(t, "and ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x34: sprintf(t, "bit $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x35: sprintf(t, "and $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x36: sprintf(t, "rol $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x37: sprintf(t, "and [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x38: sprintf(t, "sec                    "); break;
+    case 0x39: sprintf(t, "and $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x3a: sprintf(t, "dec                    "); break;
+    case 0x3b: sprintf(t, "tsc                    "); break;
+    case 0x3c: sprintf(t, "bit $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x3d: sprintf(t, "and $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x3e: sprintf(t, "rol $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x3f: sprintf(t, "and $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0x40: sprintf(t, "rti                    "); break;
+    case 0x41: sprintf(t, "eor ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x42: sprintf(t, "wdm                    "); break;
+    case 0x43: sprintf(t, "eor $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x44: sprintf(t, "mvp $%.2x,$%.2x            ", op1, op8); break;
+    case 0x45: sprintf(t, "eor $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x46: sprintf(t, "lsr $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x47: sprintf(t, "eor [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x48: sprintf(t, "pha                    "); break;
+    case 0x49: if(a8)sprintf(t, "eor #$%.2x               ", op8);
+               else  sprintf(t, "eor #$%.4x             ", op16); break;
+    case 0x4a: sprintf(t, "lsr a                  "); break;
+    case 0x4b: sprintf(t, "phk                    "); break;
+    case 0x4c: sprintf(t, "jmp $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR_PC, op16)); break;
+    case 0x4d: sprintf(t, "eor $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x4e: sprintf(t, "lsr $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x4f: sprintf(t, "eor $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x50: sprintf(t, "bvc $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x51: sprintf(t, "eor ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x52: sprintf(t, "eor ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x53: sprintf(t, "eor ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x54: sprintf(t, "mvn $%.2x,$%.2x            ", op1, op8); break;
+    case 0x55: sprintf(t, "eor $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x56: sprintf(t, "lsr $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x57: sprintf(t, "eor [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x58: sprintf(t, "cli                    "); break;
+    case 0x59: sprintf(t, "eor $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x5a: sprintf(t, "phy                    "); break;
+    case 0x5b: sprintf(t, "tcd                    "); break;
+    case 0x5c: sprintf(t, "jml $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x5d: sprintf(t, "eor $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x5e: sprintf(t, "lsr $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x5f: sprintf(t, "eor $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0x60: sprintf(t, "rts                    "); break;
+    case 0x61: sprintf(t, "adc ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x62: sprintf(t, "per $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x63: sprintf(t, "adc $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x64: sprintf(t, "stz $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x65: sprintf(t, "adc $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x66: sprintf(t, "ror $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x67: sprintf(t, "adc [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x68: sprintf(t, "pla                    "); break;
+    case 0x69: if(a8)sprintf(t, "adc #$%.2x               ", op8);
+               else  sprintf(t, "adc #$%.4x             ", op16); break;
+    case 0x6a: sprintf(t, "ror a                  "); break;
+    case 0x6b: sprintf(t, "rtl                    "); break;
+    case 0x6c: sprintf(t, "jmp ($%.4x)   [$%.6x]", op16, decode(OPTYPE_IADDR_PC, op16)); break;
+    case 0x6d: sprintf(t, "adc $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x6e: sprintf(t, "ror $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x6f: sprintf(t, "adc $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x70: sprintf(t, "bvs $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x71: sprintf(t, "adc ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x72: sprintf(t, "adc ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x73: sprintf(t, "adc ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x74: sprintf(t, "stz $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x75: sprintf(t, "adc $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x76: sprintf(t, "ror $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x77: sprintf(t, "adc [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x78: sprintf(t, "sei                    "); break;
+    case 0x79: sprintf(t, "adc $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x7a: sprintf(t, "ply                    "); break;
+    case 0x7b: sprintf(t, "tdc                    "); break;
+    case 0x7c: sprintf(t, "jmp ($%.4x,x) [$%.6x]", op16, decode(OPTYPE_IADDRX, op16)); break;
+    case 0x7d: sprintf(t, "adc $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x7e: sprintf(t, "ror $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x7f: sprintf(t, "adc $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0x80: sprintf(t, "bra $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x81: sprintf(t, "sta ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0x82: sprintf(t, "brl $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELW, op16)), decode(OPTYPE_RELW, op16)); break;
+    case 0x83: sprintf(t, "sta $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0x84: sprintf(t, "sty $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x85: sprintf(t, "sta $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x86: sprintf(t, "stx $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0x87: sprintf(t, "sta [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0x88: sprintf(t, "dey                    "); break;
+    case 0x89: if(a8)sprintf(t, "bit #$%.2x               ", op8);
+               else  sprintf(t, "bit #$%.4x             ", op16); break;
+    case 0x8a: sprintf(t, "txa                    "); break;
+    case 0x8b: sprintf(t, "phb                    "); break;
+    case 0x8c: sprintf(t, "sty $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x8d: sprintf(t, "sta $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x8e: sprintf(t, "stx $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x8f: sprintf(t, "sta $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0x90: sprintf(t, "bcc $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0x91: sprintf(t, "sta ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0x92: sprintf(t, "sta ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0x93: sprintf(t, "sta ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0x94: sprintf(t, "sty $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x95: sprintf(t, "sta $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0x96: sprintf(t, "stx $%.2x,y     [$%.6x]", op8, decode(OPTYPE_DPY, op8)); break;
+    case 0x97: sprintf(t, "sta [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0x98: sprintf(t, "tya                    "); break;
+    case 0x99: sprintf(t, "sta $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0x9a: sprintf(t, "txs                    "); break;
+    case 0x9b: sprintf(t, "txy                    "); break;
+    case 0x9c: sprintf(t, "stz $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0x9d: sprintf(t, "sta $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x9e: sprintf(t, "stz $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0x9f: sprintf(t, "sta $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0xa0: if(x8)sprintf(t, "ldy #$%.2x               ", op8);
+               else  sprintf(t, "ldy #$%.4x             ", op16); break;
+    case 0xa1: sprintf(t, "lda ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0xa2: if(x8)sprintf(t, "ldx #$%.2x               ", op8);
+               else  sprintf(t, "ldx #$%.4x             ", op16); break;
+    case 0xa3: sprintf(t, "lda $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0xa4: sprintf(t, "ldy $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xa5: sprintf(t, "lda $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xa6: sprintf(t, "ldx $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xa7: sprintf(t, "lda [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0xa8: sprintf(t, "tay                    "); break;
+    case 0xa9: if(a8)sprintf(t, "lda #$%.2x               ", op8);
+               else  sprintf(t, "lda #$%.4x             ", op16); break;
+    case 0xaa: sprintf(t, "tax                    "); break;
+    case 0xab: sprintf(t, "plb                    "); break;
+    case 0xac: sprintf(t, "ldy $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xad: sprintf(t, "lda $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xae: sprintf(t, "ldx $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xaf: sprintf(t, "lda $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0xb0: sprintf(t, "bcs $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0xb1: sprintf(t, "lda ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0xb2: sprintf(t, "lda ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0xb3: sprintf(t, "lda ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0xb4: sprintf(t, "ldy $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xb5: sprintf(t, "lda $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xb6: sprintf(t, "ldx $%.2x,y     [$%.6x]", op8, decode(OPTYPE_DPY, op8)); break;
+    case 0xb7: sprintf(t, "lda [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0xb8: sprintf(t, "clv                    "); break;
+    case 0xb9: sprintf(t, "lda $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0xba: sprintf(t, "tsx                    "); break;
+    case 0xbb: sprintf(t, "tyx                    "); break;
+    case 0xbc: sprintf(t, "ldy $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xbd: sprintf(t, "lda $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xbe: sprintf(t, "ldx $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0xbf: sprintf(t, "lda $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0xc0: if(x8)sprintf(t, "cpy #$%.2x               ", op8);
+               else  sprintf(t, "cpy #$%.4x             ", op16); break;
+    case 0xc1: sprintf(t, "cmp ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0xc2: sprintf(t, "rep #$%.2x               ", op8); break;
+    case 0xc3: sprintf(t, "cmp $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0xc4: sprintf(t, "cpy $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xc5: sprintf(t, "cmp $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xc6: sprintf(t, "dec $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xc7: sprintf(t, "cmp [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0xc8: sprintf(t, "iny                    "); break;
+    case 0xc9: if(a8)sprintf(t, "cmp #$%.2x               ", op8);
+               else  sprintf(t, "cmp #$%.4x             ", op16); break;
+    case 0xca: sprintf(t, "dex                    "); break;
+    case 0xcb: sprintf(t, "wai                    "); break;
+    case 0xcc: sprintf(t, "cpy $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xcd: sprintf(t, "cmp $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xce: sprintf(t, "dec $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xcf: sprintf(t, "cmp $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0xd0: sprintf(t, "bne $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0xd1: sprintf(t, "cmp ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0xd2: sprintf(t, "cmp ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0xd3: sprintf(t, "cmp ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0xd4: sprintf(t, "pei ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0xd5: sprintf(t, "cmp $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xd6: sprintf(t, "dec $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xd7: sprintf(t, "cmp [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0xd8: sprintf(t, "cld                    "); break;
+    case 0xd9: sprintf(t, "cmp $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0xda: sprintf(t, "phx                    "); break;
+    case 0xdb: sprintf(t, "stp                    "); break;
+    case 0xdc: sprintf(t, "jmp [$%.4x]   [$%.6x]", op16, decode(OPTYPE_ILADDR, op16)); break;
+    case 0xdd: sprintf(t, "cmp $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xde: sprintf(t, "dec $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xdf: sprintf(t, "cmp $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+    case 0xe0: if(x8)sprintf(t, "cpx #$%.2x               ", op8);
+               else  sprintf(t, "cpx #$%.4x             ", op16); break;
+    case 0xe1: sprintf(t, "sbc ($%.2x,x)   [$%.6x]", op8, decode(OPTYPE_IDPX, op8)); break;
+    case 0xe2: sprintf(t, "sep #$%.2x               ", op8); break;
+    case 0xe3: sprintf(t, "sbc $%.2x,s     [$%.6x]", op8, decode(OPTYPE_SR, op8)); break;
+    case 0xe4: sprintf(t, "cpx $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xe5: sprintf(t, "sbc $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xe6: sprintf(t, "inc $%.2x       [$%.6x]", op8, decode(OPTYPE_DP, op8)); break;
+    case 0xe7: sprintf(t, "sbc [$%.2x]     [$%.6x]", op8, decode(OPTYPE_ILDP, op8)); break;
+    case 0xe8: sprintf(t, "inx                    "); break;
+    case 0xe9: if(a8)sprintf(t, "sbc #$%.2x               ", op8);
+               else  sprintf(t, "sbc #$%.4x             ", op16); break;
+    case 0xea: sprintf(t, "nop                    "); break;
+    case 0xeb: sprintf(t, "xba                    "); break;
+    case 0xec: sprintf(t, "cpx $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xed: sprintf(t, "sbc $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xee: sprintf(t, "inc $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xef: sprintf(t, "sbc $%.6x   [$%.6x]", op24, decode(OPTYPE_LONG, op24)); break;
+    case 0xf0: sprintf(t, "beq $%.4x     [$%.6x]", uint16(decode(OPTYPE_RELB, op8)), decode(OPTYPE_RELB, op8)); break;
+    case 0xf1: sprintf(t, "sbc ($%.2x),y   [$%.6x]", op8, decode(OPTYPE_IDPY, op8)); break;
+    case 0xf2: sprintf(t, "sbc ($%.2x)     [$%.6x]", op8, decode(OPTYPE_IDP, op8)); break;
+    case 0xf3: sprintf(t, "sbc ($%.2x,s),y [$%.6x]", op8, decode(OPTYPE_ISRY, op8)); break;
+    case 0xf4: sprintf(t, "pea $%.4x     [$%.6x]", op16, decode(OPTYPE_ADDR, op16)); break;
+    case 0xf5: sprintf(t, "sbc $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xf6: sprintf(t, "inc $%.2x,x     [$%.6x]", op8, decode(OPTYPE_DPX, op8)); break;
+    case 0xf7: sprintf(t, "sbc [$%.2x],y   [$%.6x]", op8, decode(OPTYPE_ILDPY, op8)); break;
+    case 0xf8: sprintf(t, "sed                    "); break;
+    case 0xf9: sprintf(t, "sbc $%.4x,y   [$%.6x]", op16, decode(OPTYPE_ADDRY, op16)); break;
+    case 0xfa: sprintf(t, "plx                    "); break;
+    case 0xfb: sprintf(t, "xce                    "); break;
+    case 0xfc: sprintf(t, "jsr ($%.4x,x) [$%.6x]", op16, decode(OPTYPE_IADDRX, op16)); break;
+    case 0xfd: sprintf(t, "sbc $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xfe: sprintf(t, "inc $%.4x,x   [$%.6x]", op16, decode(OPTYPE_ADDRX, op16)); break;
+    case 0xff: sprintf(t, "sbc $%.6x,x [$%.6x]", op24, decode(OPTYPE_LONGX, op24)); break;
+  }
+
+  #undef op8
+  #undef op16
+  #undef op24
+  #undef a8
+  #undef x8
+
+  strcat(s, t);
+  strcat(s, " ");
+
+  sprintf(t, "A:%.4x X:%.4x Y:%.4x S:%.4x D:%.4x DB:%.2x ",
+    regs.a.w, regs.x.w, regs.y.w, regs.s.w, regs.d.w, regs.db);
+  strcat(s, t);
+
+  if(regs.e) {
+    sprintf(t, "%c%c%c%c%c%c%c%c",
+      regs.p.n ? 'N' : 'n', regs.p.v ? 'V' : 'v',
+      regs.p.m ? '1' : '0', regs.p.x ? 'B' : 'b',
+      regs.p.d ? 'D' : 'd', regs.p.i ? 'I' : 'i',
+      regs.p.z ? 'Z' : 'z', regs.p.c ? 'C' : 'c');
+  } else {
+    sprintf(t, "%c%c%c%c%c%c%c%c",
+      regs.p.n ? 'N' : 'n', regs.p.v ? 'V' : 'v',
+      regs.p.m ? 'M' : 'm', regs.p.x ? 'X' : 'x',
+      regs.p.d ? 'D' : 'd', regs.p.i ? 'I' : 'i',
+      regs.p.z ? 'Z' : 'z', regs.p.c ? 'C' : 'c');
+  }
+
+  strcat(s, t);
+  strcat(s, " ");
+
+  sprintf(t, "V:%3d H:%4d", ppu.vcounter(), ppu.hcounter());
+  strcat(s, t);
+}
+
+//opcode_length() retrieves the length of the next opcode
+//to be executed. It is used by the debugger to step over,
+//disable and proceed cpu opcodes.
+//
+//5 and 6 are special cases, 5 is used for #consts based on
+//the A register size, 6 for the X/Y register size. the
+//rest are literal sizes. There's no need to test for
+//emulation mode, as regs.p.m/regs.p.x should *always* be
+//set in emulation mode.
+
+uint8 CPUcore::opcode_length() {
+  uint8 op, len;
+  static uint8 op_len_tbl[256] = {
+  //0,1,2,3,  4,5,6,7,  8,9,a,b,  c,d,e,f
+
+    2,2,2,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x0n
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0x1n
+    3,2,4,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x2n
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0x3n
+
+    1,2,2,2,  3,2,2,2,  1,5,1,1,  3,3,3,4, //0x4n
+    2,2,2,2,  3,2,2,2,  1,3,1,1,  4,3,3,4, //0x5n
+    1,2,3,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x6n
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0x7n
+
+    2,2,3,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0x8n
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0x9n
+    6,2,6,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0xan
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0xbn
+
+    6,2,2,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0xcn
+    2,2,2,2,  2,2,2,2,  1,3,1,1,  3,3,3,4, //0xdn
+    6,2,2,2,  2,2,2,2,  1,5,1,1,  3,3,3,4, //0xen
+    2,2,2,2,  3,2,2,2,  1,3,1,1,  3,3,3,4  //0xfn
+  };
+
+  if(false /* in_opcode() == true */) {
+    return 0;
+  }
+
+  op  = dreadb(regs.pc.d);
+  len = op_len_tbl[op];
+  if(len == 5) return (regs.e || regs.p.m) ? 2 : 3;
+  if(len == 6) return (regs.e || regs.p.x) ? 2 : 3;
+  return len;
+}

src/cpu/core/disasm/disasm.hpp

@@ -0,0 +1,30 @@
+  enum {
+    OPTYPE_DP = 0,    //dp
+    OPTYPE_DPX,       //dp,x
+    OPTYPE_DPY,       //dp,y
+    OPTYPE_IDP,       //(dp)
+    OPTYPE_IDPX,      //(dp,x)
+    OPTYPE_IDPY,      //(dp),y
+    OPTYPE_ILDP,      //[dp]
+    OPTYPE_ILDPY,     //[dp],y
+    OPTYPE_ADDR,      //addr
+    OPTYPE_ADDRX,     //addr,x
+    OPTYPE_ADDRY,     //addr,y
+    OPTYPE_IADDRX,    //(addr,x)
+    OPTYPE_ILADDR,    //[addr]
+    OPTYPE_LONG,      //long
+    OPTYPE_LONGX,     //long, x
+    OPTYPE_SR,        //sr,s
+    OPTYPE_ISRY,      //(sr,s),y
+    OPTYPE_ADDR_PC,   //pbr:addr
+    OPTYPE_IADDR_PC,  //pbr:(addr)
+    OPTYPE_RELB,      //relb
+    OPTYPE_RELW,      //relw
+  };
+
+  void   disassemble_opcode(char *output);
+  uint8  dreadb(uint32 addr);
+  uint16 dreadw(uint32 addr);
+  uint32 dreadl(uint32 addr);
+  uint32 decode(uint8 offset_type, uint32 addr);
+  uint8  opcode_length();

src/cpu/core/memory.hpp

@@ -0,0 +1,77 @@
+alwaysinline uint8_t op_readpc() {
+  return op_read((regs.pc.b << 16) + regs.pc.w++);
+}
+
+alwaysinline uint8_t op_readstack() {
+  regs.e ? regs.s.l++ : regs.s.w++;
+  return op_read(regs.s.w);
+}
+
+alwaysinline uint8_t op_readstackn() {
+  return op_read(++regs.s.w);
+}
+
+alwaysinline uint8_t op_readaddr(uint32_t addr) {
+  return op_read(addr & 0xffff);
+}
+
+alwaysinline uint8_t op_readlong(uint32_t addr) {
+  return op_read(addr & 0xffffff);
+}
+
+alwaysinline uint8_t op_readdbr(uint32_t addr) {
+  return op_read(((regs.db << 16) + addr) & 0xffffff);
+}
+
+alwaysinline uint8_t op_readpbr(uint32_t addr) {
+  return op_read((regs.pc.b << 16) + (addr & 0xffff));
+}
+
+alwaysinline uint8_t op_readdp(uint32_t addr) {
+  if(regs.e && regs.d.l == 0x00) {
+    return op_read((regs.d & 0xff00) + ((regs.d + (addr & 0xffff)) & 0xff));
+  } else {
+    return op_read((regs.d + (addr & 0xffff)) & 0xffff);
+  }
+}
+
+alwaysinline uint8_t op_readsp(uint32_t addr) {
+  return op_read((regs.s + (addr & 0xffff)) & 0xffff);
+}
+
+alwaysinline void op_writestack(uint8_t data) {
+  op_write(regs.s.w, data);
+  regs.e ? regs.s.l-- : regs.s.w--;
+}
+
+alwaysinline void op_writestackn(uint8_t data) {
+  op_write(regs.s.w--, data);
+}
+
+alwaysinline void op_writeaddr(uint32_t addr, uint8_t data) {
+  op_write(addr & 0xffff, data);
+}
+
+alwaysinline void op_writelong(uint32_t addr, uint8_t data) {
+  op_write(addr & 0xffffff, data);
+}
+
+alwaysinline void op_writedbr(uint32_t addr, uint8_t data) {
+  op_write(((regs.db << 16) + addr) & 0xffffff, data);
+}
+
+alwaysinline void op_writepbr(uint32_t addr, uint8_t data) {
+  op_write((regs.pc.b << 16) + (addr & 0xffff), data);
+}
+
+alwaysinline void op_writedp(uint32_t addr, uint8_t data) {
+  if(regs.e && regs.d.l == 0x00) {
+    op_write((regs.d & 0xff00) + ((regs.d + (addr & 0xffff)) & 0xff), data);
+  } else {
+    op_write((regs.d + (addr & 0xffff)) & 0xffff, data);
+  }
+}
+
+alwaysinline void op_writesp(uint32_t addr, uint8_t data) {
+  op_write((regs.s + (addr & 0xffff)) & 0xffff, data);
+}

src/cpu/core/opcode_algorithms.cpp

@@ -1,7 +1,6 @@
-#ifdef SCPU_CPP
+#ifdef CPUCORE_CPP
 
-//op_read
-inline void sCPU::op_adc_b() {
+inline void CPUcore::op_adc_b() {
   int r;
   if(regs.p.d) {
     uint8 n0 = (regs.a.l     ) & 15;
@@ -29,7 +28,7 @@ inline void sCPU::op_adc_b() {
   regs.a.l = r;
 }
 
-inline void sCPU::op_adc_w() {
+inline void CPUcore::op_adc_w() {
   int r;
   if(regs.p.d) {
     uint8 n0 = (regs.a.w      ) & 15;
@@ -69,133 +68,133 @@ inline void sCPU::op_adc_w() {
   regs.a.w = r;
 }
 
-inline void sCPU::op_and_b() {
+inline void CPUcore::op_and_b() {
   regs.a.l &= rd.l;
   regs.p.n = regs.a.l & 0x80;
   regs.p.z = regs.a.l == 0;
 }
 
-inline void sCPU::op_and_w() {
+inline void CPUcore::op_and_w() {
   regs.a.w &= rd.w;
   regs.p.n = regs.a.w & 0x8000;
   regs.p.z = regs.a.w == 0;
 }
 
-inline void sCPU::op_bit_b() {
+inline void CPUcore::op_bit_b() {
   regs.p.n = rd.l & 0x80;
   regs.p.v = rd.l & 0x40;
   regs.p.z = (rd.l & regs.a.l) == 0;
 }
 
-inline void sCPU::op_bit_w() {
+inline void CPUcore::op_bit_w() {
   regs.p.n = rd.w & 0x8000;
   regs.p.v = rd.w & 0x4000;
   regs.p.z = (rd.w & regs.a.w) == 0;
 }
 
-inline void sCPU::op_cmp_b() {
+inline void CPUcore::op_cmp_b() {
   int r = regs.a.l - rd.l;
   regs.p.n = r & 0x80;
   regs.p.z = (uint8)r == 0;
   regs.p.c = r >= 0;
 }
 
-inline void sCPU::op_cmp_w() {
+inline void CPUcore::op_cmp_w() {
   int r = regs.a.w - rd.w;
   regs.p.n = r & 0x8000;
   regs.p.z = (uint16)r == 0;
   regs.p.c = r >= 0;
 }
 
-inline void sCPU::op_cpx_b() {
+inline void CPUcore::op_cpx_b() {
   int r = regs.x.l - rd.l;
   regs.p.n = r & 0x80;
   regs.p.z = (uint8)r == 0;
   regs.p.c = r >= 0;
 }
 
-inline void sCPU::op_cpx_w() {
+inline void CPUcore::op_cpx_w() {
   int r = regs.x.w - rd.w;
   regs.p.n = r & 0x8000;
   regs.p.z = (uint16)r == 0;
   regs.p.c = r >= 0;
 }
 
-inline void sCPU::op_cpy_b() {
+inline void CPUcore::op_cpy_b() {
   int r = regs.y.l - rd.l;
   regs.p.n = r & 0x80;
   regs.p.z = (uint8)r == 0;
   regs.p.c = r >= 0;
 }
 
-inline void sCPU::op_cpy_w() {
+inline void CPUcore::op_cpy_w() {
   int r = regs.y.w - rd.w;
   regs.p.n = r & 0x8000;
   regs.p.z = (uint16)r == 0;
   regs.p.c = r >= 0;
 }
 
-inline void sCPU::op_eor_b() {
+inline void CPUcore::op_eor_b() {
   regs.a.l ^= rd.l;
   regs.p.n = regs.a.l & 0x80;
   regs.p.z = regs.a.l == 0;
 }
 
-inline void sCPU::op_eor_w() {
+inline void CPUcore::op_eor_w() {
   regs.a.w ^= rd.w;
   regs.p.n = regs.a.w & 0x8000;
   regs.p.z = regs.a.w == 0;
 }
 
-inline void sCPU::op_lda_b() {
+inline void CPUcore::op_lda_b() {
   regs.a.l = rd.l;
   regs.p.n = regs.a.l & 0x80;
   regs.p.z = regs.a.l == 0;
 }
 
-inline void sCPU::op_lda_w() {
+inline void CPUcore::op_lda_w() {
   regs.a.w = rd.w;
   regs.p.n = regs.a.w & 0x8000;
   regs.p.z = regs.a.w == 0;
 }
 
-inline void sCPU::op_ldx_b() {
+inline void CPUcore::op_ldx_b() {
   regs.x.l = rd.l;
   regs.p.n = regs.x.l & 0x80;
   regs.p.z = regs.x.l == 0;
 }
 
-inline void sCPU::op_ldx_w() {
+inline void CPUcore::op_ldx_w() {
   regs.x.w = rd.w;
   regs.p.n = regs.x.w & 0x8000;
   regs.p.z = regs.x.w == 0;
 }
 
-inline void sCPU::op_ldy_b() {
+inline void CPUcore::op_ldy_b() {
   regs.y.l = rd.l;
   regs.p.n = regs.y.l & 0x80;
   regs.p.z = regs.y.l == 0;
 }
 
-inline void sCPU::op_ldy_w() {
+inline void CPUcore::op_ldy_w() {
   regs.y.w = rd.w;
   regs.p.n = regs.y.w & 0x8000;
   regs.p.z = regs.y.w == 0;
 }
 
-inline void sCPU::op_ora_b() {
+inline void CPUcore::op_ora_b() {
   regs.a.l |= rd.l;
   regs.p.n = regs.a.l & 0x80;
   regs.p.z = regs.a.l == 0;
 }
 
-inline void sCPU::op_ora_w() {
+inline void CPUcore::op_ora_w() {
   regs.a.w |= rd.w;
   regs.p.n = regs.a.w & 0x8000;
   regs.p.z = regs.a.w == 0;
 }
 
-inline void sCPU::op_sbc_b() {
+inline void CPUcore::op_sbc_b() {
   int r;
   if(regs.p.d) {
     uint8 n0 = (regs.a.l     ) & 15;
@@ -223,7 +222,7 @@ inline void sCPU::op_sbc_b() {
   regs.a.l = r;
 }
 
-inline void sCPU::op_sbc_w() {
+inline void CPUcore::op_sbc_w() {
   int r;
   if(regs.p.d) {
     uint8 n0 = (regs.a.w      ) & 15;
@@ -263,60 +262,59 @@ inline void sCPU::op_sbc_w() {
   regs.a.w = r;
 }
 
-//op_rmw
-inline void sCPU::op_inc_b() {
+inline void CPUcore::op_inc_b() {
   rd.l++;
   regs.p.n = rd.l & 0x80;
   regs.p.z = rd.l == 0;
 }
 
-inline void sCPU::op_inc_w() {
+inline void CPUcore::op_inc_w() {
   rd.w++;
   regs.p.n = rd.w & 0x8000;
   regs.p.z = rd.w == 0;
 }
 
-inline void sCPU::op_dec_b() {
+inline void CPUcore::op_dec_b() {
   rd.l--;
   regs.p.n = rd.l & 0x80;
   regs.p.z = rd.l == 0;
 }
 
-inline void sCPU::op_dec_w() {
+inline void CPUcore::op_dec_w() {
   rd.w--;
   regs.p.n = rd.w & 0x8000;
   regs.p.z = rd.w == 0;
 }
 
-inline void sCPU::op_asl_b() {
+inline void CPUcore::op_asl_b() {
   regs.p.c = rd.l & 0x80;
   rd.l <<= 1;
   regs.p.n = rd.l & 0x80;
   regs.p.z = rd.l == 0;
 }
 
-inline void sCPU::op_asl_w() {
+inline void CPUcore::op_asl_w() {
   regs.p.c = rd.w & 0x8000;
   rd.w <<= 1;
   regs.p.n = rd.w & 0x8000;
   regs.p.z = rd.w == 0;
 }
 
-inline void sCPU::op_lsr_b() {
+inline void CPUcore::op_lsr_b() {
   regs.p.c = rd.l & 1;
   rd.l >>= 1;
   regs.p.n = rd.l & 0x80;
   regs.p.z = rd.l == 0;
 }
 
-inline void sCPU::op_lsr_w() {
+inline void CPUcore::op_lsr_w() {
   regs.p.c = rd.w & 1;
   rd.w >>= 1;
   regs.p.n = rd.w & 0x8000;
   regs.p.z = rd.w == 0;
 }
 
-inline void sCPU::op_rol_b() {
+inline void CPUcore::op_rol_b() {
   unsigned carry = (unsigned)regs.p.c;
   regs.p.c = rd.l & 0x80;
   rd.l = (rd.l << 1) | carry;
@@ -324,7 +322,7 @@ inline void sCPU::op_rol_b() {
   regs.p.z = rd.l == 0;
 }
 
-inline void sCPU::op_rol_w() {
+inline void CPUcore::op_rol_w() {
   unsigned carry = (unsigned)regs.p.c;
   regs.p.c = rd.w & 0x8000;
   rd.w = (rd.w << 1) | carry;
@@ -332,7 +330,7 @@ inline void sCPU::op_rol_w() {
   regs.p.z = rd.w == 0;
 }
 
-inline void sCPU::op_ror_b() {
+inline void CPUcore::op_ror_b() {
   unsigned carry = (unsigned)regs.p.c << 7;
   regs.p.c = rd.l & 1;
   rd.l = carry | (rd.l >> 1);
@@ -340,7 +338,7 @@ inline void sCPU::op_ror_b() {
   regs.p.z = rd.l == 0;
 }
 
-inline void sCPU::op_ror_w() {
+inline void CPUcore::op_ror_w() {
   unsigned carry = (unsigned)regs.p.c << 15;
   regs.p.c = rd.w & 1;
   rd.w = carry | (rd.w >> 1);
@@ -348,24 +346,24 @@ inline void sCPU::op_ror_w() {
   regs.p.z = rd.w == 0;
 }
 
-inline void sCPU::op_trb_b() {
+inline void CPUcore::op_trb_b() {
   regs.p.z = (rd.l & regs.a.l) == 0;
   rd.l &= ~regs.a.l;
 }
 
-inline void sCPU::op_trb_w() {
+inline void CPUcore::op_trb_w() {
   regs.p.z = (rd.w & regs.a.w) == 0;
   rd.w &= ~regs.a.w;
 }
 
-inline void sCPU::op_tsb_b() {
+inline void CPUcore::op_tsb_b() {
   regs.p.z = (rd.l & regs.a.l) == 0;
   rd.l |= regs.a.l;
 }
 
-inline void sCPU::op_tsb_w() {
+inline void CPUcore::op_tsb_w() {
   regs.p.z = (rd.w & regs.a.w) == 0;
   rd.w |= regs.a.w;
 }
+#endif
 
-#endif //ifdef SCPU_CPP

src/cpu/core/opcode_functions.bpp

@@ -0,0 +1,13 @@
+//opcode_functions.cpp was generated via bpp -> opcode_functions.bpp
+
+@global class CPUcore
+@global lc last_cycle();
+@global wai regs.wai
+
+@include "opcode_read.bpp"
+@include "opcode_write.bpp"
+@include "opcode_rmw.bpp"
+@include "opcode_pc.bpp"
+@include "opcode_misc.bpp"
+
+@include "opcode_list.bpp"

src/cpu/core/opcode_headers.bpp

@@ -0,0 +1,386 @@
+//===============
+//opcode_read.bpp
+//===============
+
+@macro op_read_const(name)
+void op_{name}_const_b();
+void op_{name}_const_w();
+@endmacro
+
+@macro op_read_bit_const()
+void op_bit_const_b();
+void op_bit_const_w();
+@endmacro
+
+@macro op_read_addr(name)
+void op_{name}_addr_b();
+void op_{name}_addr_w();
+@endmacro
+
+@macro op_read_addrx(name)
+void op_{name}_addrx_b();
+void op_{name}_addrx_w();
+@endmacro
+
+@macro op_read_addry(name)
+void op_{name}_addry_b();
+void op_{name}_addry_w();
+@endmacro
+
+@macro op_read_long(name)
+void op_{name}_long_b();
+void op_{name}_long_w();
+@endmacro
+
+@macro op_read_longx(name)
+void op_{name}_longx_b();
+void op_{name}_longx_w();
+@endmacro
+
+@macro op_read_dp(name)
+void op_{name}_dp_b();
+void op_{name}_dp_w();
+@endmacro
+
+@macro op_read_dpr(name, r)
+void op_{name}_dpr_b();
+void op_{name}_dpr_w();
+@endmacro
+
+@macro op_read_idp(name)
+void op_{name}_idp_b();
+void op_{name}_idp_w();
+@endmacro
+
+@macro op_read_idpx(name)
+void op_{name}_idpx_b();
+void op_{name}_idpx_w();
+@endmacro
+
+@macro op_read_idpy(name)
+void op_{name}_idpy_b();
+void op_{name}_idpy_w();
+@endmacro
+
+@macro op_read_ildp(name)
+void op_{name}_ildp_b();
+void op_{name}_ildp_w();
+@endmacro
+
+@macro op_read_ildpy(name)
+void op_{name}_ildpy_b();
+void op_{name}_ildpy_w();
+@endmacro
+
+@macro op_read_sr(name)
+void op_{name}_sr_b();
+void op_{name}_sr_w();
+@endmacro
+
+@macro op_read_isry(name)
+void op_{name}_isry_b();
+void op_{name}_isry_w();
+@endmacro
+
+//================
+//opcode_write.bpp
+//================
+
+@macro op_store_addr(name, r)
+void op_{name}_addr_b();
+void op_{name}_addr_w();
+@endmacro
+
+@macro op_store_addrr(name, suffix, r, index)
+void op_{name}_addr{suffix}_b();
+void op_{name}_addr{suffix}_w();
+@endmacro
+
+@macro op_store_longr(name, suffix, index)
+void op_{name}_long{suffix}_b();
+void op_{name}_long{suffix}_w();
+@endmacro
+
+@macro op_store_dp(name, r)
+void op_{name}_dp_b();
+void op_{name}_dp_w();
+@endmacro
+
+@macro op_store_dpr(name, r, index)
+void op_{name}_dpr_b();
+void op_{name}_dpr_w();
+@endmacro
+
+@macro op_sta_idp()
+void op_sta_idp_b();
+void op_sta_idp_w();
+@endmacro
+
+@macro op_sta_ildp()
+void op_sta_ildp_b();
+void op_sta_ildp_w();
+@endmacro
+
+@macro op_sta_idpx()
+void op_sta_idpx_b();
+void op_sta_idpx_w();
+@endmacro
+
+@macro op_sta_idpy()
+void op_sta_idpy_b();
+void op_sta_idpy_w();
+@endmacro
+
+@macro op_sta_ildpy()
+void op_sta_ildpy_b();
+void op_sta_ildpy_w();
+@endmacro
+
+@macro op_sta_sr()
+void op_sta_sr_b();
+void op_sta_sr_w();
+@endmacro
+
+@macro op_sta_isry()
+void op_sta_isry_b();
+void op_sta_isry_w();
+@endmacro
+
+//==============
+//opcode_rmw.bpp
+//==============
+
+@macro op_adjust(name, r, op)
+void op_{name}_imm_b();
+void op_{name}_imm_w();
+@endmacro
+
+@macro op_asl()
+void op_asl_imm_b();
+void op_asl_imm_w();
+@endmacro
+
+@macro op_lsr()
+void op_lsr_imm_b();
+void op_lsr_imm_w();
+@endmacro
+
+@macro op_rol()
+void op_rol_imm_b();
+void op_rol_imm_w();
+@endmacro
+
+@macro op_ror()
+void op_ror_imm_b();
+void op_ror_imm_w();
+@endmacro
+
+@macro op_adjust_addr(name)
+void op_{name}_addr_b();
+void op_{name}_addr_w();
+@endmacro
+
+@macro op_adjust_addrx(name)
+void op_{name}_addrx_b();
+void op_{name}_addrx_w();
+@endmacro
+
+@macro op_adjust_dp(name)
+void op_{name}_dp_b();
+void op_{name}_dp_w();
+@endmacro
+
+@macro op_adjust_dpx(name)
+void op_{name}_dpx_b();
+void op_{name}_dpx_w();
+@endmacro
+
+//=============
+//opcode_pc.bpp
+//=============
+
+@macro op_branch(name, condition)
+void op_{name}();
+@endmacro
+
+@macro op_bra()
+void op_bra();
+@endmacro
+
+@macro op_brl()
+void op_brl();
+@endmacro
+
+@macro op_jmp_addr()
+void op_jmp_addr();
+@endmacro
+
+@macro op_jmp_long()
+void op_jmp_long();
+@endmacro
+
+@macro op_jmp_iaddr()
+void op_jmp_iaddr();
+@endmacro
+
+@macro op_jmp_iaddrx()
+void op_jmp_iaddrx();
+@endmacro
+
+@macro op_jmp_iladdr()
+void op_jmp_iladdr();
+@endmacro
+
+@macro op_jsr_addr()
+void op_jsr_addr();
+@endmacro
+
+@macro op_jsr_long()
+void op_jsr_long_e();
+void op_jsr_long_n();
+@endmacro
+
+@macro op_jsr_iaddrx()
+void op_jsr_iaddrx_e();
+void op_jsr_iaddrx_n();
+@endmacro
+
+@macro op_rti()
+void op_rti_e();
+void op_rti_n();
+@endmacro
+
+@macro op_rts()
+void op_rts();
+@endmacro
+
+@macro op_rtl()
+void op_rtl_e();
+void op_rtl_n();
+@endmacro
+
+//===============
+//opcode_misc.bpp
+//===============
+
+@macro op_nop()
+void op_nop();
+@endmacro
+
+@macro op_wdm()
+void op_wdm();
+@endmacro
+
+@macro op_xba()
+void op_xba();
+@endmacro
+
+@macro op_move(name, op)
+void op_{name}_b();
+void op_{name}_w();
+@endmacro
+
+@macro op_interrupt(name, vectorE, vectorN)
+void op_{name}_e();
+void op_{name}_n();
+@endmacro
+
+@macro op_stp()
+void op_stp();
+@endmacro
+
+@macro op_wai()
+void op_wai();
+@endmacro
+
+@macro op_xce()
+void op_xce();
+@endmacro
+
+@macro op_flag(name, rule)
+void op_{name}();
+@endmacro
+
+@macro op_pflag(name, op)
+void op_{name}_e();
+void op_{name}_n();
+@endmacro
+
+@macro op_transfer(name, from, to)
+void op_{name}_b();
+void op_{name}_w();
+@endmacro
+
+@macro op_transfer_word(name, from, to)
+void op_{name}();
+@endmacro
+
+@macro op_tcs()
+void op_tcs_e();
+void op_tcs_n();
+@endmacro
+
+@macro op_tsc()
+void op_tsc_e();
+void op_tsc_n();
+@endmacro
+
+@macro op_tsx()
+void op_tsx_b();
+void op_tsx_w();
+@endmacro
+
+@macro op_txs()
+void op_txs_e();
+void op_txs_n();
+@endmacro
+
+@macro op_push(name, r)
+void op_{name}_b();
+void op_{name}_w();
+@endmacro
+
+@macro op_phd()
+void op_phd_e();
+void op_phd_n();
+@endmacro
+
+@macro op_push_byte(name, r)
+void op_{name}();
+@endmacro
+
+@macro op_pull(name, r)
+void op_{name}_b();
+void op_{name}_w();
+@endmacro
+
+@macro op_pld()
+void op_pld_e();
+void op_pld_n();
+@endmacro
+
+@macro op_plb()
+void op_plb();
+@endmacro
+
+@macro op_plp()
+void op_plp_e();
+void op_plp_n();
+@endmacro
+
+@macro op_pea()
+void op_pea_e();
+void op_pea_n();
+@endmacro
+
+@macro op_pei()
+void op_pei_e();
+void op_pei_n();
+@endmacro
+
+@macro op_per()
+void op_per_e();
+void op_per_n();
+@endmacro
+
+@include "opcode_list.bpp"

src/cpu/core/opcode_headers.hpp

@@ -0,0 +1,892 @@
+//===============
+//opcode_read.bpp
+//===============
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+//================
+//opcode_write.bpp
+//================
+
+
+
+
+
+
+
+
+
+
+
+
+
+//==============
+//opcode_rmw.bpp
+//==============
+
+
+
+
+
+
+
+
+
+
+//=============
+//opcode_pc.bpp
+//=============
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+//===============
+//opcode_misc.bpp
+//===============
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+//===============
+//opcode_read.bpp
+//===============
+
+void op_adc_const_b();
+void op_adc_const_w();
+
+void op_and_const_b();
+void op_and_const_w();
+
+void op_cmp_const_b();
+void op_cmp_const_w();
+
+void op_cpx_const_b();
+void op_cpx_const_w();
+
+void op_cpy_const_b();
+void op_cpy_const_w();
+
+void op_eor_const_b();
+void op_eor_const_w();
+
+void op_lda_const_b();
+void op_lda_const_w();
+
+void op_ldx_const_b();
+void op_ldx_const_w();
+
+void op_ldy_const_b();
+void op_ldy_const_w();
+
+void op_ora_const_b();
+void op_ora_const_w();
+
+void op_sbc_const_b();
+void op_sbc_const_w();
+
+
+void op_bit_const_b();
+void op_bit_const_w();
+
+
+void op_adc_addr_b();
+void op_adc_addr_w();
+
+void op_and_addr_b();
+void op_and_addr_w();
+
+void op_bit_addr_b();
+void op_bit_addr_w();
+
+void op_cmp_addr_b();
+void op_cmp_addr_w();
+
+void op_cpx_addr_b();
+void op_cpx_addr_w();
+
+void op_cpy_addr_b();
+void op_cpy_addr_w();
+
+void op_eor_addr_b();
+void op_eor_addr_w();
+
+void op_lda_addr_b();
+void op_lda_addr_w();
+
+void op_ldx_addr_b();
+void op_ldx_addr_w();
+
+void op_ldy_addr_b();
+void op_ldy_addr_w();
+
+void op_ora_addr_b();
+void op_ora_addr_w();
+
+void op_sbc_addr_b();
+void op_sbc_addr_w();
+
+
+void op_adc_addrx_b();
+void op_adc_addrx_w();
+
+void op_and_addrx_b();
+void op_and_addrx_w();
+
+void op_bit_addrx_b();
+void op_bit_addrx_w();
+
+void op_cmp_addrx_b();
+void op_cmp_addrx_w();
+
+void op_eor_addrx_b();
+void op_eor_addrx_w();
+
+void op_lda_addrx_b();
+void op_lda_addrx_w();
+
+void op_ldy_addrx_b();
+void op_ldy_addrx_w();
+
+void op_ora_addrx_b();
+void op_ora_addrx_w();
+
+void op_sbc_addrx_b();
+void op_sbc_addrx_w();
+
+
+void op_adc_addry_b();
+void op_adc_addry_w();
+
+void op_and_addry_b();
+void op_and_addry_w();
+
+void op_cmp_addry_b();
+void op_cmp_addry_w();
+
+void op_eor_addry_b();
+void op_eor_addry_w();
+
+void op_lda_addry_b();
+void op_lda_addry_w();
+
+void op_ldx_addry_b();
+void op_ldx_addry_w();
+
+void op_ora_addry_b();
+void op_ora_addry_w();
+
+void op_sbc_addry_b();
+void op_sbc_addry_w();
+
+
+void op_adc_long_b();
+void op_adc_long_w();
+
+void op_and_long_b();
+void op_and_long_w();
+
+void op_cmp_long_b();
+void op_cmp_long_w();
+
+void op_eor_long_b();
+void op_eor_long_w();
+
+void op_lda_long_b();
+void op_lda_long_w();
+
+void op_ora_long_b();
+void op_ora_long_w();
+
+void op_sbc_long_b();
+void op_sbc_long_w();
+
+
+void op_adc_longx_b();
+void op_adc_longx_w();
+
+void op_and_longx_b();
+void op_and_longx_w();
+
+void op_cmp_longx_b();
+void op_cmp_longx_w();
+
+void op_eor_longx_b();
+void op_eor_longx_w();
+
+void op_lda_longx_b();
+void op_lda_longx_w();
+
+void op_ora_longx_b();
+void op_ora_longx_w();
+
+void op_sbc_longx_b();
+void op_sbc_longx_w();
+
+
+void op_adc_dp_b();
+void op_adc_dp_w();
+
+void op_and_dp_b();
+void op_and_dp_w();
+
+void op_bit_dp_b();
+void op_bit_dp_w();
+
+void op_cmp_dp_b();
+void op_cmp_dp_w();
+
+void op_cpx_dp_b();
+void op_cpx_dp_w();
+
+void op_cpy_dp_b();
+void op_cpy_dp_w();
+
+void op_eor_dp_b();
+void op_eor_dp_w();
+
+void op_lda_dp_b();
+void op_lda_dp_w();
+
+void op_ldx_dp_b();
+void op_ldx_dp_w();
+
+void op_ldy_dp_b();
+void op_ldy_dp_w();
+
+void op_ora_dp_b();
+void op_ora_dp_w();
+
+void op_sbc_dp_b();
+void op_sbc_dp_w();
+
+
+void op_adc_dpr_b();
+void op_adc_dpr_w();
+
+void op_and_dpr_b();
+void op_and_dpr_w();
+
+void op_bit_dpr_b();
+void op_bit_dpr_w();
+
+void op_cmp_dpr_b();
+void op_cmp_dpr_w();
+
+void op_eor_dpr_b();
+void op_eor_dpr_w();
+
+void op_lda_dpr_b();
+void op_lda_dpr_w();
+
+void op_ldx_dpr_b();
+void op_ldx_dpr_w();
+
+void op_ldy_dpr_b();
+void op_ldy_dpr_w();
+
+void op_ora_dpr_b();
+void op_ora_dpr_w();
+
+void op_sbc_dpr_b();
+void op_sbc_dpr_w();
+
+
+void op_adc_idp_b();
+void op_adc_idp_w();
+
+void op_and_idp_b();
+void op_and_idp_w();
+
+void op_cmp_idp_b();
+void op_cmp_idp_w();
+
+void op_eor_idp_b();
+void op_eor_idp_w();
+
+void op_lda_idp_b();
+void op_lda_idp_w();
+
+void op_ora_idp_b();
+void op_ora_idp_w();
+
+void op_sbc_idp_b();
+void op_sbc_idp_w();
+
+
+void op_adc_idpx_b();
+void op_adc_idpx_w();
+
+void op_and_idpx_b();
+void op_and_idpx_w();
+
+void op_cmp_idpx_b();
+void op_cmp_idpx_w();
+
+void op_eor_idpx_b();
+void op_eor_idpx_w();
+
+void op_lda_idpx_b();
+void op_lda_idpx_w();
+
+void op_ora_idpx_b();
+void op_ora_idpx_w();
+
+void op_sbc_idpx_b();
+void op_sbc_idpx_w();
+
+
+void op_adc_idpy_b();
+void op_adc_idpy_w();
+
+void op_and_idpy_b();
+void op_and_idpy_w();
+
+void op_cmp_idpy_b();
+void op_cmp_idpy_w();
+
+void op_eor_idpy_b();
+void op_eor_idpy_w();
+
+void op_lda_idpy_b();
+void op_lda_idpy_w();
+
+void op_ora_idpy_b();
+void op_ora_idpy_w();
+
+void op_sbc_idpy_b();
+void op_sbc_idpy_w();
+
+
+void op_adc_ildp_b();
+void op_adc_ildp_w();
+
+void op_and_ildp_b();
+void op_and_ildp_w();
+
+void op_cmp_ildp_b();
+void op_cmp_ildp_w();
+
+void op_eor_ildp_b();
+void op_eor_ildp_w();
+
+void op_lda_ildp_b();
+void op_lda_ildp_w();
+
+void op_ora_ildp_b();
+void op_ora_ildp_w();
+
+void op_sbc_ildp_b();
+void op_sbc_ildp_w();
+
+
+void op_adc_ildpy_b();
+void op_adc_ildpy_w();
+
+void op_and_ildpy_b();
+void op_and_ildpy_w();
+
+void op_cmp_ildpy_b();
+void op_cmp_ildpy_w();
+
+void op_eor_ildpy_b();
+void op_eor_ildpy_w();
+
+void op_lda_ildpy_b();
+void op_lda_ildpy_w();
+
+void op_ora_ildpy_b();
+void op_ora_ildpy_w();
+
+void op_sbc_ildpy_b();
+void op_sbc_ildpy_w();
+
+
+void op_adc_sr_b();
+void op_adc_sr_w();
+
+void op_and_sr_b();
+void op_and_sr_w();
+
+void op_cmp_sr_b();
+void op_cmp_sr_w();
+
+void op_eor_sr_b();
+void op_eor_sr_w();
+
+void op_lda_sr_b();
+void op_lda_sr_w();
+
+void op_ora_sr_b();
+void op_ora_sr_w();
+
+void op_sbc_sr_b();
+void op_sbc_sr_w();
+
+
+void op_adc_isry_b();
+void op_adc_isry_w();
+
+void op_and_isry_b();
+void op_and_isry_w();
+
+void op_cmp_isry_b();
+void op_cmp_isry_w();
+
+void op_eor_isry_b();
+void op_eor_isry_w();
+
+void op_lda_isry_b();
+void op_lda_isry_w();
+
+void op_ora_isry_b();
+void op_ora_isry_w();
+
+void op_sbc_isry_b();
+void op_sbc_isry_w();
+
+
+//================
+//opcode_write.bpp
+//================
+
+void op_sta_addr_b();
+void op_sta_addr_w();
+
+void op_stx_addr_b();
+void op_stx_addr_w();
+
+void op_sty_addr_b();
+void op_sty_addr_w();
+
+void op_stz_addr_b();
+void op_stz_addr_w();
+
+
+void op_sta_addrx_b();
+void op_sta_addrx_w();
+
+void op_sta_addry_b();
+void op_sta_addry_w();
+
+void op_stz_addrx_b();
+void op_stz_addrx_w();
+
+
+void op_sta_long_b();
+void op_sta_long_w();
+
+void op_sta_longx_b();
+void op_sta_longx_w();
+
+
+void op_sta_dp_b();
+void op_sta_dp_w();
+
+void op_stx_dp_b();
+void op_stx_dp_w();
+
+void op_sty_dp_b();
+void op_sty_dp_w();
+
+void op_stz_dp_b();
+void op_stz_dp_w();
+
+
+void op_sta_dpr_b();
+void op_sta_dpr_w();
+
+void op_stx_dpr_b();
+void op_stx_dpr_w();
+
+void op_sty_dpr_b();
+void op_sty_dpr_w();
+
+void op_stz_dpr_b();
+void op_stz_dpr_w();
+
+
+void op_sta_idp_b();
+void op_sta_idp_w();
+
+void op_sta_ildp_b();
+void op_sta_ildp_w();
+
+void op_sta_idpx_b();
+void op_sta_idpx_w();
+
+void op_sta_idpy_b();
+void op_sta_idpy_w();
+
+void op_sta_ildpy_b();
+void op_sta_ildpy_w();
+
+void op_sta_sr_b();
+void op_sta_sr_w();
+
+void op_sta_isry_b();
+void op_sta_isry_w();
+
+
+//==============
+//opcode_rmw.bpp
+//==============
+
+void op_inc_imm_b();
+void op_inc_imm_w();
+
+void op_inx_imm_b();
+void op_inx_imm_w();
+
+void op_iny_imm_b();
+void op_iny_imm_w();
+
+void op_dec_imm_b();
+void op_dec_imm_w();
+
+void op_dex_imm_b();
+void op_dex_imm_w();
+
+void op_dey_imm_b();
+void op_dey_imm_w();
+
+
+void op_asl_imm_b();
+void op_asl_imm_w();
+
+void op_lsr_imm_b();
+void op_lsr_imm_w();
+
+void op_rol_imm_b();
+void op_rol_imm_w();
+
+void op_ror_imm_b();
+void op_ror_imm_w();
+
+
+void op_inc_addr_b();
+void op_inc_addr_w();
+
+void op_dec_addr_b();
+void op_dec_addr_w();
+
+void op_asl_addr_b();
+void op_asl_addr_w();
+
+void op_lsr_addr_b();
+void op_lsr_addr_w();
+
+void op_rol_addr_b();
+void op_rol_addr_w();
+
+void op_ror_addr_b();
+void op_ror_addr_w();
+
+void op_trb_addr_b();
+void op_trb_addr_w();
+
+void op_tsb_addr_b();
+void op_tsb_addr_w();
+
+
+void op_inc_addrx_b();
+void op_inc_addrx_w();
+
+void op_dec_addrx_b();
+void op_dec_addrx_w();
+
+void op_asl_addrx_b();
+void op_asl_addrx_w();
+
+void op_lsr_addrx_b();
+void op_lsr_addrx_w();
+
+void op_rol_addrx_b();
+void op_rol_addrx_w();
+
+void op_ror_addrx_b();
+void op_ror_addrx_w();
+
+
+void op_inc_dp_b();
+void op_inc_dp_w();
+
+void op_dec_dp_b();
+void op_dec_dp_w();
+
+void op_asl_dp_b();
+void op_asl_dp_w();
+
+void op_lsr_dp_b();
+void op_lsr_dp_w();
+
+void op_rol_dp_b();
+void op_rol_dp_w();
+
+void op_ror_dp_b();
+void op_ror_dp_w();
+
+void op_trb_dp_b();
+void op_trb_dp_w();
+
+void op_tsb_dp_b();
+void op_tsb_dp_w();
+
+
+void op_inc_dpx_b();
+void op_inc_dpx_w();
+
+void op_dec_dpx_b();
+void op_dec_dpx_w();
+
+void op_asl_dpx_b();
+void op_asl_dpx_w();
+
+void op_lsr_dpx_b();
+void op_lsr_dpx_w();
+
+void op_rol_dpx_b();
+void op_rol_dpx_w();
+
+void op_ror_dpx_b();
+void op_ror_dpx_w();
+
+
+//=============
+//opcode_pc.bpp
+//=============
+
+void op_bcc();
+
+void op_bcs();
+
+void op_bne();
+
+void op_beq();
+
+void op_bpl();
+
+void op_bmi();
+
+void op_bvc();
+
+void op_bvs();
+
+
+void op_bra();
+
+void op_brl();
+
+void op_jmp_addr();
+
+void op_jmp_long();
+
+void op_jmp_iaddr();
+
+void op_jmp_iaddrx();
+
+void op_jmp_iladdr();
+
+void op_jsr_addr();
+
+void op_jsr_long_e();
+void op_jsr_long_n();
+
+void op_jsr_iaddrx_e();
+void op_jsr_iaddrx_n();
+
+void op_rti_e();
+void op_rti_n();
+
+void op_rts();
+
+void op_rtl_e();
+void op_rtl_n();
+
+
+//===============
+//opcode_misc.bpp
+//===============
+
+void op_nop();
+
+void op_wdm();
+
+void op_xba();
+
+
+void op_mvn_b();
+void op_mvn_w();
+
+void op_mvp_b();
+void op_mvp_w();
+
+
+void op_brk_e();
+void op_brk_n();
+
+void op_cop_e();
+void op_cop_n();
+
+
+void op_stp();
+
+void op_wai();
+
+void op_xce();
+
+
+void op_clc();
+
+void op_cld();
+
+void op_cli();
+
+void op_clv();
+
+void op_sec();
+
+void op_sed();
+
+void op_sei();
+
+
+void op_rep_e();
+void op_rep_n();
+
+void op_sep_e();
+void op_sep_n();
+
+
+void op_tax_b();
+void op_tax_w();
+
+void op_tay_b();
+void op_tay_w();
+
+void op_txa_b();
+void op_txa_w();
+
+void op_txy_b();
+void op_txy_w();
+
+void op_tya_b();
+void op_tya_w();
+
+void op_tyx_b();
+void op_tyx_w();
+
+
+void op_tcd();
+
+void op_tdc();
+
+
+void op_tcs_e();
+void op_tcs_n();
+
+void op_tsc_e();
+void op_tsc_n();
+
+void op_tsx_b();
+void op_tsx_w();
+
+void op_txs_e();
+void op_txs_n();
+
+
+void op_pha_b();
+void op_pha_w();
+
+void op_phx_b();
+void op_phx_w();
+
+void op_phy_b();
+void op_phy_w();
+
+void op_phd_e();
+void op_phd_n();
+
+void op_phb();
+
+void op_phk();
+
+void op_php();
+
+
+void op_pla_b();
+void op_pla_w();
+
+void op_plx_b();
+void op_plx_w();
+
+void op_ply_b();
+void op_ply_w();
+
+void op_pld_e();
+void op_pld_n();
+
+void op_plb();
+
+void op_plp_e();
+void op_plp_n();
+
+
+void op_pea_e();
+void op_pea_n();
+
+void op_pei_e();
+void op_pei_n();
+
+void op_per_e();
+void op_per_n();
+
+
+

src/cpu/core/opcode_list.bpp

@@ -0,0 +1,317 @@
+//===============
+//opcode_read.bpp
+//===============
+
+@op_read_const(adc)
+@op_read_const(and)
+@op_read_const(cmp)
+@op_read_const(cpx)
+@op_read_const(cpy)
+@op_read_const(eor)
+@op_read_const(lda)
+@op_read_const(ldx)
+@op_read_const(ldy)
+@op_read_const(ora)
+@op_read_const(sbc)
+
+@op_read_bit_const()
+
+@op_read_addr(adc)
+@op_read_addr(and)
+@op_read_addr(bit)
+@op_read_addr(cmp)
+@op_read_addr(cpx)
+@op_read_addr(cpy)
+@op_read_addr(eor)
+@op_read_addr(lda)
+@op_read_addr(ldx)
+@op_read_addr(ldy)
+@op_read_addr(ora)
+@op_read_addr(sbc)
+
+@op_read_addrx(adc)
+@op_read_addrx(and)
+@op_read_addrx(bit)
+@op_read_addrx(cmp)
+@op_read_addrx(eor)
+@op_read_addrx(lda)
+@op_read_addrx(ldy)
+@op_read_addrx(ora)
+@op_read_addrx(sbc)
+
+@op_read_addry(adc)
+@op_read_addry(and)
+@op_read_addry(cmp)
+@op_read_addry(eor)
+@op_read_addry(lda)
+@op_read_addry(ldx)
+@op_read_addry(ora)
+@op_read_addry(sbc)
+
+@op_read_long(adc)
+@op_read_long(and)
+@op_read_long(cmp)
+@op_read_long(eor)
+@op_read_long(lda)
+@op_read_long(ora)
+@op_read_long(sbc)
+
+@op_read_longx(adc)
+@op_read_longx(and)
+@op_read_longx(cmp)
+@op_read_longx(eor)
+@op_read_longx(lda)
+@op_read_longx(ora)
+@op_read_longx(sbc)
+
+@op_read_dp(adc)
+@op_read_dp(and)
+@op_read_dp(bit)
+@op_read_dp(cmp)
+@op_read_dp(cpx)
+@op_read_dp(cpy)
+@op_read_dp(eor)
+@op_read_dp(lda)
+@op_read_dp(ldx)
+@op_read_dp(ldy)
+@op_read_dp(ora)
+@op_read_dp(sbc)
+
+@op_read_dpr(adc, x)
+@op_read_dpr(and, x)
+@op_read_dpr(bit, x)
+@op_read_dpr(cmp, x)
+@op_read_dpr(eor, x)
+@op_read_dpr(lda, x)
+@op_read_dpr(ldx, y)
+@op_read_dpr(ldy, x)
+@op_read_dpr(ora, x)
+@op_read_dpr(sbc, x)
+
+@op_read_idp(adc)
+@op_read_idp(and)
+@op_read_idp(cmp)
+@op_read_idp(eor)
+@op_read_idp(lda)
+@op_read_idp(ora)
+@op_read_idp(sbc)
+
+@op_read_idpx(adc)
+@op_read_idpx(and)
+@op_read_idpx(cmp)
+@op_read_idpx(eor)
+@op_read_idpx(lda)
+@op_read_idpx(ora)
+@op_read_idpx(sbc)
+
+@op_read_idpy(adc)
+@op_read_idpy(and)
+@op_read_idpy(cmp)
+@op_read_idpy(eor)
+@op_read_idpy(lda)
+@op_read_idpy(ora)
+@op_read_idpy(sbc)
+
+@op_read_ildp(adc)
+@op_read_ildp(and)
+@op_read_ildp(cmp)
+@op_read_ildp(eor)
+@op_read_ildp(lda)
+@op_read_ildp(ora)
+@op_read_ildp(sbc)
+
+@op_read_ildpy(adc)
+@op_read_ildpy(and)
+@op_read_ildpy(cmp)
+@op_read_ildpy(eor)
+@op_read_ildpy(lda)
+@op_read_ildpy(ora)
+@op_read_ildpy(sbc)
+
+@op_read_sr(adc)
+@op_read_sr(and)
+@op_read_sr(cmp)
+@op_read_sr(eor)
+@op_read_sr(lda)
+@op_read_sr(ora)
+@op_read_sr(sbc)
+
+@op_read_isry(adc)
+@op_read_isry(and)
+@op_read_isry(cmp)
+@op_read_isry(eor)
+@op_read_isry(lda)
+@op_read_isry(ora)
+@op_read_isry(sbc)
+
+//================
+//opcode_write.bpp
+//================
+
+@op_store_addr(sta, regs.a.w)
+@op_store_addr(stx, regs.x.w)
+@op_store_addr(sty, regs.y.w)
+@op_store_addr(stz, 0x0000)
+
+@op_store_addrr(sta, x, regs.a.w, regs.x.w)
+@op_store_addrr(sta, y, regs.a.w, regs.y.w)
+@op_store_addrr(stz, x, 0x0000,   regs.x.w)
+
+@op_store_longr(sta, ,  0x0000)
+@op_store_longr(sta, x, regs.x.w)
+
+@op_store_dp(sta, regs.a.w)
+@op_store_dp(stx, regs.x.w)
+@op_store_dp(sty, regs.y.w)
+@op_store_dp(stz, 0x0000)
+
+@op_store_dpr(sta, regs.a.w, x)
+@op_store_dpr(stx, regs.x.w, y)
+@op_store_dpr(sty, regs.y.w, x)
+@op_store_dpr(stz, 0x0000,   x)
+
+@op_sta_idp()
+@op_sta_ildp()
+@op_sta_idpx()
+@op_sta_idpy()
+@op_sta_ildpy()
+@op_sta_sr()
+@op_sta_isry()
+
+//==============
+//opcode_rmw.bpp
+//==============
+
+@op_adjust(inc, a, ++)
+@op_adjust(inx, x, ++)
+@op_adjust(iny, y, ++)
+@op_adjust(dec, a, --)
+@op_adjust(dex, x, --)
+@op_adjust(dey, y, --)
+
+@op_asl()
+@op_lsr()
+@op_rol()
+@op_ror()
+
+@op_adjust_addr(inc)
+@op_adjust_addr(dec)
+@op_adjust_addr(asl)
+@op_adjust_addr(lsr)
+@op_adjust_addr(rol)
+@op_adjust_addr(ror)
+@op_adjust_addr(trb)
+@op_adjust_addr(tsb)
+
+@op_adjust_addrx(inc)
+@op_adjust_addrx(dec)
+@op_adjust_addrx(asl)
+@op_adjust_addrx(lsr)
+@op_adjust_addrx(rol)
+@op_adjust_addrx(ror)
+
+@op_adjust_dp(inc)
+@op_adjust_dp(dec)
+@op_adjust_dp(asl)
+@op_adjust_dp(lsr)
+@op_adjust_dp(rol)
+@op_adjust_dp(ror)
+@op_adjust_dp(trb)
+@op_adjust_dp(tsb)
+
+@op_adjust_dpx(inc)
+@op_adjust_dpx(dec)
+@op_adjust_dpx(asl)
+@op_adjust_dpx(lsr)
+@op_adjust_dpx(rol)
+@op_adjust_dpx(ror)
+
+//=============
+//opcode_pc.bpp
+//=============
+
+@op_branch(bcc, !regs.p.c)
+@op_branch(bcs,  regs.p.c)
+@op_branch(bne, !regs.p.z)
+@op_branch(beq,  regs.p.z)
+@op_branch(bpl, !regs.p.n)
+@op_branch(bmi,  regs.p.n)
+@op_branch(bvc, !regs.p.v)
+@op_branch(bvs,  regs.p.v)
+
+@op_bra()
+@op_brl()
+@op_jmp_addr()
+@op_jmp_long()
+@op_jmp_iaddr()
+@op_jmp_iaddrx()
+@op_jmp_iladdr()
+@op_jsr_addr()
+@op_jsr_long()
+@op_jsr_iaddrx()
+@op_rti()
+@op_rts()
+@op_rtl()
+
+//===============
+//opcode_misc.bpp
+//===============
+
+@op_nop()
+@op_wdm()
+@op_xba()
+
+@op_move(mvn, ++)
+@op_move(mvp, --)
+
+@op_interrupt(brk, 0xfffe, 0xffe6)
+@op_interrupt(cop, 0xfff4, 0xffe4)
+
+@op_stp()
+@op_wai()
+@op_xce()
+
+@op_flag(clc, regs.p.c = 0)
+@op_flag(cld, regs.p.d = 0)
+@op_flag(cli, regs.p.i = 0)
+@op_flag(clv, regs.p.v = 0)
+@op_flag(sec, regs.p.c = 1)
+@op_flag(sed, regs.p.d = 1)
+@op_flag(sei, regs.p.i = 1)
+
+@op_pflag(rep, &=~)
+@op_pflag(sep, |=)
+
+@op_transfer(tax, a, x)
+@op_transfer(tay, a, y)
+@op_transfer(txa, x, a)
+@op_transfer(txy, x, y)
+@op_transfer(tya, y, a)
+@op_transfer(tyx, y, x)
+
+@op_transfer_word(tcd, a, d)
+@op_transfer_word(tdc, d, a)
+
+@op_tcs()
+@op_tsc()
+@op_tsx()
+@op_txs()
+
+@op_push(pha, a)
+@op_push(phx, x)
+@op_push(phy, y)
+@op_phd()
+@op_push_byte(phb, regs.db)
+@op_push_byte(phk, regs.pc.b)
+@op_push_byte(php, regs.p)
+
+@op_pull(pla, a)
+@op_pull(plx, x)
+@op_pull(ply, y)
+@op_pld()
+@op_plb()
+@op_plp()
+
+@op_pea()
+@op_pei()
+@op_per()

src/cpu/core/opcode_misc.bpp

@@ -0,0 +1,397 @@
+@macro op_nop()
+  void {class}::op_nop() {
+{lc}op_io_irq();
+  }
+@endmacro
+
+@macro op_wdm()
+  void {class}::op_wdm() {
+{lc}op_readpc();
+  }
+@endmacro
+
+@macro op_xba()
+  void {class}::op_xba() {
+    op_io();
+{lc}op_io();
+    regs.a.l ^= regs.a.h;
+    regs.a.h ^= regs.a.l;
+    regs.a.l ^= regs.a.h;
+    regs.p.n = (regs.a.l & 0x80);
+    regs.p.z = (regs.a.l == 0);
+  }
+@endmacro
+
+@macro op_move(name, op)
+  void {class}::op_{name}_b() {
+    dp = op_readpc();
+    sp = op_readpc();
+    regs.db = dp;
+    rd.l = op_readlong((sp << 16) | regs.x.w);
+    op_writelong((dp << 16) | regs.y.w, rd.l);
+    op_io();
+    regs.x.l {op};
+    regs.y.l {op};
+{lc}op_io();
+    if(regs.a.w--) regs.pc.w -= 3;
+  }
+
+  void {class}::op_{name}_w() {
+    dp = op_readpc();
+    sp = op_readpc();
+    regs.db = dp;
+    rd.l = op_readlong((sp << 16) | regs.x.w);
+    op_writelong((dp << 16) | regs.y.w, rd.l);
+    op_io();
+    regs.x.w {op};
+    regs.y.w {op};
+{lc}op_io();
+    if(regs.a.w--) regs.pc.w -= 3;
+  }
+@endmacro
+
+@macro op_interrupt(name, vectorE, vectorN)
+  void {class}::op_{name}_e() {
+    op_readpc();
+    op_writestack(regs.pc.h);
+    op_writestack(regs.pc.l);
+    op_writestack(regs.p);
+    rd.l = op_readlong({vectorE} + 0);
+    regs.pc.b = 0;
+    regs.p.i = 1;
+    regs.p.d = 0;
+{lc}rd.h = op_readlong({vectorE} + 1);
+    regs.pc.w = rd.w;
+  }
+
+  void {class}::op_{name}_n() {
+    op_readpc();
+    op_writestack(regs.pc.b);
+    op_writestack(regs.pc.h);
+    op_writestack(regs.pc.l);
+    op_writestack(regs.p);
+    rd.l = op_readlong({vectorN} + 0);
+    regs.pc.b = 0x00;
+    regs.p.i = 1;
+    regs.p.d = 0;
+{lc}rd.h = op_readlong({vectorN} + 1);
+    regs.pc.w = rd.w;
+  }
+@endmacro
+
+@macro op_stp()
+  void {class}::op_stp() {
+    while({wai} = true) {
+{lc}  op_io();
+    }
+  }
+@endmacro
+
+@macro op_wai()
+  void {class}::op_wai() {
+    {wai} = true;
+    while({wai}) {
+{lc}  op_io();
+    }
+    op_io();
+  }
+@endmacro
+
+@macro op_xce()
+  void {class}::op_xce() {
+{lc}op_io_irq();
+    bool carry = regs.p.c;
+    regs.p.c = regs.e;
+    regs.e = carry;
+    if(regs.e) {
+      regs.p |= 0x30;
+      regs.s.h = 0x01;
+    }
+    if(regs.p.x) {
+      regs.x.h = 0x00;
+      regs.y.h = 0x00;
+    }
+    update_table();
+  }
+@endmacro
+
+@macro op_flag(name, rule)
+  void {class}::op_{name}() {
+{lc}op_io_irq();
+    {rule};
+  }
+@endmacro
+
+@macro op_pflag(name, op)
+  void {class}::op_{name}_e() {
+    rd.l = op_readpc();
+{lc}op_io();
+    regs.p {op} rd.l;
+    regs.p |= 0x30;
+    if(regs.p.x) {
+      regs.x.h = 0x00;
+      regs.y.h = 0x00;
+    }
+    update_table();
+  }
+
+  void {class}::op_{name}_n() {
+    rd.l = op_readpc();
+{lc}op_io();
+    regs.p {op} rd.l;
+    if(regs.p.x) {
+      regs.x.h = 0x00;
+      regs.y.h = 0x00;
+    }
+    update_table();
+  }
+@endmacro
+
+@macro op_transfer(name, from, to)
+  void {class}::op_{name}_b() {
+{lc}op_io_irq();
+    regs.{to}.l = regs.{from}.l;
+    regs.p.n = (regs.{to}.l & 0x80);
+    regs.p.z = (regs.{to}.l == 0);
+  }
+
+  void {class}::op_{name}_w() {
+{lc}op_io_irq();
+    regs.{to}.w = regs.{from}.w;
+    regs.p.n = (regs.{to}.w & 0x8000);
+    regs.p.z = (regs.{to}.w == 0);
+  }
+@endmacro
+
+@macro op_transfer_word(name, from, to)
+  void {class}::op_{name}() {
+{lc}op_io_irq();
+    regs.{to}.w = regs.{from}.w;
+    regs.p.n = (regs.{to}.w & 0x8000);
+    regs.p.z = (regs.{to}.w == 0);
+  }
+@endmacro
+
+@macro op_tcs()
+  void {class}::op_tcs_e() {
+{lc}op_io_irq();
+    regs.s.l = regs.a.l;
+  }
+
+  void {class}::op_tcs_n() {
+{lc}op_io_irq();
+    regs.s.w = regs.a.w;
+  }
+@endmacro
+
+@macro op_tsc()
+  void {class}::op_tsc_e() {
+{lc}op_io_irq();
+    regs.a.w = regs.s.w;
+    regs.p.n = (regs.a.l & 0x80);
+    regs.p.z = (regs.a.l == 0);
+  }
+
+  void {class}::op_tsc_n() {
+{lc}op_io_irq();
+    regs.a.w = regs.s.w;
+    regs.p.n = (regs.a.w & 0x8000);
+    regs.p.z = (regs.a.w == 0);
+  }
+@endmacro
+
+@macro op_tsx()
+  void {class}::op_tsx_b() {
+{lc}op_io_irq();
+    regs.x.l = regs.s.l;
+    regs.p.n = (regs.x.l & 0x80);
+    regs.p.z = (regs.x.l == 0);
+  }
+
+  void {class}::op_tsx_w() {
+{lc}op_io_irq();
+    regs.x.w = regs.s.w;
+    regs.p.n = (regs.x.w & 0x8000);
+    regs.p.z = (regs.x.w == 0);
+  }
+@endmacro
+
+@macro op_txs()
+  void {class}::op_txs_e() {
+{lc}op_io_irq();
+    regs.s.l = regs.x.l;
+  }
+
+  void {class}::op_txs_n() {
+{lc}op_io_irq();
+    regs.s.w = regs.x.w;
+  }
+@endmacro
+
+@macro op_push(name, r)
+  void {class}::op_{name}_b() {
+    op_io();
+{lc}op_writestack(regs.{r}.l);
+  }
+
+  void {class}::op_{name}_w() {
+    op_io();
+    op_writestack(regs.{r}.h);
+{lc}op_writestack(regs.{r}.l);
+  }
+@endmacro
+
+@macro op_phd()
+  void {class}::op_phd_e() {
+    op_io();
+    op_writestackn(regs.d.h);
+{lc}op_writestackn(regs.d.l);
+    regs.s.h = 0x01;
+  }
+
+  void {class}::op_phd_n() {
+    op_io();
+    op_writestackn(regs.d.h);
+{lc}op_writestackn(regs.d.l);
+  }
+@endmacro
+
+@macro op_push_byte(name, r)
+  void {class}::op_{name}() {
+    op_io();
+{lc}op_writestack({r});
+  }
+@endmacro
+
+@macro op_pull(name, r)
+  void {class}::op_{name}_b() {
+    op_io();
+    op_io();
+{lc}regs.{r}.l = op_readstack();
+    regs.p.n = (regs.{r}.l & 0x80);
+    regs.p.z = (regs.{r}.l == 0);
+  }
+
+  void {class}::op_{name}_w() {
+    op_io();
+    op_io();
+    regs.{r}.l = op_readstack();
+{lc}regs.{r}.h = op_readstack();
+    regs.p.n = (regs.{r}.w & 0x8000);
+    regs.p.z = (regs.{r}.w == 0);
+  }
+@endmacro
+
+@macro op_pld()
+  void {class}::op_pld_e() {
+    op_io();
+    op_io();
+    regs.d.l = op_readstackn();
+{lc}regs.d.h = op_readstackn();
+    regs.p.n = (regs.d.w & 0x8000);
+    regs.p.z = (regs.d.w == 0);
+    regs.s.h = 0x01;
+  }
+
+  void {class}::op_pld_n() {
+    op_io();
+    op_io();
+    regs.d.l = op_readstackn();
+{lc}regs.d.h = op_readstackn();
+    regs.p.n = (regs.d.w & 0x8000);
+    regs.p.z = (regs.d.w == 0);
+  }
+@endmacro
+
+@macro op_plb()
+  void {class}::op_plb() {
+    op_io();
+    op_io();
+{lc}regs.db = op_readstack();
+    regs.p.n = (regs.db & 0x80);
+    regs.p.z = (regs.db == 0);
+  }
+@endmacro
+
+@macro op_plp()
+  void {class}::op_plp_e() {
+    op_io();
+    op_io();
+{lc}regs.p = op_readstack() | 0x30;
+    if(regs.p.x) {
+      regs.x.h = 0x00;
+      regs.y.h = 0x00;
+    }
+    update_table();
+  }
+
+  void {class}::op_plp_n() {
+    op_io();
+    op_io();
+{lc}regs.p = op_readstack();
+    if(regs.p.x) {
+      regs.x.h = 0x00;
+      regs.y.h = 0x00;
+    }
+    update_table();
+  }
+@endmacro
+
+@macro op_pea()
+  void {class}::op_pea_e() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_writestackn(aa.h);
+{lc}op_writestackn(aa.l);
+    regs.s.h = 0x01;
+  }
+
+  void {class}::op_pea_n() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_writestackn(aa.h);
+{lc}op_writestackn(aa.l);
+  }
+@endmacro
+
+@macro op_pei()
+  void {class}::op_pei_e() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    op_writestackn(aa.h);
+{lc}op_writestackn(aa.l);
+    regs.s.h = 0x01;
+  }
+
+  void {class}::op_pei_n() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    op_writestackn(aa.h);
+{lc}op_writestackn(aa.l);
+  }
+@endmacro
+
+@macro op_per()
+  void {class}::op_per_e() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io();
+    rd.w = regs.pc.d + (int16_t)aa.w;
+    op_writestackn(rd.h);
+{lc}op_writestackn(rd.l);
+    regs.s.h = 0x01;
+  }
+
+  void {class}::op_per_n() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io();
+    rd.w = regs.pc.d + (int16_t)aa.w;
+    op_writestackn(rd.h);
+{lc}op_writestackn(rd.l);
+  }
+@endmacro

src/cpu/core/opcode_pc.bpp

@@ -0,0 +1,205 @@
+@macro op_branch(name, condition)
+  void {class}::op_{name}() {
+    if({condition} == false) {
+{lc}  rd.l = op_readpc();
+    } else {
+      rd.l = op_readpc();
+      aa.w = regs.pc.d + (int8_t)rd.l;
+      op_io_cond6(aa.w);
+{lc}  op_io();
+      regs.pc.w = aa.w;
+    }
+  }
+@endmacro
+
+@macro op_bra()
+  void {class}::op_bra() {
+    rd.l = op_readpc();
+    aa.w = regs.pc.d + (int8_t)rd.l;
+    op_io_cond6(aa.w);
+{lc}op_io();
+    regs.pc.w = aa.w;
+  }
+@endmacro
+
+@macro op_brl()
+  void {class}::op_brl() {
+    rd.l = op_readpc();
+    rd.h = op_readpc();
+{lc}op_io();
+    regs.pc.w = regs.pc.d + (int16_t)rd.w;
+  }
+@endmacro
+
+@macro op_jmp_addr()
+  void {class}::op_jmp_addr() {
+    rd.l = op_readpc();
+{lc}rd.h = op_readpc();
+    regs.pc.w = rd.w;
+  }
+@endmacro
+
+@macro op_jmp_long()
+  void {class}::op_jmp_long() {
+    rd.l = op_readpc();
+    rd.h = op_readpc();
+{lc}rd.b = op_readpc();
+    regs.pc.d = rd.d & 0xffffff;
+  }
+@endmacro
+
+@macro op_jmp_iaddr()
+  void {class}::op_jmp_iaddr() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    rd.l = op_readaddr(aa.w + 0);
+{lc}rd.h = op_readaddr(aa.w + 1);
+    regs.pc.w = rd.w;
+  }
+@endmacro
+
+@macro op_jmp_iaddrx()
+  void {class}::op_jmp_iaddrx() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io();
+    rd.l = op_readpbr(aa.w + regs.x.w + 0);
+{lc}rd.h = op_readpbr(aa.w + regs.x.w + 1);
+    regs.pc.w = rd.w;
+  }
+@endmacro
+
+@macro op_jmp_iladdr()
+  void {class}::op_jmp_iladdr() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    rd.l = op_readaddr(aa.w + 0);
+    rd.h = op_readaddr(aa.w + 1);
+{lc}rd.b = op_readaddr(aa.w + 2);
+    regs.pc.d = rd.d & 0xffffff;
+  }
+@endmacro
+
+@macro op_jsr_addr()
+  void {class}::op_jsr_addr() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io();
+    regs.pc.w--;
+    op_writestack(regs.pc.h);
+{lc}op_writestack(regs.pc.l);
+    regs.pc.w = aa.w;
+  }
+@endmacro
+
+@macro op_jsr_long()
+  void {class}::op_jsr_long_e() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_writestackn(regs.pc.b);
+    op_io();
+    aa.b = op_readpc();
+    regs.pc.w--;
+    op_writestackn(regs.pc.h);
+{lc}op_writestackn(regs.pc.l);
+    regs.pc.d = aa.d & 0xffffff;
+    regs.s.h = 0x01;
+  }
+
+  void {class}::op_jsr_long_n() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_writestackn(regs.pc.b);
+    op_io();
+    aa.b = op_readpc();
+    regs.pc.w--;
+    op_writestackn(regs.pc.h);
+{lc}op_writestackn(regs.pc.l);
+    regs.pc.d = aa.d & 0xffffff;
+  }
+@endmacro
+
+@macro op_jsr_iaddrx()
+  void {class}::op_jsr_iaddrx_e() {
+    aa.l = op_readpc();
+    op_writestackn(regs.pc.h);
+    op_writestackn(regs.pc.l);
+    aa.h = op_readpc();
+    op_io();
+    rd.l = op_readpbr(aa.w + regs.x.w + 0);
+{lc}rd.h = op_readpbr(aa.w + regs.x.w + 1);
+    regs.pc.w = rd.w;
+    regs.s.h = 0x01;
+  }
+
+  void {class}::op_jsr_iaddrx_n() {
+    aa.l = op_readpc();
+    op_writestackn(regs.pc.h);
+    op_writestackn(regs.pc.l);
+    aa.h = op_readpc();
+    op_io();
+    rd.l = op_readpbr(aa.w + regs.x.w + 0);
+{lc}rd.h = op_readpbr(aa.w + regs.x.w + 1);
+    regs.pc.w = rd.w;
+  }
+@endmacro
+
+@macro op_rti()
+  void {class}::op_rti_e() {
+    op_io();
+    op_io();
+    regs.p = op_readstack() | 0x30;
+    rd.l = op_readstack();
+{lc}rd.h = op_readstack();
+    regs.pc.w = rd.w;
+  }
+
+  void {class}::op_rti_n() {
+    op_io();
+    op_io();
+    regs.p = op_readstack();
+    if(regs.p.x) {
+      regs.x.h = 0x00;
+      regs.y.h = 0x00;
+    }
+    rd.l = op_readstack();
+    rd.h = op_readstack();
+{lc}rd.b = op_readstack();
+    regs.pc.d = rd.d & 0xffffff;
+    update_table();
+  }
+@endmacro
+
+@macro op_rts()
+  void {class}::op_rts() {
+    op_io();
+    op_io();
+    rd.l = op_readstack();
+    rd.h = op_readstack();
+{lc}op_io();
+    regs.pc.w = ++rd.w;
+  }
+@endmacro
+
+@macro op_rtl()
+  void {class}::op_rtl_e() {
+    op_io();
+    op_io();
+    rd.l = op_readstackn();
+    rd.h = op_readstackn();
+{lc}rd.b = op_readstackn();
+    regs.pc.b = rd.b;
+    regs.pc.w = ++rd.w;
+    regs.s.h = 0x01;
+  }
+
+  void {class}::op_rtl_n() {
+    op_io();
+    op_io();
+    rd.l = op_readstackn();
+    rd.h = op_readstackn();
+{lc}rd.b = op_readstackn();
+    regs.pc.b = rd.b;
+    regs.pc.w = ++rd.w;
+  }
+@endmacro

src/cpu/core/opcode_read.bpp

@@ -0,0 +1,307 @@
+@macro op_read_const(name)
+  void {class}::op_{name}_const_b() {
+{lc}rd.l = op_readpc();
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_const_w() {
+    rd.l = op_readpc();
+{lc}rd.h = op_readpc();
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_bit_const()
+  void {class}::op_bit_const_b() {
+{lc}rd.l = op_readpc();
+    regs.p.z = ((rd.l & regs.a.l) == 0);
+  }
+
+  void {class}::op_bit_const_w() {
+    rd.l = op_readpc();
+{lc}rd.h = op_readpc();
+    regs.p.z = ((rd.w & regs.a.w) == 0);
+  }
+@endmacro
+
+@macro op_read_addr(name)
+  void {class}::op_{name}_addr_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+{lc}rd.l = op_readdbr(aa.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_addr_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    rd.l = op_readdbr(aa.w + 0);
+{lc}rd.h = op_readdbr(aa.w + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_addrx(name)
+  void {class}::op_{name}_addrx_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io_cond4(aa.w, aa.w + regs.x.w);
+{lc}rd.l = op_readdbr(aa.w + regs.x.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_addrx_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io_cond4(aa.w, aa.w + regs.x.w);
+    rd.l = op_readdbr(aa.w + regs.x.w + 0);
+{lc}rd.h = op_readdbr(aa.w + regs.x.w + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_addry(name)
+  void {class}::op_{name}_addry_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io_cond4(aa.w, aa.w + regs.y.w);
+{lc}rd.l = op_readdbr(aa.w + regs.y.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_addry_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io_cond4(aa.w, aa.w + regs.y.w);
+    rd.l = op_readdbr(aa.w + regs.y.w + 0);
+{lc}rd.h = op_readdbr(aa.w + regs.y.w + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_long(name)
+  void {class}::op_{name}_long_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    aa.b = op_readpc();
+{lc}rd.l = op_readlong(aa.d);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_long_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    aa.b = op_readpc();
+    rd.l = op_readlong(aa.d + 0);
+{lc}rd.h = op_readlong(aa.d + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_longx(name)
+  void {class}::op_{name}_longx_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    aa.b = op_readpc();
+{lc}rd.l = op_readlong(aa.d + regs.x.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_longx_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    aa.b = op_readpc();
+    rd.l = op_readlong(aa.d + regs.x.w + 0);
+{lc}rd.h = op_readlong(aa.d + regs.x.w + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_dp(name)
+  void {class}::op_{name}_dp_b() {
+    dp = op_readpc();
+    op_io_cond2();
+{lc}rd.l = op_readdp(dp);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_dp_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    rd.l = op_readdp(dp + 0);
+{lc}rd.h = op_readdp(dp + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_dpr(name, r)
+  void {class}::op_{name}_dpr_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+{lc}rd.l = op_readdp(dp + regs.{r}.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_dpr_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+{lc}rd.l = op_readdp(dp + regs.{r}.w + 0);
+    rd.h = op_readdp(dp + regs.{r}.w + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_idp(name)
+  void {class}::op_{name}_idp_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+{lc}rd.l = op_readdbr(aa.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_idp_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    rd.l = op_readdbr(aa.w + 0);
+{lc}rd.h = op_readdbr(aa.w + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_idpx(name)
+  void {class}::op_{name}_idpx_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+    aa.l = op_readdp(dp + regs.x.w + 0);
+    aa.h = op_readdp(dp + regs.x.w + 1);
+{lc}rd.l = op_readdbr(aa.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_idpx_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+    aa.l = op_readdp(dp + regs.x.w + 0);
+    aa.h = op_readdp(dp + regs.x.w + 1);
+    rd.l = op_readdbr(aa.w + 0);
+{lc}rd.h = op_readdbr(aa.w + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_idpy(name)
+  void {class}::op_{name}_idpy_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    op_io_cond4(aa.w, aa.w + regs.y.w);
+{lc}rd.l = op_readdbr(aa.w + regs.y.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_idpy_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    op_io_cond4(aa.w, aa.w + regs.y.w);
+    rd.l = op_readdbr(aa.w + regs.y.w + 0);
+{lc}rd.h = op_readdbr(aa.w + regs.y.w + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_ildp(name)
+  void {class}::op_{name}_ildp_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    aa.b = op_readdp(dp + 2);
+{lc}rd.l = op_readlong(aa.d);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_ildp_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    aa.b = op_readdp(dp + 2);
+    rd.l = op_readlong(aa.d + 0);
+{lc}rd.h = op_readlong(aa.d + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_ildpy(name)
+  void {class}::op_{name}_ildpy_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    aa.b = op_readdp(dp + 2);
+{lc}rd.l = op_readlong(aa.d + regs.y.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_ildpy_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    aa.b = op_readdp(dp + 2);
+    rd.l = op_readlong(aa.d + regs.y.w + 0);
+{lc}rd.h = op_readlong(aa.d + regs.y.w + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_sr(name)
+  void {class}::op_{name}_sr_b() {
+    sp = op_readpc();
+    op_io();
+{lc}rd.l = op_readsp(sp);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_sr_w() {
+    sp = op_readpc();
+    op_io();
+    rd.l = op_readsp(sp + 0);
+{lc}rd.h = op_readsp(sp + 1);
+    op_{name}_w();
+  }
+@endmacro
+
+@macro op_read_isry(name)
+  void {class}::op_{name}_isry_b() {
+    sp = op_readpc();
+    op_io();
+    aa.l = op_readsp(sp + 0);
+    aa.h = op_readsp(sp + 1);
+    op_io();
+{lc}rd.l = op_readdbr(aa.w + regs.y.w);
+    op_{name}_b();
+  }
+
+  void {class}::op_{name}_isry_w() {
+    sp = op_readpc();
+    op_io();
+    aa.l = op_readsp(sp + 0);
+    aa.h = op_readsp(sp + 1);
+    op_io();
+    rd.l = op_readdbr(aa.w + regs.y.w + 0);
+{lc}rd.h = op_readdbr(aa.w + regs.y.w + 1);
+    op_{name}_w();
+  }
+@endmacro

src/cpu/core/opcode_rmw.bpp

@@ -0,0 +1,183 @@
+@macro op_adjust(name, r, op)
+  void {class}::op_{name}_imm_b() {
+{lc}op_io_irq();
+    regs.{r}.l {op};
+    regs.p.n = (regs.{r}.l & 0x80);
+    regs.p.z = (regs.{r}.l == 0);
+  }
+
+  void {class}::op_{name}_imm_w() {
+{lc}op_io_irq();
+    regs.{r}.w {op};
+    regs.p.n = (regs.{r}.w & 0x8000);
+    regs.p.z = (regs.{r}.w == 0);
+  }
+@endmacro
+
+@macro op_asl()
+  void {class}::op_asl_imm_b() {
+{lc}op_io_irq();
+    regs.p.c = (regs.a.l & 0x80);
+    regs.a.l <<= 1;
+    regs.p.n = (regs.a.l & 0x80);
+    regs.p.z = (regs.a.l == 0);
+  }
+
+  void {class}::op_asl_imm_w() {
+{lc}op_io_irq();
+    regs.p.c = (regs.a.w & 0x8000);
+    regs.a.w <<= 1;
+    regs.p.n = (regs.a.w & 0x8000);
+    regs.p.z = (regs.a.w == 0);
+  }
+@endmacro
+
+@macro op_lsr()
+  void {class}::op_lsr_imm_b() {
+{lc}op_io_irq();
+    regs.p.c = (regs.a.l & 0x01);
+    regs.a.l >>= 1;
+    regs.p.n = (regs.a.l & 0x80);
+    regs.p.z = (regs.a.l == 0);
+  }
+
+  void {class}::op_lsr_imm_w() {
+{lc}op_io_irq();
+    regs.p.c = (regs.a.w & 0x0001);
+    regs.a.w >>= 1;
+    regs.p.n = (regs.a.w & 0x8000);
+    regs.p.z = (regs.a.w == 0);
+  }
+@endmacro
+
+@macro op_rol()
+  void {class}::op_rol_imm_b() {
+{lc}op_io_irq();
+    bool carry = regs.p.c;
+    regs.p.c = (regs.a.l & 0x80);
+    regs.a.l = (regs.a.l << 1) | carry;
+    regs.p.n = (regs.a.l & 0x80);
+    regs.p.z = (regs.a.l == 0);
+  }
+
+  void {class}::op_rol_imm_w() {
+{lc}op_io_irq();
+    bool carry = regs.p.c;
+    regs.p.c = (regs.a.w & 0x8000);
+    regs.a.w = (regs.a.w << 1) | carry;
+    regs.p.n = (regs.a.w & 0x8000);
+    regs.p.z = (regs.a.w == 0);
+  }
+@endmacro
+
+@macro op_ror()
+  void {class}::op_ror_imm_b() {
+{lc}op_io_irq();
+    bool carry = regs.p.c;
+    regs.p.c = (regs.a.l & 0x01);
+    regs.a.l = (carry << 7) | (regs.a.l >> 1);
+    regs.p.n = (regs.a.l & 0x80);
+    regs.p.z = (regs.a.l == 0);
+  }
+
+  void {class}::op_ror_imm_w() {
+{lc}op_io_irq();
+    bool carry = regs.p.c;
+    regs.p.c = (regs.a.w & 0x0001);
+    regs.a.w = (carry << 15) | (regs.a.w >> 1);
+    regs.p.n = (regs.a.w & 0x8000);
+    regs.p.z = (regs.a.w == 0);
+  }
+@endmacro
+
+@macro op_adjust_addr(name)
+  void {class}::op_{name}_addr_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    rd.l = op_readdbr(aa.w);
+    op_io();
+    op_{name}_b();
+{lc}op_writedbr(aa.w, rd.l);
+  }
+
+  void {class}::op_{name}_addr_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    rd.l = op_readdbr(aa.w + 0);
+    rd.h = op_readdbr(aa.w + 1);
+    op_io();
+    op_{name}_w();
+    op_writedbr(aa.w + 1, rd.h);
+{lc}op_writedbr(aa.w + 0, rd.l);
+  }
+@endmacro
+
+@macro op_adjust_addrx(name)
+  void {class}::op_{name}_addrx_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io();
+    rd.l = op_readdbr(aa.w + regs.x.w);
+    op_io();
+    op_{name}_b();
+{lc}op_writedbr(aa.w + regs.x.w, rd.l);
+  }
+
+  void {class}::op_{name}_addrx_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io();
+    rd.l = op_readdbr(aa.w + regs.x.w + 0);
+    rd.h = op_readdbr(aa.w + regs.x.w + 1);
+    op_io();
+    op_{name}_w();
+    op_writedbr(aa.w + regs.x.w + 1, rd.h);
+{lc}op_writedbr(aa.w + regs.x.w + 0, rd.l);
+  }
+@endmacro
+
+@macro op_adjust_dp(name)
+  void {class}::op_{name}_dp_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    rd.l = op_readdp(dp);
+    op_io();
+    op_{name}_b();
+{lc}op_writedp(dp, rd.l);
+  }
+
+  void {class}::op_{name}_dp_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    rd.l = op_readdp(dp + 0);
+    rd.h = op_readdp(dp + 1);
+    op_io();
+    op_{name}_w();
+    op_writedp(dp + 1, rd.h);
+{lc}op_writedp(dp + 0, rd.l);
+  }
+@endmacro
+
+@macro op_adjust_dpx(name)
+  void {class}::op_{name}_dpx_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+    rd.l = op_readdp(dp + regs.x.w);
+    op_io();
+    op_{name}_b();
+{lc}op_writedp(dp + regs.x.w, rd.l);
+  }
+
+  void {class}::op_{name}_dpx_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+    rd.l = op_readdp(dp + regs.x.w + 0);
+    rd.h = op_readdp(dp + regs.x.w + 1);
+    op_io();
+    op_{name}_w();
+    op_writedp(dp + regs.x.w + 1, rd.h);
+{lc}op_writedp(dp + regs.x.w + 0, rd.l);
+  }
+@endmacro

src/cpu/core/opcode_tables.cpp

@@ -0,0 +1,141 @@
+#ifdef CPUCORE_CPP
+
+void CPUcore::initialize_opcode_table() {
+  //same implementation for all processor states
+  #define opA(id, name) \
+    op_table[table_EM + id] = &CPUcore::op_ ## name; \
+    op_table[table_MX + id] = &CPUcore::op_ ## name; \
+    op_table[table_Mx + id] = &CPUcore::op_ ## name; \
+    op_table[table_mX + id] = &CPUcore::op_ ## name; \
+    op_table[table_mx + id] = &CPUcore::op_ ## name;
+
+  //implementation changes based on E processor state
+  #define opE(id, name) \
+    op_table[table_EM + id] = &CPUcore::op_ ## name ## _e; \
+    op_table[table_MX + id] = &CPUcore::op_ ## name ## _n; \
+    op_table[table_Mx + id] = &CPUcore::op_ ## name ## _n; \
+    op_table[table_mX + id] = &CPUcore::op_ ## name ## _n; \
+    op_table[table_mx + id] = &CPUcore::op_ ## name ## _n; \
+
+  //implementation changes based on M processor state
+  #define opM(id, name) \
+    op_table[table_EM + id] = &CPUcore::op_ ## name ## _b; \
+    op_table[table_MX + id] = &CPUcore::op_ ## name ## _b; \
+    op_table[table_Mx + id] = &CPUcore::op_ ## name ## _b; \
+    op_table[table_mX + id] = &CPUcore::op_ ## name ## _w; \
+    op_table[table_mx + id] = &CPUcore::op_ ## name ## _w;
+
+  //implementation changes based on X processor state
+  #define opX(id, name) \
+    op_table[table_EM + id] = &CPUcore::op_ ## name ## _b; \
+    op_table[table_MX + id] = &CPUcore::op_ ## name ## _b; \
+    op_table[table_Mx + id] = &CPUcore::op_ ## name ## _w; \
+    op_table[table_mX + id] = &CPUcore::op_ ## name ## _b; \
+    op_table[table_mx + id] = &CPUcore::op_ ## name ## _w;
+
+  opE(0x00, brk)         opM(0x01, ora_idpx)   opE(0x02, cop)        opM(0x03, ora_sr)
+  opM(0x04, tsb_dp)      opM(0x05, ora_dp)     opM(0x06, asl_dp)     opM(0x07, ora_ildp)
+  opA(0x08, php)         opM(0x09, ora_const)  opM(0x0a, asl_imm)    opE(0x0b, phd)
+  opM(0x0c, tsb_addr)    opM(0x0d, ora_addr)   opM(0x0e, asl_addr)   opM(0x0f, ora_long)
+
+  opA(0x10, bpl)         opM(0x11, ora_idpy)   opM(0x12, ora_idp)    opM(0x13, ora_isry)
+  opM(0x14, trb_dp)      opM(0x15, ora_dpr)    opM(0x16, asl_dpx)    opM(0x17, ora_ildpy)
+  opA(0x18, clc)         opM(0x19, ora_addry)  opM(0x1a, inc_imm)    opE(0x1b, tcs)
+  opM(0x1c, trb_addr)    opM(0x1d, ora_addrx)  opM(0x1e, asl_addrx)  opM(0x1f, ora_longx)
+
+  opA(0x20, jsr_addr)    opM(0x21, and_idpx)   opE(0x22, jsr_long)   opM(0x23, and_sr)
+  opM(0x24, bit_dp)      opM(0x25, and_dp)     opM(0x26, rol_dp)     opM(0x27, and_ildp)
+  opE(0x28, plp)         opM(0x29, and_const)  opM(0x2a, rol_imm)    opE(0x2b, pld)
+  opM(0x2c, bit_addr)    opM(0x2d, and_addr)   opM(0x2e, rol_addr)   opM(0x2f, and_long)
+
+  opA(0x30, bmi)         opM(0x31, and_idpy)   opM(0x32, and_idp)    opM(0x33, and_isry)
+  opM(0x34, bit_dpr)     opM(0x35, and_dpr)    opM(0x36, rol_dpx)    opM(0x37, and_ildpy)
+  opA(0x38, sec)         opM(0x39, and_addry)  opM(0x3a, dec_imm)    opE(0x3b, tsc)
+  opM(0x3c, bit_addrx)   opM(0x3d, and_addrx)  opM(0x3e, rol_addrx)  opM(0x3f, and_longx)
+
+  opE(0x40, rti)         opM(0x41, eor_idpx)   opA(0x42, wdm)        opM(0x43, eor_sr)
+  opX(0x44, mvp)         opM(0x45, eor_dp)     opM(0x46, lsr_dp)     opM(0x47, eor_ildp)
+  opM(0x48, pha)         opM(0x49, eor_const)  opM(0x4a, lsr_imm)    opA(0x4b, phk)
+  opA(0x4c, jmp_addr)    opM(0x4d, eor_addr)   opM(0x4e, lsr_addr)   opM(0x4f, eor_long)
+
+  opA(0x50, bvc)         opM(0x51, eor_idpy)   opM(0x52, eor_idp)    opM(0x53, eor_isry)
+  opX(0x54, mvn)         opM(0x55, eor_dpr)    opM(0x56, lsr_dpx)    opM(0x57, eor_ildpy)
+  opA(0x58, cli)         opM(0x59, eor_addry)  opX(0x5a, phy)        opA(0x5b, tcd)
+  opA(0x5c, jmp_long)    opM(0x5d, eor_addrx)  opM(0x5e, lsr_addrx)  opM(0x5f, eor_longx)
+
+  opA(0x60, rts)         opM(0x61, adc_idpx)   opE(0x62, per)        opM(0x63, adc_sr)
+  opM(0x64, stz_dp)      opM(0x65, adc_dp)     opM(0x66, ror_dp)     opM(0x67, adc_ildp)
+  opM(0x68, pla)         opM(0x69, adc_const)  opM(0x6a, ror_imm)    opE(0x6b, rtl)
+  opA(0x6c, jmp_iaddr)   opM(0x6d, adc_addr)   opM(0x6e, ror_addr)   opM(0x6f, adc_long)
+
+  opA(0x70, bvs)         opM(0x71, adc_idpy)   opM(0x72, adc_idp)    opM(0x73, adc_isry)
+  opM(0x74, stz_dpr)     opM(0x75, adc_dpr)    opM(0x76, ror_dpx)    opM(0x77, adc_ildpy)
+  opA(0x78, sei)         opM(0x79, adc_addry)  opX(0x7a, ply)        opA(0x7b, tdc)
+  opA(0x7c, jmp_iaddrx)  opM(0x7d, adc_addrx)  opM(0x7e, ror_addrx)  opM(0x7f, adc_longx)
+
+  opA(0x80, bra)         opM(0x81, sta_idpx)   opA(0x82, brl)        opM(0x83, sta_sr)
+  opX(0x84, sty_dp)      opM(0x85, sta_dp)     opX(0x86, stx_dp)     opM(0x87, sta_ildp)
+  opX(0x88, dey_imm)     opM(0x89, bit_const)  opM(0x8a, txa)        opA(0x8b, phb)
+  opX(0x8c, sty_addr)    opM(0x8d, sta_addr)   opX(0x8e, stx_addr)   opM(0x8f, sta_long)
+
+  opA(0x90, bcc)         opM(0x91, sta_idpy)   opM(0x92, sta_idp)    opM(0x93, sta_isry)
+  opX(0x94, sty_dpr)     opM(0x95, sta_dpr)    opX(0x96, stx_dpr)    opM(0x97, sta_ildpy)
+  opM(0x98, tya)         opM(0x99, sta_addry)  opE(0x9a, txs)        opX(0x9b, txy)
+  opM(0x9c, stz_addr)    opM(0x9d, sta_addrx)  opM(0x9e, stz_addrx)  opM(0x9f, sta_longx)
+
+  opX(0xa0, ldy_const)   opM(0xa1, lda_idpx)   opX(0xa2, ldx_const)  opM(0xa3, lda_sr)
+  opX(0xa4, ldy_dp)      opM(0xa5, lda_dp)     opX(0xa6, ldx_dp)     opM(0xa7, lda_ildp)
+  opX(0xa8, tay)         opM(0xa9, lda_const)  opX(0xaa, tax)        opA(0xab, plb)
+  opX(0xac, ldy_addr)    opM(0xad, lda_addr)   opX(0xae, ldx_addr)   opM(0xaf, lda_long)
+
+  opA(0xb0, bcs)         opM(0xb1, lda_idpy)   opM(0xb2, lda_idp)    opM(0xb3, lda_isry)
+  opX(0xb4, ldy_dpr)     opM(0xb5, lda_dpr)    opX(0xb6, ldx_dpr)    opM(0xb7, lda_ildpy)
+  opA(0xb8, clv)         opM(0xb9, lda_addry)  opX(0xba, tsx)        opX(0xbb, tyx)
+  opX(0xbc, ldy_addrx)   opM(0xbd, lda_addrx)  opX(0xbe, ldx_addry)  opM(0xbf, lda_longx)
+
+  opX(0xc0, cpy_const)   opM(0xc1, cmp_idpx)   opE(0xc2, rep)        opM(0xc3, cmp_sr)
+  opX(0xc4, cpy_dp)      opM(0xc5, cmp_dp)     opM(0xc6, dec_dp)     opM(0xc7, cmp_ildp)
+  opX(0xc8, iny_imm)     opM(0xc9, cmp_const)  opX(0xca, dex_imm)    opA(0xcb, wai)
+  opX(0xcc, cpy_addr)    opM(0xcd, cmp_addr)   opM(0xce, dec_addr)   opM(0xcf, cmp_long)
+
+  opA(0xd0, bne)         opM(0xd1, cmp_idpy)   opM(0xd2, cmp_idp)    opM(0xd3, cmp_isry)
+  opE(0xd4, pei)         opM(0xd5, cmp_dpr)    opM(0xd6, dec_dpx)    opM(0xd7, cmp_ildpy)
+  opA(0xd8, cld)         opM(0xd9, cmp_addry)  opX(0xda, phx)        opA(0xdb, stp)
+  opA(0xdc, jmp_iladdr)  opM(0xdd, cmp_addrx)  opM(0xde, dec_addrx)  opM(0xdf, cmp_longx)
+
+  opX(0xe0, cpx_const)   opM(0xe1, sbc_idpx)   opE(0xe2, sep)        opM(0xe3, sbc_sr)
+  opX(0xe4, cpx_dp)      opM(0xe5, sbc_dp)     opM(0xe6, inc_dp)     opM(0xe7, sbc_ildp)
+  opX(0xe8, inx_imm)     opM(0xe9, sbc_const)  opA(0xea, nop)        opA(0xeb, xba)
+  opX(0xec, cpx_addr)    opM(0xed, sbc_addr)   opM(0xee, inc_addr)   opM(0xef, sbc_long)
+
+  opA(0xf0, beq)         opM(0xf1, sbc_idpy)   opM(0xf2, sbc_idp)    opM(0xf3, sbc_isry)
+  opE(0xf4, pea)         opM(0xf5, sbc_dpr)    opM(0xf6, inc_dpx)    opM(0xf7, sbc_ildpy)
+  opA(0xf8, sed)         opM(0xf9, sbc_addry)  opX(0xfa, plx)        opA(0xfb, xce)
+  opE(0xfc, jsr_iaddrx)  opM(0xfd, sbc_addrx)  opM(0xfe, inc_addrx)  opM(0xff, sbc_longx)
+
+  #undef opA
+  #undef opE
+  #undef opM
+  #undef opX
+}
+
+void CPUcore::update_table() {
+  if(regs.e) {
+    opcode_table = &op_table[table_EM];
+  } else if(regs.p.m) {
+    if(regs.p.x) {
+      opcode_table = &op_table[table_MX];
+    } else {
+      opcode_table = &op_table[table_Mx];
+    }
+  } else {
+    if(regs.p.x) {
+      opcode_table = &op_table[table_mX];
+    } else {
+      opcode_table = &op_table[table_mx];
+    }
+  }
+}
+
+#endif
+

src/cpu/core/opcode_write.bpp

@@ -0,0 +1,219 @@
+@macro op_store_addr(name, r)
+  void {class}::op_{name}_addr_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+{lc}op_writedbr(aa.w, {r});
+  }
+
+  void {class}::op_{name}_addr_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_writedbr(aa.w + 0, {r} >> 0);
+{lc}op_writedbr(aa.w + 1, {r} >> 8);
+  }
+@endmacro
+
+@macro op_store_addrr(name, suffix, r, index)
+  void {class}::op_{name}_addr{suffix}_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io();
+{lc}op_writedbr(aa.w + {index}, {r});
+  }
+
+  void {class}::op_{name}_addr{suffix}_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    op_io();
+    op_writedbr(aa.w + {index} + 0, {r} >> 0);
+{lc}op_writedbr(aa.w + {index} + 1, {r} >> 8);
+  }
+@endmacro
+
+@macro op_store_longr(name, suffix, index)
+  void {class}::op_{name}_long{suffix}_b() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    aa.b = op_readpc();
+{lc}op_writelong(aa.d + {index}, regs.a.l);
+  }
+
+  void {class}::op_{name}_long{suffix}_w() {
+    aa.l = op_readpc();
+    aa.h = op_readpc();
+    aa.b = op_readpc();
+    op_writelong(aa.d + {index} + 0, regs.a.l);
+{lc}op_writelong(aa.d + {index} + 1, regs.a.h);
+  }
+@endmacro
+
+@macro op_store_dp(name, r)
+  void {class}::op_{name}_dp_b() {
+    dp = op_readpc();
+    op_io_cond2();
+{lc}op_writedp(dp, {r});
+  }
+
+  void {class}::op_{name}_dp_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_writedp(dp + 0, {r} >> 0);
+{lc}op_writedp(dp + 1, {r} >> 8);
+  }
+@endmacro
+
+@macro op_store_dpr(name, r, index)
+  void {class}::op_{name}_dpr_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+{lc}op_writedp(dp + regs.{index}.w, {r});
+  }
+
+  void {class}::op_{name}_dpr_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+    op_writedp(dp + regs.{index}.w + 0, {r} >> 0);
+{lc}op_writedp(dp + regs.{index}.w + 1, {r} >> 8);
+  }
+@endmacro
+
+@macro op_sta_idp()
+  void {class}::op_sta_idp_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+{lc}op_writedbr(aa.w, regs.a.l);
+  }
+
+  void {class}::op_sta_idp_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    op_writedbr(aa.w + 0, regs.a.l);
+{lc}op_writedbr(aa.w + 1, regs.a.h);
+  }
+@endmacro
+
+@macro op_sta_ildp()
+  void {class}::op_sta_ildp_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    aa.b = op_readdp(dp + 2);
+{lc}op_writelong(aa.d, regs.a.l);
+  }
+
+  void {class}::op_sta_ildp_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    aa.b = op_readdp(dp + 2);
+    op_writelong(aa.d + 0, regs.a.l);
+{lc}op_writelong(aa.d + 1, regs.a.h);
+  }
+@endmacro
+
+@macro op_sta_idpx()
+  void {class}::op_sta_idpx_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+    aa.l = op_readdp(dp + regs.x.w + 0);
+    aa.h = op_readdp(dp + regs.x.w + 1);
+{lc}op_writedbr(aa.w, regs.a.l);
+  }
+
+  void {class}::op_sta_idpx_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    op_io();
+    aa.l = op_readdp(dp + regs.x.w + 0);
+    aa.h = op_readdp(dp + regs.x.w + 1);
+    op_writedbr(aa.w + 0, regs.a.l);
+{lc}op_writedbr(aa.w + 1, regs.a.h);
+  }
+@endmacro
+
+@macro op_sta_idpy()
+  void {class}::op_sta_idpy_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    op_io();
+{lc}op_writedbr(aa.w + regs.y.w, regs.a.l);
+  }
+
+  void {class}::op_sta_idpy_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    op_io();
+    op_writedbr(aa.w + regs.y.w + 0, regs.a.l);
+{lc}op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
+  }
+@endmacro
+
+@macro op_sta_ildpy()
+  void {class}::op_sta_ildpy_b() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    aa.b = op_readdp(dp + 2);
+{lc}op_writelong(aa.d + regs.y.w, regs.a.l);
+  }
+
+  void {class}::op_sta_ildpy_w() {
+    dp = op_readpc();
+    op_io_cond2();
+    aa.l = op_readdp(dp + 0);
+    aa.h = op_readdp(dp + 1);
+    aa.b = op_readdp(dp + 2);
+    op_writelong(aa.d + regs.y.w + 0, regs.a.l);
+{lc}op_writelong(aa.d + regs.y.w + 1, regs.a.h);
+  }
+@endmacro
+
+@macro op_sta_sr()
+  void {class}::op_sta_sr_b() {
+    sp = op_readpc();
+    op_io();
+{lc}op_writesp(sp, regs.a.l);
+  }
+
+  void {class}::op_sta_sr_w() {
+    sp = op_readpc();
+    op_io();
+    op_writesp(sp + 0, regs.a.l);
+{lc}op_writesp(sp + 1, regs.a.h);
+  }
+@endmacro
+
+@macro op_sta_isry()
+  void {class}::op_sta_isry_b() {
+    sp = op_readpc();
+    op_io();
+    aa.l = op_readsp(sp + 0);
+    aa.h = op_readsp(sp + 1);
+    op_io();
+{lc}op_writedbr(aa.w + regs.y.w, regs.a.l);
+  }
+
+  void {class}::op_sta_isry_w() {
+    sp = op_readpc();
+    op_io();
+    aa.l = op_readsp(sp + 0);
+    aa.h = op_readsp(sp + 1);
+    op_io();
+    op_writedbr(aa.w + regs.y.w + 0, regs.a.l);
+{lc}op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
+  }
+@endmacro

src/cpu/core/registers.hpp

@@ -0,0 +1,79 @@
+struct flag_t {
+  bool n, v, m, x, d, i, z, c;
+
+  inline operator unsigned() const {
+    return (n << 7) + (v << 6) + (m << 5) + (x << 4)
+         + (d << 3) + (i << 2) + (z << 1) + (c << 0);
+  }
+
+  inline unsigned operator=(uint8_t data) {
+    n = data & 0x80; v = data & 0x40; m = data & 0x20; x = data & 0x10;
+    d = data & 0x08; i = data & 0x04; z = data & 0x02; c = data & 0x01;
+    return data;
+  }
+
+  inline unsigned operator|=(unsigned data) { return operator=(operator unsigned() | data); }
+  inline unsigned operator^=(unsigned data) { return operator=(operator unsigned() ^ data); }
+  inline unsigned operator&=(unsigned data) { return operator=(operator unsigned() & data); }
+
+  flag_t() : n(0), v(0), m(0), x(0), d(0), i(0), z(0), c(0) {}
+};
+
+struct reg16_t {
+  union {
+    uint16 w;
+    struct { uint8 order_lsb2(l, h); };
+  };
+
+  inline operator unsigned() const { return w; }
+  inline unsigned operator   = (unsigned i) { return w   = i; }
+  inline unsigned operator  |= (unsigned i) { return w  |= i; }
+  inline unsigned operator  ^= (unsigned i) { return w  ^= i; }
+  inline unsigned operator  &= (unsigned i) { return w  &= i; }
+  inline unsigned operator <<= (unsigned i) { return w <<= i; }
+  inline unsigned operator >>= (unsigned i) { return w >>= i; }
+  inline unsigned operator  += (unsigned i) { return w  += i; }
+  inline unsigned operator  -= (unsigned i) { return w  -= i; }
+  inline unsigned operator  *= (unsigned i) { return w  *= i; }
+  inline unsigned operator  /= (unsigned i) { return w  /= i; }
+  inline unsigned operator  %= (unsigned i) { return w  %= i; }
+
+  reg16_t() : w(0) {}
+};
+
+struct reg24_t {
+  union {
+    uint32 d;
+    struct { uint16 order_lsb2(w, wh); };
+    struct { uint8  order_lsb4(l, h, b, bh); };
+  };
+
+  inline operator unsigned() const { return d; }
+  inline unsigned operator   = (unsigned i) { return d = uclip<24>(i); }
+  inline unsigned operator  |= (unsigned i) { return d = uclip<24>(d  | i); }
+  inline unsigned operator  ^= (unsigned i) { return d = uclip<24>(d  ^ i); }
+  inline unsigned operator  &= (unsigned i) { return d = uclip<24>(d  & i); }
+  inline unsigned operator <<= (unsigned i) { return d = uclip<24>(d << i); }
+  inline unsigned operator >>= (unsigned i) { return d = uclip<24>(d >> i); }
+  inline unsigned operator  += (unsigned i) { return d = uclip<24>(d  + i); }
+  inline unsigned operator  -= (unsigned i) { return d = uclip<24>(d  - i); }
+  inline unsigned operator  *= (unsigned i) { return d = uclip<24>(d  * i); }
+  inline unsigned operator  /= (unsigned i) { return d = uclip<24>(d  / i); }
+  inline unsigned operator  %= (unsigned i) { return d = uclip<24>(d  % i); }
+
+  reg24_t() : d(0) {}
+};
+
+struct regs_t {
+  reg24_t  pc;
+  reg16_t  a, x, y, s, d;
+  flag_t   p;
+  uint8_t  db;
+  bool     e;
+
+  bool    irq;  //IRQ pin (0 = low, 1 = trigger)
+  bool    wai;  //raised during wai, cleared after interrupt triggered
+  uint8_t mdr;  //memory data register
+
+  regs_t() : db(0), e(false), irq(false), wai(false), mdr(0) {}
+};