Bodge to jhead to allow the ziptie and sleaving to be removed by setting naked to undef.

readme.md

@@ -85,6 +85,7 @@ Axial components for PCBs.
 |   1 | ```ax_res(res1_4, 47000)``` |  Resistor 47000 Ohms 5% 0.25W |
 |   1 | ```ax_res(res1_2, 8200)``` |  Resistor 8200 Ohms 5% 0.5W |
 |   1 | ```ax_res(res1_2, 8250, tol = 1)``` |  Resistor 8250 Ohms 1% 0.5W |
+|   1 | ```wire_link(0.8, 10.16)``` |  Wire link 0.8mm x 0.4" |
 
 
 <a href="#top">Top</a>
@@ -2223,6 +2224,8 @@ PCBs and perfboard with optional components. The shape can be a rectangle with o
 |   2 | ```green_terminal(gt_3p5, 4)``` |  Terminal block 4 way 3.5mm |
 |   1 | ```terminal_35(4)``` |  Terminal block 4 way 3.5mm |
 |   1 | ```pcb(TestPCB)``` |  Test PCB |
+|   1 | ```wire_link(0.8, 5.08, h = 10.16)``` |  Wire link 0.8mm x 0.2" |
+|   1 | ```wire_link(0.8, 10.16)``` |  Wire link 0.8mm x 0.4" |
 
 
 <a href="#top">Top</a>

tests/PCB.scad

@@ -86,10 +86,13 @@ test_pcb = ["TestPCB", "Test PCB",
         [  5, 218, 180, "hdmi"],
         [  3, 235, 180, "mini_hdmi"],
         [  6, 175, 180, "uSD", [12, 11.5, 1.4]],
+
+        [ 65,   9,   0, "link", inch(0.4)],
         [ 65,  12,   0, "ax_res", res1_8, 1000],
         [ 65,  17,   0, "ax_res", res1_4, 10000],
         [ 65,  22,   0, "ax_res", res1_2, 100000],
 
+        [ 80,   9,   0, "link", inch(0.2), inch(0.4)],
         [ 80,  12,   0, "ax_res", res1_8, 1000000, 1, inch(0.1)],
         [ 80,  17,   0, "ax_res", res1_4, 100,     2, inch(0.1)],
         [ 80,  22,   0, "ax_res", res1_2, 10,     10, inch(0.2)],

vitamins/axial.scad

@@ -24,6 +24,7 @@ include <../utils/core/core.scad>
 include <../utils/round.scad>
 
 module wire_link(d, l, h = 1, tail = 3) { //! Draw a wire jumper link.
+    vitamin(str("wire_link(", d, ", ", l, arg(h, 1, "h"), arg(tail, 3, "tail"),  "): Wire link ", d, "mm x ", l / inch(1), "\""));
     r = d;
     $fn = 32;
 
@@ -57,13 +58,16 @@ module orientate_axial(length, height, pitch, wire_d) { // Orient horizontal or
     min_pitch = ceil((length + 1) / inch(0.1)) * inch(0.1);
     lead_pitch = pitch ? pitch : min_pitch;
     if(lead_pitch >= min_pitch) {
-        wire_link(wire_d, lead_pitch, height);
+        not_on_bom()
+            wire_link(wire_d, lead_pitch, height);
+
         translate_z(height)
             rotate([0, 90, 0])
                 children();
     }
     else {
-        wire_link(wire_d, lead_pitch, length + 0.7 + wire_d);
+        not_on_bom()
+            wire_link(wire_d, lead_pitch, length + 0.7 + wire_d);
 
         translate([-pitch / 2, 0, length / 2 + 0.2])
             children();

vitamins/jhead.scad

@@ -138,7 +138,7 @@ module jhead_hot_end_assembly(type, filament, naked = false) { //! Assembly with
     //
     // silcone tape
     //
-    if(!naked)
+    if(is_undef(naked) || !naked)
         color("red")
             if(exploded())
                 translate([0, max(hot_end_insulator_diameter(type) / 2, heater_length(heater) / 2 - nozzle_x(heater)),
@@ -156,7 +156,7 @@ module jhead_hot_end_assembly(type, filament, naked = false) { //! Assembly with
     //
     // Zip tie and heatshrink
     //
-    if(!naked)
+    if(!naked  && !is_undef(naked))
         rotate(10) {
             dia =  hot_end_insulator_diameter(type);
             scale([1, (bundle + dia) / dia])

vitamins/led_meter.scad

@@ -85,7 +85,8 @@ module meter(type, colour = "red", value = "888", display_colour = false) //! Dr
         translate([0, meter_shunt_y(type), size.z])
             vflip()
                 color("#b87333")
-                    wire_link(shunt.y, shunt.x, shunt.z, tail = 2);
+                    not_on_bom()
+                        wire_link(shunt.y, shunt.x, shunt.z, tail = 2);
 }
 
 clearance = 0.1;

vitamins/pcb.scad

@@ -953,6 +953,7 @@ module pcb_component(comp, cutouts = false, angle = undef) { //! Draw pcb compon
             if(show(comp, "led"))           led(comp[4], comp[5], 2.6);
             if(show(comp, "pdip"))          pdip(comp[4], comp[5], param(6, false), param(7, inch(0.3)));
             if(show(comp, "ax_res"))        ax_res(comp[4], comp[5], param(6, 5), param(7, 0));
+            if(show(comp, "link"))          wire_link(l = comp[4], h = param(5, 1), d = param(6, 0.8), tail = param(7, 3));
             if(show(comp, "D_plug"))        translate_z(d_pcb_offset(comp[4])) d_plug(comp[4], pcb = true);
             if(show(comp, "molex_hdr"))     molex_254(comp[4]);
             if(show(comp, "jst_xh"))        jst_xh_header(jst_xh_header, comp[4], param(5, false), param(6, "white"), param(7, undef));

vitamins/veroboard.scad

@@ -132,8 +132,12 @@ module veroboard(type) { //! Draw specified veroboard with missing tracks and tr
 module vero_components(type, cutouts = false, angle = undef)
     for(comp = vero_components(type))
         vero_grid_pos(type, comp.x, comp.y)
-            translate_z(vero_thickness(type))
-                pcb_component(comp, cutouts, angle);
+            if(comp[3][0] == "-")
+                vflip()
+                    pcb_component(comp, cutouts, angle);
+            else
+                translate_z(vero_thickness(type))
+                    pcb_component(comp, cutouts, angle);
 
 module vero_cutouts(type, angle = undef) vero_components(type, true, angle); //! Make cutouts to clear components