Update to bsnes v033 release.

This release adds SPC7110 emulation, without the need for graphics packs!!, and a rewritten S-RTC (real-time clock) emulator.
SPC7110 support means that Far East of Eden Zero, FEoEZ: Shounen Jump Edition, Momotarou Dentetsu Happy and Super Power League 4 are now all fully playable. I will warn you, the emulation is very slow in this version -- while most areas of each game will run at the same speed as other games, there are a few peak moments where speed will drop by up to ~50%. The reason for the slow-down is that I am currently uncertain how to determine the amount of data to decompress in advance, so I default to the maximum amount possible. The reason I am releasing now anyway, is because I beleive in the "release early, release often" paradigm. It will likely take me a few weeks to finish researching this chip, and I didn't want to keep the work I had private during that time. But rest assured, bsnes v034 should feature much faster SPC7110 emulation.
neviksti, Andreas Naive and jolly_codger worked non-stop on the SPC7110 decompression algorithm for the past two weeks. caitsith2 provided valuable data to the effort. I only wish that I could've been of some use, but alas, I had no role in this. In the end, it was neviksti who managed to crack all three(!!) compression modes of this chip, which turned out to be a customized 8-bit QM-coder with a prediction model. You can read more about this here. I would also like to thank Dark Force and John Weidman (aka The Dumper) for their research notes on the SPC7110 register interface.
For those who don't understand the hoopla about figuring out this compression algorithm when we already had graphics pack simulation, I should note that we have since found a few errors in these packs. Not to mention, you no longer need ~4-16MB packs for each game you wish to run. They work like any other game now. Better still, the chip can now be used to compress new graphics, eg for any future translation efforts on these titles.
The real-time clocks in both Far East of Eden Zero and Dai Kaijuu Monogatari 2 will now save a ".rtc" file in your save folder, which contains the clock as set by the video game, as well as a timestamp from your computer when the time was last updated. It uses the difference between the saved timestamp and current time to update the time. This allows you to specify any time you like, whereas previously bsnes would just use your computer's current time, ignoring the time you set in-game. It also allows the "round clock by 30 seconds" option in both games to work. I avoided this before because this method makes supporting daylight savings time and such impractical, although I should note that the original hardware did not support DST, either. This method was required to pass the SPC7110 tests, and is overall much more faithful to how the original chips worked.
Once again, I'd really like to personally thank neviksti for his tireless efforts. Eliminating graphics packs from SNES emulation was one of my primary reasons for getting involved in the SNES emulation scene. That neviksti managed to crack this algorithm means a lot to me. Thank you so much, neviksti. This release is dedicated to you, now go get some sleep Wink

license.txt

@@ -66,7 +66,8 @@ such software.
 libco, author: byuu
 libui, author: byuu
 OBC-1 emu, author: byuu
-S-DD1 emu, author: Andreas Naive
+S-DD1 decompressor, author: Andreas Naive
+SPC7110 decompressor, author: neviksti
 S-RTC emu, author: byuu
 
 Any software listed above as exemptions may be relicensed individually from

readme.txt

@@ -1,10 +1,10 @@
 bsnes
-Version: 0.028
+Version: 0.033
 Author: byuu
 
---------
+========
 General:
---------
+========
 bsnes is a Super Nintendo / Super Famicom emulator that began on
 October 14th, 2004.
 
@@ -13,12 +13,34 @@ http://byuu.org/
 
 Please see license.txt for important licensing information.
 
-------------------
+==============
+Configuration:
+==============
+bsnes has two configuration files: bsnes.cfg, for program settings; and
+locale.cfg, for localization.
+
+For each file, bsnes will start by looking inside the same folder where the
+bsnes executable is located. If said file is not found, it will then check your
+user profile folder. On Windows, this is located at "%APPDATA%/.bsnes". On all
+other operating systems, this is located at "~/.bsnes". If said file is still
+not found, it will automatically be created in your user profile folder.
+
+If you wish to use bsnes in single-user mode, be sure that both files exist
+inside the same folder as the bsnes executable. If they do not, you can simply
+create new blank files and bsnes will use them in the future.
+
+If you wish to use bsnes in multi-user mode, simply delete these two files from
+the bsnes executable directory if they exist.
+
+If you wish to have multiple configuration profiles for the same user, you will
+need to make copies of the bsnes executable, and use each one in single-user
+mode.
+
+==================
 Known Limitations:
-------------------
+==================
 S-CPU
-- Invalid DMA / HDMA transfers not fully emulated
-- Multiply / Divide register delays not implemented
+- Multiply / divide register delays not implemented
 
 S-PPU
 - Uses scanline-based renderer. This is very inaccurate, but few (if any)
@@ -34,9 +56,9 @@ Hardware Bugs
 - S-CPU.r1 HDMA crashing bug not emulated
 - S-CPU<>S-SMP communication bus conflicts not emulated
 
----------------------
+=====================
 Unsupported Hardware:
----------------------
+=====================
 SA-1
 Coprocessor used in many popular games, including:
 - Dragon Ball Z Hyper Dimension
@@ -53,25 +75,18 @@ Coprocessor used in many popular games, including:
 - Star Fox 2 (unreleased beta)
 - Super Mario World 2: Yoshi's Island
 
-SPC7110
-Coprocessor used only by the following games:
-- Far East of Eden Zero
-- Far East of Eden Zero: Shounen Jump no Shou
-- Momotarou Densetsu Happy
-- Super Power League 4
-
 ST-011
-SETA DSP used only by Quick-move Shogi Match with Nidan Rank-holder Morita
+SETA DSP used by Quick-move Shogi Match with Nidan Rank-holder Morita
 
 ST-018
-SETA RISC CPU used only by Quick-move Shogi Match with Nidan Rank-holder Morita 2
+SETA RISC CPU used by Quick-move Shogi Match with Nidan Rank-holder Morita 2
 
 Super Gameboy
 Cartridge passthrough used for playing Gameboy games
 
-------------------------
+========================
 Unsupported Controllers:
-------------------------
+========================
 Mouse
 Super Scope
 Justifier

src/Makefile

@@ -1,7 +1,5 @@
 include lib/nall/Makefile.string
-
 prefix = /usr/local
-arch = ARCH_LSB
 
 ################
 ### compiler ###
@@ -13,7 +11,7 @@ ifneq ($(findstring gcc,$(compiler)),) # GCC family
   cpp = $(subst cc,++,$(compiler)) $(flags)
   obj = o
   rule = -c $< -o $@
-  link =
+  link = -s
   mkbin = -o$1
   mkdef = -D$1
   mklib = -l$1
@@ -36,13 +34,12 @@ endif
 ##########
 
 ifeq ($(platform),x) # X11
-  ruby = video.glx video.xv video.sdl audio.openal audio.oss audio.ao input.sdl input.x
-  arch += PLATFORM_X
+  ruby = video.glx video.xv video.sdl audio.openal audio.oss audio.alsa audio.ao input.sdl input.x
   link += `pkg-config --libs gtk+-2.0`
+  link += $(call mklib,Xtst)
   delete = rm -f $1
 else ifeq ($(platform),win) # Windows
-  ruby = video.direct3d video.directdraw video.gdi audio.directsound input.directinput
-  arch += PLATFORM_WIN
+  ruby = video.direct3d video.wgl video.directdraw video.gdi audio.directsound input.directinput
   link += $(if $(findstring mingw,$(compiler)),-mwindows)
   link += $(call mklib,uuid)
   link += $(call mklib,kernel32)
@@ -61,13 +58,18 @@ endif
 ### ruby ###
 ############
 
+rubyflags =
+rubyflags += $(if $(findstring .sdl,$(ruby)),`sdl-config --cflags`)
+
 link += $(if $(findstring video.direct3d,$(ruby)),$(call mklib,d3d9))
 link += $(if $(findstring video.directdraw,$(ruby)),$(call mklib,ddraw))
 link += $(if $(findstring video.glx,$(ruby)),$(call mklib,GL))
+link += $(if $(findstring video.wgl,$(ruby)),$(call mklib,opengl32))
 link += $(if $(findstring video.xv,$(ruby)),$(call mklib,Xv))
+link += $(if $(findstring audio.alsa,$(ruby)),$(call mklib,asound))
 link += $(if $(findstring audio.ao,$(ruby)),$(call mklib,ao))
 link += $(if $(findstring audio.directsound,$(ruby)),$(call mklib,dsound))
-link += $(if $(findstring audio.openal,$(ruby)),$(call mklib,openal) $(call mklib,alut))
+link += $(if $(findstring audio.openal,$(ruby)),$(if $(call streq,$(platform),x),$(call mklib,openal),$(call mklib,openal32)))
 link += $(if $(findstring input.directinput,$(ruby)),$(call mklib,dinput8) $(call mklib,dxguid))
 link += $(if $(findstring input.sdl,$(ruby)),`sdl-config --libs`)
 
@@ -75,9 +77,9 @@ link += $(if $(findstring input.sdl,$(ruby)),`sdl-config --libs`)
 ### main target and dependencies ###
 ####################################
 
-objects = main libco hiro ruby $(ruby) string reader cart cheat \
-  memory smemory cpu scpu smp ssmp bdsp ppu bppu snes \
-  bsx srtc sdd1 cx4 dsp1 dsp2 dsp3 dsp4 obc1 st010
+objects = main libco hiro ruby libfilter string reader cart cheat \
+  memory smemory cpu scpu smp ssmp sdsp ppu bppu snes \
+  bsx srtc sdd1 spc7110 cx4 dsp1 dsp2 dsp3 dsp4 obc1 st010
 
 ifeq ($(enable_gzip),true)
   objects += adler32 compress crc32 deflate gzio inffast inflate inftrees ioapi trees unzip zip zutil
@@ -89,7 +91,6 @@ ifeq ($(enable_jma),true)
   flags += $(call mkdef,JMA_SUPPORT)
 endif
 
-arch := $(patsubst %,$(call mkdef,%),$(arch))
 objects := $(patsubst %,obj/%.$(obj),$(objects))
 rubydef := $(foreach c,$(subst .,_,$(call strupper,$(ruby))),$(call mkdef,$c))
 
@@ -124,47 +125,22 @@ all: build;
 ### main ###
 ############
 
-obj/main.$(obj): ui/main.cpp config/* lib/nall/* lib/ruby/* ui/* ui/loader/* ui/settings/*
-	$(call compile,$(arch))
-
-obj/bsnes.res     : ui/bsnes.rc; rc /r /foobj/bsnes.res ui/bsnes.rc
-obj/bsnesrc.$(obj): ui/bsnes.rc; windres -I data ui/bsnes.rc obj/bsnesrc.$(obj)
-
-############
-### ruby ###
-############
-
-obj/ruby.$(obj)             : lib/ruby/ruby.cpp lib/ruby/*
-	$(call compile,$(rubydef))
-obj/video.direct3d.$(obj)   : lib/ruby/video/direct3d.cpp lib/ruby/video/direct3d.*
-obj/video.directdraw.$(obj) : lib/ruby/video/directdraw.cpp lib/ruby/video/directdraw.*
-obj/video.gdi.$(obj)        : lib/ruby/video/gdi.cpp lib/ruby/video/gdi.*
-obj/video.glx.$(obj)        : lib/ruby/video/glx.cpp lib/ruby/video/glx.*
-obj/video.sdl.$(obj)        : lib/ruby/video/sdl.cpp lib/ruby/video/sdl.*
-	$(call compile,`sdl-config --cflags`)
-obj/video.xv.$(obj)         : lib/ruby/video/xv.cpp lib/ruby/video/xv.*
-obj/audio.ao.$(obj)         : lib/ruby/audio/ao.cpp lib/ruby/audio/ao.*
-obj/audio.directsound.$(obj): lib/ruby/audio/directsound.cpp lib/ruby/audio/directsound.*
-obj/audio.openal.$(obj)     : lib/ruby/audio/openal.cpp lib/ruby/audio/openal.*
-obj/audio.oss.$(obj)        : lib/ruby/audio/oss.cpp lib/ruby/audio/oss.*
-obj/input.directinput.$(obj): lib/ruby/input/directinput.cpp lib/ruby/input/directinput.*
-obj/input.sdl.$(obj)        : lib/ruby/input/sdl.cpp lib/ruby/input/sdl.*
-	$(call compile,`sdl-config --cflags`)
-obj/input.x.$(obj)          : lib/ruby/input/x.cpp lib/ruby/input/x.*
-
-############
-### hiro ###
-############
-
-obj/hiro.$(obj): lib/hiro.cpp lib/hiro.* lib/hiro_gtk/* lib/hiro_win/*
-	$(call compile,$(if $(call streq,$(platform),x),`pkg-config --cflags gtk+-2.0`))
+obj/main.$(obj): ui/main.cpp ui/* ui/base/* ui/loader/* ui/settings/*
+obj/bsnes.res: ui/bsnes.rc; rc /r /foobj/bsnes.res ui/bsnes.rc
+obj/bsnesrc.$(obj): ui/bsnes.rc; windres ui/bsnes.rc obj/bsnesrc.$(obj)
 
 #################
 ### libraries ###
 #################
 
-obj/libco.$(obj): lib/libco.c lib/libco.* lib/libco/*
-obj/string.$(obj): lib/nall/string.cpp lib/nall/*
+obj/ruby.$(obj): lib/ruby/ruby.cpp lib/ruby/*
+	$(call compile,$(rubydef) $(rubyflags))
+obj/hiro.$(obj): lib/hiro/hiro.cpp lib/hiro/* lib/hiro/gtk/* lib/hiro/win/*
+	$(call compile,$(if $(call streq,$(platform),x),`pkg-config --cflags gtk+-2.0`))
+obj/libco.$(obj):     lib/libco/libco.c lib/libco/*
+	$(call compile,-static)
+obj/libfilter.$(obj): lib/libfilter/libfilter.cpp lib/libfilter/*
+obj/string.$(obj):    lib/nall/string.cpp lib/nall/*
 
 #################
 ### utilities ###
@@ -179,7 +155,6 @@ obj/cheat.$(obj) : cheat/cheat.cpp cheat/*
 ##############
 
 obj/memory.$(obj) : memory/memory.cpp memory/*
-obj/bmemory.$(obj): memory/bmemory/bmemory.cpp memory/bmemory/* memory/bmemory/mapper/*
 obj/smemory.$(obj): memory/smemory/smemory.cpp memory/smemory/* memory/smemory/mapper/*
 
 ###########
@@ -202,6 +177,7 @@ obj/ssmp.$(obj): smp/ssmp/ssmp.cpp smp/ssmp/* smp/ssmp/core/* smp/ssmp/memory/*
 
 obj/adsp.$(obj): dsp/adsp/adsp.cpp dsp/adsp/*
 obj/bdsp.$(obj): dsp/bdsp/bdsp.cpp dsp/bdsp/*
+obj/sdsp.$(obj): dsp/sdsp/sdsp.cpp dsp/sdsp/*
 
 ###########
 ### ppu ###
@@ -220,16 +196,17 @@ obj/snes.$(obj): snes/snes.cpp snes/* snes/scheduler/* snes/video/* snes/audio/*
 ### special chips ###
 #####################
 
-obj/bsx.$(obj)  : chip/bsx/bsx.cpp chip/bsx/*
-obj/srtc.$(obj) : chip/srtc/srtc.cpp chip/srtc/*
-obj/sdd1.$(obj) : chip/sdd1/sdd1.cpp chip/sdd1/*
-obj/cx4.$(obj)  : chip/cx4/cx4.cpp chip/cx4/*
-obj/dsp1.$(obj) : chip/dsp1/dsp1.cpp chip/dsp1/*
-obj/dsp2.$(obj) : chip/dsp2/dsp2.cpp chip/dsp2/*
-obj/dsp3.$(obj) : chip/dsp3/dsp3.cpp chip/dsp3/*
-obj/dsp4.$(obj) : chip/dsp4/dsp4.cpp chip/dsp4/*
-obj/obc1.$(obj) : chip/obc1/obc1.cpp chip/obc1/*
-obj/st010.$(obj): chip/st010/st010.cpp chip/st010/*
+obj/bsx.$(obj)    : chip/bsx/bsx.cpp chip/bsx/*
+obj/srtc.$(obj)   : chip/srtc/srtc.cpp chip/srtc/*
+obj/sdd1.$(obj)   : chip/sdd1/sdd1.cpp chip/sdd1/*
+obj/spc7110.$(obj): chip/spc7110/spc7110.cpp chip/spc7110/*
+obj/cx4.$(obj)    : chip/cx4/cx4.cpp chip/cx4/*
+obj/dsp1.$(obj)   : chip/dsp1/dsp1.cpp chip/dsp1/*
+obj/dsp2.$(obj)   : chip/dsp2/dsp2.cpp chip/dsp2/*
+obj/dsp3.$(obj)   : chip/dsp3/dsp3.cpp chip/dsp3/*
+obj/dsp4.$(obj)   : chip/dsp4/dsp4.cpp chip/dsp4/*
+obj/obc1.$(obj)   : chip/obc1/obc1.cpp chip/obc1/*
+obj/st010.$(obj)  : chip/st010/st010.cpp chip/st010/*
 
 ############
 ### zlib ###
@@ -270,8 +247,8 @@ build: $(objects)
 	$(strip $(cpp) $(call mkbin,../bsnes) $(objects) $(link))
 
 install:
-	install -m 755 ../bsnes $(prefix)/bin/bsnes
-	install -m 644 data/bsnes.png $(prefix)/share/icons/bsnes.png
+	install -D -m 755 ../bsnes $(DESTDIR)$(prefix)/bin/bsnes
+	install -D -m 644 data/bsnes.png $(DESTDIR)$(prefix)/share/icons/bsnes.png
 
 clean:
 	-@$(call delete,obj/*.$(obj))

src/base.h

@@ -1,38 +1,39 @@
-#define BSNES_VERSION "0.028"
+#define BSNES_VERSION "0.033"
 #define BSNES_TITLE   "bsnes v" BSNES_VERSION
 
 #define BUSCORE sBus
 #define CPUCORE sCPU
 #define SMPCORE sSMP
-#define DSPCORE bDSP
+#define DSPCORE sDSP
 #define PPUCORE bPPU
 
-//FAVOR_ACCURACY calculates RTO during frameskip, whereas FAVOR_SPEED does not
+//S-DSP can be encapsulated into a state machine using #define magic
+//this avoids ~2.048m co_switch() calls per second (~5% speedup)
+#define USE_STATE_MACHINE
+
+//FAST_FRAMESKIP disables calculation of RTO during frameskip
 //frameskip offers near-zero speedup if RTO is calculated
 //accuracy is not affected by this define when frameskipping is off
+#define FAST_FRAMESKIP
 
-//#define FAVOR_ACCURACY
-#define FAVOR_SPEED
-
-//game genie + pro action replay code support (~1-3% speed hit)
+//game genie + pro action replay code support (~2% speed hit)
 #define CHEAT_SYSTEM
 
-#if !defined(ARCH_LSB) && !defined(ARCH_MSB)
-  #define ARCH_LSB //guess
-#endif
-
 #include <nall/algorithm.hpp>
 #include <nall/array.hpp>
 #include <nall/bit.hpp>
 #include <nall/config.hpp>
+#include <nall/detect.hpp>
 #include <nall/function.hpp>
+#include <nall/modulo.hpp>
 #include <nall/new.hpp>
 #include <nall/sort.hpp>
+#include <nall/stdint.hpp>
 #include <nall/string.hpp>
 #include <nall/vector.hpp>
 using namespace nall;
 
-#include <libco.h>
+#include <libco/libco.h>
 #include <bbase.h>
 
 //platform-specific global functions

src/cart/cart.cpp

@@ -1,5 +1,9 @@
-#include "../base.h"
-
+#include "../base.h"
+#define CART_CPP
+
+#include <nall/crc32.hpp>
+#include <nall/ups.hpp>
+
 #include "cart_normal.cpp"
 #include "cart_bsx.cpp"
 #include "cart_bsc.cpp"
@@ -9,7 +13,7 @@
 #include "cart_header.cpp"
 
 namespace memory {
-  MappedRAM cartrom, cartram;
+  MappedRAM cartrom, cartram, cartrtc;
   MappedRAM bscram;
   MappedRAM stArom, stAram;
   MappedRAM stBrom, stBram;
@@ -23,12 +27,12 @@ Cartridge::Region Cartridge::region() { return info.region; }
 bool Cartridge::loaded() { return cart.loaded; }
 
 void Cartridge::load_begin(CartridgeType cart_type) {
-  cart.rom = cart.ram = 0;
+  cart.rom = cart.ram = cart.rtc = 0;
   bs.ram   = 0;
   stA.rom  = stA.ram  = 0;
   stB.rom  = stB.ram  = 0;
 
-  cart.rom_size = cart.ram_size = 0;
+  cart.rom_size = cart.ram_size = cart.rtc_size = 0;
   bs.ram_size   = 0;
   stA.rom_size  = stA.ram_size  = 0;
   stB.rom_size  = stB.ram_size  = 0;
@@ -40,19 +44,21 @@ void Cartridge::load_begin(CartridgeType cart_type) {
   info.bsxflash = false;
   info.st       = false;
 
-  info.superfx = false;
-  info.sa1     = false;
-  info.srtc    = false;
-  info.sdd1    = false;
-  info.cx4     = false;
-  info.dsp1    = false;
-  info.dsp2    = false;
-  info.dsp3    = false;
-  info.dsp4    = false;
-  info.obc1    = false;
-  info.st010   = false;
-  info.st011   = false;
-  info.st018   = false;
+  info.superfx    = false;
+  info.sa1        = false;
+  info.srtc       = false;
+  info.sdd1       = false;
+  info.spc7110    = false;
+  info.spc7110rtc = false;
+  info.cx4        = false;
+  info.dsp1       = false;
+  info.dsp2       = false;
+  info.dsp3       = false;
+  info.dsp4       = false;
+  info.obc1       = false;
+  info.st010      = false;
+  info.st011      = false;
+  info.st018      = false;
 
   info.dsp1_mapper = DSP1Unmapped;
 
@@ -68,6 +74,7 @@ void Cartridge::load_begin(CartridgeType cart_type) {
 void Cartridge::load_end() {
   memory::cartrom.map(cart.rom, cart.rom_size);
   memory::cartram.map(cart.ram, cart.ram_size);
+  memory::cartrtc.map(cart.rtc, cart.rtc_size);
   memory::bscram.map(bs.ram, bs.ram_size);
   memory::stArom.map(stA.rom, stA.rom_size);
   memory::stAram.map(stA.ram, stA.ram_size);
@@ -82,12 +89,9 @@ void Cartridge::load_end() {
   memory::stBrom.write_protect(true);
   memory::stBram.write_protect(false);
 
-char fn[PATH_MAX];
-  strcpy(fn, cart.fn);
-  modify_extension(fn, "cht");
-  if(fexists(fn)) {
+  if(fexists(get_cheat_filename(cart.fn, "cht"))) {
     cheat.clear();
-    cheat.load(fn);
+    cheat.load(cheatfn);
   }
 
   cart.loaded = true;
@@ -100,25 +104,26 @@ bool Cartridge::unload() {
   bus.unload_cart();
 
   switch(info.type) {
-    case CartridgeNormal: unload_cart_normal(); break;
-    case CartridgeBSX: unload_cart_bsx(); break;
-    case CartridgeBSC: unload_cart_bsc(); break;
-    case CartridgeSufamiTurbo: unload_cart_st(); break;
+    case CartridgeNormal:      unload_cart_normal(); break;
+    case CartridgeBSX:         unload_cart_bsx();    break;
+    case CartridgeBSC:         unload_cart_bsc();    break;
+    case CartridgeSufamiTurbo: unload_cart_st();     break;
   }
 
-  safe_free(cart.rom);
-  safe_free(cart.ram);
-  safe_free(bs.ram);
-  safe_free(stA.rom);
-  safe_free(stA.ram);
-  safe_free(stB.rom);
-  safe_free(stB.ram);
+  if(cart.rom) { delete[] cart.rom; cart.rom = 0; }
+  if(cart.ram) { delete[] cart.ram; cart.ram = 0; }
+  if(cart.rtc) { delete[] cart.rtc; cart.rtc = 0; }
+  if(bs.ram)   { delete[] bs.ram;   bs.ram   = 0; }
+  if(stA.rom)  { delete[] stA.rom;  stA.rom  = 0; }
+  if(stA.ram)  { delete[] stA.ram;  stA.ram  = 0; }
+  if(stB.rom)  { delete[] stB.rom;  stB.rom  = 0; }
+  if(stB.ram)  { delete[] stB.ram;  stB.ram  = 0; }
 
-char fn[PATH_MAX];
+  char fn[PATH_MAX];
   strcpy(fn, cart.fn);
   modify_extension(fn, "cht");
-  if(cheat.count() > 0 || fexists(fn)) {
-    cheat.save(fn);
+  if(cheat.count() > 0 || fexists(get_cheat_filename(cart.fn, "cht"))) {
+    cheat.save(cheatfn);
     cheat.clear();
   }
 

src/cart/cart.h

@@ -20,11 +20,11 @@ public:
     CKSUM     = 0x1e,
     RESL      = 0x3c,
     RESH      = 0x3d,
-  };
-
-  enum Region {
-    NTSC,
-    PAL,
+  };
+
+  enum Region {
+    NTSC,
+    PAL,
   };
 
   enum MemoryMapper {
@@ -32,6 +32,7 @@ public:
     HiROM,
     ExLoROM,
     ExHiROM,
+    SPC7110ROM,
     BSXROM,
     BSCLoROM,
     BSCHiROM,
@@ -48,8 +49,8 @@ public:
   struct {
     bool loaded;
     char fn[PATH_MAX];
-    uint8 *rom, *ram;
-    uint rom_size, ram_size;
+    uint8 *rom, *ram, *rtc;
+    uint rom_size, ram_size, rtc_size;
   } cart;
 
   struct {
@@ -67,7 +68,8 @@ public:
   struct {
     CartridgeType type;
 
-    uint32 crc32;
+    uint32 crc32;
+    char filename[PATH_MAX * 4];
     char name[128];
 
     Region region;
@@ -82,7 +84,9 @@ public:
     bool superfx;
     bool sa1;
     bool srtc;
-    bool sdd1;
+    bool sdd1;
+    bool spc7110;
+    bool spc7110rtc;
     bool cx4;
     bool dsp1;
     bool dsp2;
@@ -119,21 +123,34 @@ public:
   void find_header();
   void read_header();
   void read_extended_header();
-
-  bool load_file(const char *fn, uint8 *&data, uint &size);
-  bool save_file(const char *fn, uint8 *data, uint size);
-  char* modify_extension(char *filename, const char *extension);
-  char* get_save_filename(const char *source, const char *extension);
+
+  enum CompressionMode {
+    CompressionNone,    //always load without compression
+    CompressionInspect, //use file header inspection
+    CompressionAuto,    //use file extension or file header inspection (configured by user)
+  };
+  bool load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression = CompressionNone);
+  bool save_file(const char *fn, uint8 *data, uint size);
+  bool apply_patch(const uint8_t *pdata, unsigned psize, uint8_t *&data, unsigned &size);
+  char* modify_extension(char *filename, const char *extension);
+  char* get_base_filename(char *filename);
+  char* get_path_filename(char *filename, const char *path, const char *source, const char *extension);
+  char* get_patch_filename(const char *source, const char *extension);
+  char* get_save_filename(const char *source, const char *extension);
+  char* get_cheat_filename(const char *source, const char *extension);
 
   Cartridge();
   ~Cartridge();
 
-private:
+private:
+  char patchfn[PATH_MAX];
   char savefn[PATH_MAX];
+  char rtcfn[PATH_MAX];
+  char cheatfn[PATH_MAX];
 };
 
 namespace memory {
-  extern MappedRAM cartrom, cartram;
+  extern MappedRAM cartrom, cartram, cartrtc;
   extern MappedRAM bscram;
   extern MappedRAM stArom, stAram;
   extern MappedRAM stBrom, stBram;

src/cart/cart_bsc.cpp

@@ -1,3 +1,5 @@
+#ifdef CART_CPP
+
 void Cartridge::load_cart_bsc(const char *base, const char *slot) {
   if(!base || !*base) return;
 
@@ -5,15 +7,24 @@ void Cartridge::load_cart_bsc(const char *base, const char *slot) {
   strcpy(bs.fn, slot ? slot : "");
   load_begin(CartridgeBSC);
 
-uint8 *data;
-uint size;
-  load_file(cart.fn, data, size);
+  uint8_t *data = 0;
+  unsigned size;
+  load_file(cart.fn, data, size, CompressionAuto);
   cart.rom = data, cart.rom_size = size;
 
+  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
+    apply_patch(data, size, cart.rom, cart.rom_size);
+    delete[] data;
+  }
+
   if(*bs.fn) {
-    if(load_file(bs.fn, data, size) == true) {
+    if(load_file(bs.fn, data, size, CompressionAuto) == true) {
       info.bsxflash = true;
       bs.ram = data, bs.ram_size = size;
+      if(load_file(get_patch_filename(bs.fn, "ups"), data, size, CompressionInspect) == true) {
+        apply_patch(data, size, bs.ram, bs.ram_size);
+        delete[] data;
+      }
     }
   }
 
@@ -24,18 +35,31 @@ uint size;
   info.region = NTSC;
 
   if(info.ram_size > 0) {
-    cart.ram = (uint8*)malloc(cart.ram_size = info.ram_size);
+    cart.ram = new uint8_t[cart.ram_size = info.ram_size];
     memset(cart.ram, 0xff, cart.ram_size);
 
-    if(load_file(get_save_filename(cart.fn, "srm"), data, size) == true) {
+    if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
       memcpy(cart.ram, data, min(size, cart.ram_size));
-      safe_free(data);
+      delete[] data;
     }
   }
 
   load_end();
+
+  //set base filename
+  strcpy(info.filename, cart.fn);
+  get_base_filename(info.filename);
+  if(*bs.fn) {
+    char filenameBS[PATH_MAX];
+    strcpy(filenameBS, bs.fn);
+    get_base_filename(filenameBS);
+    strcat(info.filename, " + ");
+    strcat(info.filename, filenameBS);
+  }
 }
 
 void Cartridge::unload_cart_bsc() {
   if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
 }
+
+#endif //ifdef CART_CPP

src/cart/cart_bsx.cpp

@@ -1,3 +1,5 @@
+#ifdef CART_CPP
+
 void Cartridge::load_cart_bsx(const char *base, const char *slot) {
   if(!base || !*base) return;
 
@@ -10,36 +12,50 @@ void Cartridge::load_cart_bsx(const char *base, const char *slot) {
   info.mapper = BSXROM;
   info.region = NTSC;
 
-uint8 *data;
-uint size;
-  load_file(cart.fn, data, size);
+  uint8_t *data = 0;
+  unsigned size;
+  load_file(cart.fn, data, size, CompressionAuto);
   cart.rom = data, cart.rom_size = size;
   cart.ram = 0, cart.ram_size = 0;
 
+  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
+    apply_patch(data, size, cart.rom, cart.rom_size);
+    delete[] data;
+  }
+
   memset(bsxcart.sram.handle (), 0x00, bsxcart.sram.size ());
   memset(bsxcart.psram.handle(), 0x00, bsxcart.psram.size());
 
-  if(load_file(get_save_filename(cart.fn, "srm"), data, size) == true) {
+  if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
     memcpy(bsxcart.sram.handle (), data, min(bsxcart.sram.size (), size));
-    safe_free(data);
+    delete[] data;
   }
 
-  if(load_file(get_save_filename(cart.fn, "psr"), data, size) == true) {
+  if(load_file(get_save_filename(cart.fn, "psr"), data, size, CompressionNone) == true) {
     memcpy(bsxcart.psram.handle(), data, min(bsxcart.psram.size(), size));
-    safe_free(data);
+    delete[] data;
   }
 
   if(*bs.fn) {
-    if(load_file(bs.fn, data, size) == true) {
+    if(load_file(bs.fn, data, size, CompressionAuto) == true) {
       info.bsxflash = true;
       bs.ram = data, bs.ram_size = size;
+      if(load_file(get_patch_filename(bs.fn, "ups"), data, size, CompressionInspect) == true) {
+        apply_patch(data, size, bs.ram, bs.ram_size);
+        delete[] data;
+      }
     }
   }
 
   load_end();
+
+  strcpy(info.filename, !*bs.fn ? cart.fn : bs.fn);
+  get_base_filename(info.filename);
 }
 
 void Cartridge::unload_cart_bsx() {
   save_file(get_save_filename(cart.fn, "srm"), bsxcart.sram.handle (), bsxcart.sram.size ());
   save_file(get_save_filename(cart.fn, "psr"), bsxcart.psram.handle(), bsxcart.psram.size());
 }
+
+#endif //ifdef CART_CPP

src/cart/cart_file.cpp

@@ -1,3 +1,5 @@
+#ifdef CART_CPP
+
 #include "../reader/filereader.h"
 
 #if defined(GZIP_SUPPORT)
@@ -10,7 +12,7 @@
 #endif
 
 char* Cartridge::modify_extension(char *filename, const char *extension) {
-int i;
+  int i;
   for(i = strlen(filename); i >= 0; i--) {
     if(filename[i] == '.') break;
     if(filename[i] == '/') break;
@@ -20,42 +22,85 @@ int i;
   strcat(filename, ".");
   strcat(filename, extension);
   return filename;
+}
+
+//remove directory information and file extension ("/foo/bar.ext" -> "bar")
+char* Cartridge::get_base_filename(char *filename) {
+  //remove extension
+  for(int i = strlen(filename) - 1; i >= 0; i--) {
+    if(filename[i] == '.') {
+      filename[i] = 0;
+      break;
+    }
+  }
+
+  //remove directory information
+  for(int i = strlen(filename) - 1; i >= 0; i--) {
+    if(filename[i] == '/' || filename[i] == '\\') {
+      i++;
+      char *output = filename;
+      while(true) {
+        *output++ = filename[i];
+        if(!filename[i]) break;
+        i++;
+      }
+      break;
+    }
+  }
 }
 
-char* Cartridge::get_save_filename(const char *source, const char *extension) {
-  strcpy(savefn, source);
-  for(char *p = savefn; *p; p++) { if(*p == '\\') *p = '/'; }
-  modify_extension(savefn, extension);
+char* Cartridge::get_path_filename(char *filename, const char *path, const char *source, const char *extension) {
+  strcpy(filename, source);
+  for(char *p = filename; *p; p++) { if(*p == '\\') *p = '/'; }
+  modify_extension(filename, extension);
 
-//override path with user-specified folder, if one was defined
-  if(config::path.save != "") {
-  lstring part;
-    split(part, "/", savefn);
-  string fn = (const char*)config::path.save;
+  //override path with user-specified folder, if one was defined
+  if(*path) {
+    lstring part;
+    split(part, "/", filename);
+    string fn = path;
     if(strend(fn, "/") == false) strcat(fn, "/");
     strcat(fn, part[count(part) - 1]);
-    strcpy(savefn, fn);
+    strcpy(filename, fn);
 
-  //resolve relative path, if found
+    //resolve relative path, if found
     if(strbegin(fn, "./") == true) {
       ltrim(fn, "./");
-      strcpy(savefn, config::path.base);
-      strcat(savefn, fn);
+      strcpy(filename, config::path.base);
+      strcat(filename, fn);
     }
   }
 
-  return savefn;
+  return filename;
+}
+
+char* Cartridge::get_patch_filename(const char *source, const char *extension) {
+  return get_path_filename(patchfn, config::path.patch, source, extension);
 }
+
+char* Cartridge::get_save_filename(const char *source, const char *extension) {
+  return get_path_filename(savefn, config::path.save, source, extension);
+}
+
+char* Cartridge::get_cheat_filename(const char *source, const char *extension) {
+  return get_path_filename(cheatfn, config::path.cheat, source, extension);
+}
 
-bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size) {
-  dprintf("* Loading \"%s\"...", fn);
+bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression) {
+  dprintf("* Loading \"%s\" ...", fn);
 
-  if(fexists(fn) == false) return false;
+  if(fexists(fn) == false) return false;
+
+  Reader::Type filetype = Reader::Normal;
+  if(compression == CompressionInspect) filetype = Reader::detect(fn, true);
+  if(compression == CompressionAuto) filetype = Reader::detect(fn, config::file.autodetect_type);
 
-  switch(Reader::detect(fn)) {
-    default:
-    case Reader::RF_NORMAL: {
-    FileReader ff(fn);
+  switch(filetype) {
+    default:
+      dprintf("* Warning: filetype detected as unsupported compression type.");
+      dprintf("* Will attempt to load as uncompressed file -- may fail.");
+    case Reader::Normal: {
+      FileReader ff(fn);
       if(!ff.ready()) {
         alert("Error loading image file (%s)!", fn);
         return false;
@@ -64,9 +109,9 @@ bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size) {
       data = ff.read();
     } break;
 
-  #ifdef GZIP_SUPPORT
-    case Reader::RF_GZ: {
-    GZReader gf(fn);
+    #ifdef GZIP_SUPPORT
+    case Reader::GZIP: {
+      GZReader gf(fn);
       if(!gf.ready()) {
         alert("Error loading image file (%s)!", fn);
         return false;
@@ -75,17 +120,17 @@ bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size) {
       data = gf.read();
     } break;
 
-    case Reader::RF_ZIP: {
-    ZipReader zf(fn);
+    case Reader::ZIP: {
+      ZipReader zf(fn);
       size = zf.size();
       data = zf.read();
     } break;
-  #endif
+    #endif
 
-  #ifdef JMA_SUPPORT
-    case Reader::RF_JMA: {
+    #ifdef JMA_SUPPORT
+    case Reader::JMA: {
       try {
-      JMAReader jf(fn);
+        JMAReader jf(fn);
         size = jf.size();
         data = jf.read();
       } catch(JMA::jma_errors jma_error) {
@@ -93,15 +138,42 @@ bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size) {
         return false;
       }
     } break;
-  #endif
+    #endif
   }
 
   return true;
+}
+
+bool Cartridge::apply_patch(const uint8_t *pdata, const unsigned psize, uint8_t *&data, unsigned &size) {
+  uint8_t *outdata = 0;
+  unsigned outsize;
+  ups patcher;
+  ups::result result = patcher.apply(pdata, psize, data, size, outdata, outsize);
+
+  bool apply = false;
+  if(result == ups::ok) apply = true;
+  if(config::file.bypass_patch_crc32 == true) {
+    if(result == ups::input_crc32_invalid) apply = true;
+    if(result == ups::output_crc32_invalid) apply = true;
+  }
+
+  if(apply == true) {
+    delete[] data;
+    data = new uint8_t[size = outsize];
+    memcpy(data, outdata, outsize);
+  } else {
+    dprintf("* Warning: patch application failed!");
+  }
+
+  if(outdata) delete[] outdata;
 }
 
-bool Cartridge::save_file(const char *fn, uint8 *data, uint size) {
-FileWriter ff(fn);
-  if(!ff.ready())return false;
-  ff.write(data, size);
-  return true;
+bool Cartridge::save_file(const char *fn, uint8 *data, uint size) {
+  FILE *fp = fopen(fn, "wb");
+  if(!fp) return false;
+  fwrite(data, 1, size, fp);
+  fclose(fp);
+  return true;
 }
+
+#endif //ifdef CART_CPP

src/cart/cart_header.cpp

@@ -1,184 +1,195 @@
-void Cartridge::read_header() {
-uint8 *rom = cart.rom;
-uint index = info.header_index;
-uint8 mapper   = rom[index + MAPPER];
-uint8 rom_type = rom[index + ROM_TYPE];
-uint8 company  = rom[index + COMPANY];
-uint8 region   = rom[index + REGION] & 0x7f;
-
-//detect presence of BS-X flash cartridge connector (reads extended header information)
-bool has_bsxflash = false;
-  if(rom[index - 14] == 'Z') {
-    if(rom[index - 11] == 'J') {
-    uint8 n13 = rom[index - 13];
-      if((n13 >= 'A' && n13 <= 'Z') || (n13 >= '0' && n13 <= '9')) {
-        if(company == 0x33 || (rom[index - 10] == 0x00 && rom[index - 4] == 0x00)) {
-          has_bsxflash = true;
-        }
-      }
-    }
-  }
-
-  if(has_bsxflash == true) {
-    info.mapper = index == 0x7fc0 ? BSCLoROM : BSCHiROM;
-  } else if(index == 0x7fc0 && cart.rom_size >= 0x401000) {
-    info.mapper = ExLoROM;
-  } else if(index == 0x7fc0 && mapper == 0x32) {
-    info.mapper = ExLoROM;
-  } else if(index == 0x7fc0) {
-    info.mapper = LoROM;
-  } else if(index == 0xffc0) {
-    info.mapper = HiROM;
-  } else { //index == 0x40ffc0
-    info.mapper = ExHiROM;
-  }
-
-  if(mapper == 0x20 && (rom_type == 0x13 || rom_type == 0x14 || rom_type == 0x15 || rom_type == 0x1a)) {
-    info.superfx = true;
-  }
-
-  if(mapper == 0x23 && (rom_type == 0x34 || rom_type == 0x35)) {
-    info.sa1 = true;
-  }
-
-  if(mapper == 0x35 && rom_type == 0x55) {
-    info.srtc = true;
-  }
-
-  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
-    info.sdd1 = true;
-  }
-
-  if(mapper == 0x20 && rom_type == 0xf3) {
-    info.cx4 = true;
-  }
-
-  if((mapper == 0x20 || mapper == 0x21) && rom_type == 0x03) {
-    info.dsp1 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x05 && company != 0xb2) {
-    info.dsp1 = true;
-  }
-
-  if(mapper == 0x31 && (rom_type == 0x03 || rom_type == 0x05)) {
-    info.dsp1 = true;
-  }
-
-  if(info.dsp1 == true) {
-    if((mapper & 0x2f) == 0x20 && cart.rom_size <= 0x100000) {
-      info.dsp1_mapper = DSP1LoROM1MB;
-    } else if((mapper & 0x2f) == 0x20) {
-      info.dsp1_mapper = DSP1LoROM2MB;
-    } else if((mapper & 0x2f) == 0x21) {
-      info.dsp1_mapper = DSP1HiROM;
-    }
-  }
-
-  if(mapper == 0x20 && rom_type == 0x05) {
-    info.dsp2 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x05 && company == 0xb2) {
-    info.dsp3 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x03) {
-    info.dsp4 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x25) {
-    info.obc1 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0xf6) {
-  //TODO: both ST010 and ST011 share the same mapper + rom_type
-  //need way to determine which is which
-  //for now, default to supported ST010
-    info.st010 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0xf5) {
-    info.st018 = true;
-  }
-
-  if(rom[info.header_index + RAM_SIZE] & 7) {
-    info.ram_size = 1024 << (rom[info.header_index + RAM_SIZE] & 7);
-  } else {
-    info.ram_size = 0;
-  }
-
-//0, 1, 13 = NTSC; 2 - 12 = PAL
-  info.region = (region <= 1 || region >= 13) ? NTSC : PAL;
-
-  memcpy(&info.name, &rom[info.header_index + CART_NAME], 21);
-  info.name[21] = 0;
-
-  for(int i = 0; i < 22; i++) {
-    if(info.name[i] & 0x80) {
-      info.name[i] = '?';
-    }
-  }
-}
-
-void Cartridge::find_header() {
-int32 score_lo = 0,
-      score_hi = 0,
-      score_ex = 0;
-uint8 *rom = cart.rom;
-
-  if(cart.rom_size < 0x010000) {
-  //cart too small to be anything but lorom
-    info.header_index = 0x007fc0;
-    return;
-  }
-
-  if((rom[0x7fc0 + MAPPER] & ~0x10) == 0x20)score_lo++;
-  if((rom[0xffc0 + MAPPER] & ~0x10) == 0x21)score_hi++;
-
-  if(rom[0x7fc0 + ROM_TYPE] < 0x08)score_lo++;
-  if(rom[0xffc0 + ROM_TYPE] < 0x08)score_hi++;
-
-  if(rom[0x7fc0 + ROM_SIZE] < 0x10)score_lo++;
-  if(rom[0xffc0 + ROM_SIZE] < 0x10)score_hi++;
-
-  if(rom[0x7fc0 + RAM_SIZE] < 0x08)score_lo++;
-  if(rom[0xffc0 + RAM_SIZE] < 0x08)score_hi++;
-
-  if(rom[0x7fc0 + REGION] < 14)score_lo++;
-  if(rom[0xffc0 + REGION] < 14)score_hi++;
-
-  if(rom[0x7fc0 + COMPANY] < 3)score_lo++;
-  if(rom[0xffc0 + COMPANY] < 3)score_hi++;
-
-  if(rom[0x7fc0 + RESH] & 0x80)score_lo += 2;
-  if(rom[0xffc0 + RESH] & 0x80)score_hi += 2;
-
-uint16 cksum, icksum;
-  cksum  = rom[0x7fc0 +  CKSUM] | (rom[0x7fc0 +  CKSUM + 1] << 8);
-  icksum = rom[0x7fc0 + ICKSUM] | (rom[0x7fc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_lo += 8;
-  }
-
-  cksum  = rom[0xffc0 +  CKSUM] | (rom[0xffc0 +  CKSUM + 1] << 8);
-  icksum = rom[0xffc0 + ICKSUM] | (rom[0xffc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_hi += 8;
-  }
-
-  if(cart.rom_size < 0x401000) {
-    score_ex = 0;
-  } else {
-    if(rom[0x7fc0 + MAPPER] == 0x32)score_lo++;
-    else score_ex += 16;
-  }
-
-  if(score_lo >= score_hi && score_lo >= score_ex) {
-    info.header_index = 0x007fc0;
-  } else if(score_hi >= score_ex) {
-    info.header_index = 0x00ffc0;
-  } else {
-    info.header_index = 0x40ffc0;
-  }
-}
+#ifdef CART_CPP
+
+void Cartridge::read_header() {
+  uint8 *rom = cart.rom;
+  uint index = info.header_index;
+  uint8 mapper   = rom[index + MAPPER];
+  uint8 rom_type = rom[index + ROM_TYPE];
+  uint8 company  = rom[index + COMPANY];
+  uint8 region   = rom[index + REGION] & 0x7f;
+
+  //detect presence of BS-X flash cartridge connector (reads extended header information)
+  bool has_bsxflash = false;
+  if(rom[index - 14] == 'Z') {
+    if(rom[index - 11] == 'J') {
+      uint8 n13 = rom[index - 13];
+      if((n13 >= 'A' && n13 <= 'Z') || (n13 >= '0' && n13 <= '9')) {
+        if(company == 0x33 || (rom[index - 10] == 0x00 && rom[index - 4] == 0x00)) {
+          has_bsxflash = true;
+        }
+      }
+    }
+  }
+
+  if(has_bsxflash == true) {
+    info.mapper = index == 0x7fc0 ? BSCLoROM : BSCHiROM;
+  } else if(index == 0x7fc0 && cart.rom_size >= 0x401000) {
+    info.mapper = ExLoROM;
+  } else if(index == 0x7fc0 && mapper == 0x32) {
+    info.mapper = ExLoROM;
+  } else if(index == 0x7fc0) {
+    info.mapper = LoROM;
+  } else if(index == 0xffc0) {
+    info.mapper = HiROM;
+  } else { //index == 0x40ffc0
+    info.mapper = ExHiROM;
+  }
+
+  if(mapper == 0x20 && (rom_type == 0x13 || rom_type == 0x14 || rom_type == 0x15 || rom_type == 0x1a)) {
+    info.superfx = true;
+  }
+
+  if(mapper == 0x23 && (rom_type == 0x34 || rom_type == 0x35)) {
+    info.sa1 = true;
+  }
+
+  if(mapper == 0x35 && rom_type == 0x55) {
+    info.srtc = true;
+  }
+
+  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
+    info.sdd1 = true;
+  }
+
+  if(mapper == 0x3a && (rom_type == 0xf5 || rom_type == 0xf9)) {
+    info.spc7110 = true;
+    info.spc7110rtc = (rom_type == 0xf9);
+    info.mapper = SPC7110ROM;
+  }
+
+  if(mapper == 0x20 && rom_type == 0xf3) {
+    info.cx4 = true;
+  }
+
+  if((mapper == 0x20 || mapper == 0x21) && rom_type == 0x03) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x05 && company != 0xb2) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x31 && (rom_type == 0x03 || rom_type == 0x05)) {
+    info.dsp1 = true;
+  }
+
+  if(info.dsp1 == true) {
+    if((mapper & 0x2f) == 0x20 && cart.rom_size <= 0x100000) {
+      info.dsp1_mapper = DSP1LoROM1MB;
+    } else if((mapper & 0x2f) == 0x20) {
+      info.dsp1_mapper = DSP1LoROM2MB;
+    } else if((mapper & 0x2f) == 0x21) {
+      info.dsp1_mapper = DSP1HiROM;
+    }
+  }
+
+  if(mapper == 0x20 && rom_type == 0x05) {
+    info.dsp2 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x05 && company == 0xb2) {
+    info.dsp3 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x03) {
+    info.dsp4 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x25) {
+    info.obc1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf6) {
+    //TODO: both ST010 and ST011 share the same mapper + rom_type.
+    //need way to determine which is which.
+    //for now, default to supported ST010.
+    info.st010 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf5) {
+    info.st018 = true;
+  }
+
+  if(rom[info.header_index + RAM_SIZE] & 7) {
+    info.ram_size = 1024 << (rom[info.header_index + RAM_SIZE] & 7);
+  } else {
+    info.ram_size = 0;
+  }
+
+  //0, 1, 13 = NTSC; 2 - 12 = PAL
+  info.region = (region <= 1 || region >= 13) ? NTSC : PAL;
+
+  memcpy(&info.name, &rom[info.header_index + CART_NAME], 21);
+  info.name[21] = 0;
+  trim(info.name);
+
+  //convert undisplayable characters (half-width katakana, etc) to '?' characters
+  for(int i = 0; i < 21; i++) {
+    if(info.name[i] & 0x80) info.name[i] = '?';
+  }
+
+  //always display something
+  if(!info.name[0]) strcpy(info.name, "(untitled)");
+}
+
+void Cartridge::find_header() {
+  int32 score_lo = 0, score_hi = 0, score_ex = 0;
+  uint8_t *rom = cart.rom;
+
+  if(cart.rom_size < 0x010000) {
+    //cart too small to be anything but lorom
+    info.header_index = 0x007fc0;
+    return;
+  }
+
+  if((rom[0x7fc0 + MAPPER] & ~0x10) == 0x20) score_lo++;
+  if((rom[0xffc0 + MAPPER] & ~0x10) == 0x21) score_hi++;
+
+  if(rom[0x7fc0 + ROM_TYPE] < 0x08) score_lo++;
+  if(rom[0xffc0 + ROM_TYPE] < 0x08) score_hi++;
+
+  if(rom[0x7fc0 + ROM_SIZE] < 0x10) score_lo++;
+  if(rom[0xffc0 + ROM_SIZE] < 0x10) score_hi++;
+
+  if(rom[0x7fc0 + RAM_SIZE] < 0x08) score_lo++;
+  if(rom[0xffc0 + RAM_SIZE] < 0x08) score_hi++;
+
+  if(rom[0x7fc0 + REGION] < 14) score_lo++;
+  if(rom[0xffc0 + REGION] < 14) score_hi++;
+
+  if(rom[0x7fc0 + COMPANY] < 3) score_lo++;
+  if(rom[0xffc0 + COMPANY] < 3) score_hi++;
+
+  if(rom[0x7fc0 + RESH] & 0x80) score_lo += 2;
+  if(rom[0xffc0 + RESH] & 0x80) score_hi += 2;
+
+  uint16 cksum, icksum;
+  cksum  = rom[0x7fc0 +  CKSUM] | (rom[0x7fc0 +  CKSUM + 1] << 8);
+  icksum = rom[0x7fc0 + ICKSUM] | (rom[0x7fc0 + ICKSUM + 1] << 8);
+  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
+    score_lo += 8;
+  }
+
+  cksum  = rom[0xffc0 +  CKSUM] | (rom[0xffc0 +  CKSUM + 1] << 8);
+  icksum = rom[0xffc0 + ICKSUM] | (rom[0xffc0 + ICKSUM + 1] << 8);
+  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
+    score_hi += 8;
+  }
+
+  if(cart.rom_size < 0x401000) {
+    score_ex = 0;
+  } else {
+    if(rom[0x7fc0 + MAPPER] == 0x32) score_lo++;
+    else score_ex += 12;
+  }
+
+  if(score_lo >= score_hi && score_lo >= score_ex) {
+    info.header_index = 0x007fc0;
+  } else if(score_hi >= score_ex) {
+    info.header_index = 0x00ffc0;
+  } else {
+    info.header_index = 0x40ffc0;
+  }
+}
+
+#endif //ifdef CART_CPP

src/cart/cart_normal.cpp

@@ -1,22 +1,29 @@
+#ifdef CART_CPP
+
 void Cartridge::load_cart_normal(const char *filename) {
   if(!filename || !*filename) return;
 
-uint8 *data;
-uint size;
-  if(load_file(filename, data, size) == false) return;
+  uint8_t *data = 0;
+  unsigned size;
+  if(load_file(filename, data, size, CompressionAuto) == false) return;
   strcpy(cart.fn, filename);
 
   load_begin(CartridgeNormal);
 
-//load ROM data, ignore 512-byte header if detected
+  //load ROM data, ignore 512-byte header if detected
   if((size & 0x7fff) != 512) {
-    cart.rom = (uint8*)malloc(cart.rom_size = size);
+    cart.rom = new uint8_t[cart.rom_size = size];
     memcpy(cart.rom, data, size);
   } else {
-    cart.rom = (uint8*)malloc(cart.rom_size = size - 512);
+    cart.rom = new uint8_t[cart.rom_size = size - 512];
     memcpy(cart.rom, data + 512, size - 512);
   }
-  safe_free(data);
+  delete[] data;
+
+  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
+    apply_patch(data, size, cart.rom, cart.rom_size);
+    delete[] data;
+  }
 
   info.crc32 = crc32_calculate(cart.rom, cart.rom_size);
 
@@ -24,18 +31,33 @@ uint size;
   read_header();
 
   if(info.ram_size > 0) {
-    cart.ram = (uint8*)malloc(cart.ram_size = info.ram_size);
+    cart.ram = new uint8_t[cart.ram_size = info.ram_size];
     memset(cart.ram, 0xff, cart.ram_size);
 
-    if(load_file(get_save_filename(cart.fn, "srm"), data, size) == true) {
+    if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
       memcpy(cart.ram, data, min(size, cart.ram_size));
-      safe_free(data);
+      delete[] data;
+    }
+  }
+
+  if(info.srtc || info.spc7110rtc) {
+    cart.rtc = new(zeromemory) uint8_t[cart.rtc_size = 20];
+    if(load_file(get_save_filename(cart.fn, "rtc"), data, size, CompressionNone) == true) {
+      memcpy(cart.rtc, data, min(size, cart.rtc_size));
+      delete[] data;
     }
   }
 
   load_end();
+
+  //set base filename
+  strcpy(info.filename, cart.fn);
+  get_base_filename(info.filename);
 }
 
 void Cartridge::unload_cart_normal() {
   if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
+  if(cart.rtc) save_file(get_save_filename(cart.fn, "rtc"), cart.rtc, cart.rtc_size);
 }
+
+#endif //ifdef CART_CPP

src/cart/cart_st.cpp

@@ -1,3 +1,5 @@
+#ifdef CART_CPP
+
 void Cartridge::load_cart_st(const char *base, const char *slotA, const char *slotB) {
   if(!base || !*base) return;
 
@@ -10,50 +12,85 @@ void Cartridge::load_cart_st(const char *base, const char *slotA, const char *sl
   info.mapper = STROM;
   info.region = NTSC;
 
-uint8 *data;
-uint size;
-  if(load_file(cart.fn, data, size) == true) {
-    cart.rom = (uint8*)malloc(cart.rom_size = 0x040000);
+  uint8_t *data = 0;
+  unsigned size;
+  if(load_file(cart.fn, data, size, CompressionAuto) == true) {
+    cart.rom = new(zeromemory) uint8_t[cart.rom_size = 0x040000];
     memcpy(cart.rom, data, min(size, cart.rom_size));
-    safe_free(data);
+    delete[] data;
+    if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
+      apply_patch(data, size, cart.rom, cart.rom_size);
+      delete[] data;
+    }
   }
 
   if(*stA.fn) {
-    if(load_file(stA.fn, data, size) == true) {
-      stA.rom = (uint8*)malloc(stA.rom_size = 0x100000);
+    if(load_file(stA.fn, data, size, CompressionAuto) == true) {
+      stA.rom = new(zeromemory) uint8_t[stA.rom_size = 0x100000];
       memcpy(stA.rom, data, min(size, stA.rom_size));
-      safe_free(data);
+      delete[] data;
+      if(load_file(get_patch_filename(stA.fn, "ups"), data, size, CompressionInspect) == true) {
+        apply_patch(data, size, stA.rom, stA.rom_size);
+        delete[] data;
+      }
 
-      stA.ram = (uint8*)malloc(stA.ram_size = 0x020000);
+      stA.ram = new uint8_t[stA.ram_size = 0x020000];
       memset(stA.ram, 0xff, stA.ram_size);
 
-      if(load_file(get_save_filename(stA.fn, "srm"), data, size) == true) {
+      if(load_file(get_save_filename(stA.fn, "srm"), data, size, CompressionNone) == true) {
         memcpy(stA.ram, data, min(size, 0x020000U));
-        safe_free(data);
+        delete[] data;
       }
     }
   }
 
   if(*stB.fn) {
-    if(load_file(stB.fn, data, size) == true) {
-      stB.rom = (uint8*)malloc(stB.rom_size = 0x100000);
+    if(load_file(stB.fn, data, size, CompressionAuto) == true) {
+      stB.rom = new(zeromemory) uint8_t[stB.rom_size = 0x100000];
       memcpy(stB.rom, data, min(size, stB.rom_size));
-      safe_free(data);
+      delete[] data;
+      if(load_file(get_patch_filename(stB.fn, "ups"), data, size, CompressionInspect) == true) {
+        apply_patch(data, size, stB.rom, stB.rom_size);
+        delete[] data;
+      }
 
-      stB.ram = (uint8*)malloc(stB.ram_size = 0x020000);
+      stB.ram = new uint8_t[stB.ram_size = 0x020000];
       memset(stB.ram, 0xff, stB.ram_size);
 
-      if(load_file(get_save_filename(stB.fn, "srm"), data, size) == true) {
+      if(load_file(get_save_filename(stB.fn, "srm"), data, size, CompressionNone) == true) {
         memcpy(stB.ram, data, min(size, 0x020000U));
-        safe_free(data);
+        delete[] data;
       }
     }
   }
 
   load_end();
+
+  //set base filename
+  if(!*stA.fn && !*stB.fn) {
+    strcpy(info.filename, cart.fn);
+    get_base_filename(info.filename);
+  } else if(*stA.fn && !*stB.fn) {
+    strcpy(info.filename, stA.fn);
+    get_base_filename(info.filename);
+  } else if(!*stA.fn && *stB.fn) {
+    strcpy(info.filename, stB.fn);
+    get_base_filename(info.filename);
+  } else {
+    char filenameA[PATH_MAX], filenameB[PATH_MAX];
+    strcpy(filenameA, stA.fn);
+    get_base_filename(filenameA);
+    strcpy(filenameB, stB.fn);
+    get_base_filename(filenameB);
+    strcpy(info.filename, filenameA);
+    strcat(info.filename, " + ");
+    strcat(info.filename, filenameB);
+  }
 }
 
 void Cartridge::unload_cart_st() {
   if(stA.ram) save_file(get_save_filename(stA.fn, "srm"), stA.ram, stA.ram_size);
   if(stB.ram) save_file(get_save_filename(stB.fn, "srm"), stB.ram, stB.ram_size);
 }
+
+#endif //ifdef CART_CPP

src/cheat/cheat.cpp

@@ -10,24 +10,24 @@ Cheat cheat;
  *****/
 
 bool Cheat::decode(char *str, uint32 &addr, uint8 &data, uint8 &type) {
-string t, part;
+  string t, part;
   strcpy(t, str);
   strlower(t());
   if(strlen(t) == 8 || (strlen(t) == 9 && t()[6] == ':')) {
-    type = CT_PRO_ACTION_REPLAY;
+    type = ProActionReplay;
     replace(t, ":", "");
-  uint32 r = strhex((const char*)t);
+    uint32 r = strhex((const char*)t);
     addr = r >> 8;
     data = r & 0xff;
     return true;
   } else if(strlen(t) == 9 && t()[4] == '-') {
-    type = CT_GAME_GENIE;
+    type = GameGenie;
     replace(t, "-", "");
     strtr(t, "df4709156bc8a23e", "0123456789abcdef");
-  uint32 r = strhex((const char*)t);
-  //8421 8421 8421 8421 8421 8421
-  //abcd efgh ijkl mnop qrst uvwx
-  //ijkl qrst opab cduv wxef ghmn
+    uint32 r = strhex((const char*)t);
+    //8421 8421 8421 8421 8421 8421
+    //abcd efgh ijkl mnop qrst uvwx
+    //ijkl qrst opab cduv wxef ghmn
     addr = (!!(r & 0x002000) << 23) | (!!(r & 0x001000) << 22) |
            (!!(r & 0x000800) << 21) | (!!(r & 0x000400) << 20) |
            (!!(r & 0x000020) << 19) | (!!(r & 0x000010) << 18) |
@@ -47,10 +47,10 @@ string t, part;
 }
 
 bool Cheat::encode(char *str, uint32 addr, uint8 data, uint8 type) {
-  if(type == CT_PRO_ACTION_REPLAY) {
+  if(type == ProActionReplay) {
     sprintf(str, "%0.6x:%0.2x", addr, data);
     return true;
-  } else if(type == CT_GAME_GENIE) {
+  } else if(type == GameGenie) {
   uint32 r = addr;
     addr = (!!(r & 0x008000) << 23) | (!!(r & 0x004000) << 22) |
            (!!(r & 0x002000) << 21) | (!!(r & 0x001000) << 20) |
@@ -79,9 +79,9 @@ bool Cheat::encode(char *str, uint32 addr, uint8 data, uint8 type) {
  *****/
 
 uint Cheat::mirror_address(uint addr) {
-  if((addr & 0x40e000) != 0x0000)return addr;
-//8k WRAM mirror
-//$[00-3f|80-bf]:[0000-1fff] -> $7e:[0000-1fff]
+  if((addr & 0x40e000) != 0x0000) return addr;
+  //8k WRAM mirror
+  //$[00-3f|80-bf]:[0000-1fff] -> $7e:[0000-1fff]
   return (0x7e0000 + (addr & 0x1fff));
 }
 
@@ -90,8 +90,8 @@ void Cheat::set(uint32 addr) {
 
   mask[addr >> 3] |= 1 << (addr & 7);
   if((addr & 0xffe000) == 0x7e0000) {
-  //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
-  uint mirror;
+    //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
+    uint mirror;
     for(int x = 0; x <= 0x3f; x++) {
       mirror = ((0x00 + x) << 16) + (addr & 0x1fff);
       mask[mirror >> 3] |= 1 << (mirror & 7);
@@ -104,16 +104,16 @@ void Cheat::set(uint32 addr) {
 void Cheat::clear(uint32 addr) {
   addr = mirror_address(addr);
 
-//is there more than one cheat code using the same address
-//(and likely a different override value) that is enabled?
-//if so, do not clear code lookup table entry for this address.
-uint8 r;
+  //is there more than one cheat code using the same address
+  //(and likely a different override value) that is enabled?
+  //if so, do not clear code lookup table entry for this address.
+  uint8 r;
   if(read(addr, r) == true)return;
 
   mask[addr >> 3] &= ~(1 << (addr & 7));
   if((addr & 0xffe000) == 0x7e0000) {
-  //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
-  uint mirror;
+    //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
+    uint mirror;
     for(int x = 0; x <= 0x3f; x++) {
       mirror = ((0x00 + x) << 16) + (addr & 0x1fff);
       mask[mirror >> 3] &= ~(1 << (mirror & 7));
@@ -133,13 +133,13 @@ uint8 r;
 bool Cheat::read(uint32 addr, uint8 &data) {
   addr = mirror_address(addr);
   for(int i = 0; i < cheat_count; i++) {
-    if(enabled(i) == false)continue;
+    if(enabled(i) == false) continue;
     if(addr == mirror_address(index[i].addr)) {
       data = index[i].data;
       return true;
     }
   }
-//code not found, or code is disabled
+  //code not found, or code is disabled
   return false;
 }
 
@@ -147,9 +147,10 @@ bool Cheat::read(uint32 addr, uint8 &data) {
  * update_cheat_status() will scan to see if any codes are
  * enabled. if any are, make sure the cheat system is on.
  * otherwise, turn cheat system off to speed up emulation.
- *****/
+ *****/
+
 void Cheat::update_cheat_status() {
-  for(int i = 0; i < cheat_count; i++) {
+  for(unsigned i = 0; i < cheat_count; i++) {
     if(index[i].enabled) {
       cheat_enabled = true;
       return;
@@ -163,11 +164,11 @@ void Cheat::update_cheat_status() {
  *****/
 
 bool Cheat::add(bool enable, char *code, char *desc) {
-  if(cheat_count >= CHEAT_LIMIT)return false;
+  if(cheat_count >= CheatLimit) return false;
 
-uint32 addr, len;
-uint8  data, type;
-  if(decode(code, addr, data, type) == false)return false;
+  uint32 addr, len;
+  uint8  data, type;
+  if(decode(code, addr, data, type) == false) return false;
 
   index[cheat_count].enabled = enable;
   index[cheat_count].addr = addr;
@@ -188,17 +189,17 @@ uint8  data, type;
 }
 
 bool Cheat::edit(uint32 n, bool enable, char *code, char *desc) {
-  if(n >= cheat_count)return false;
+  if(n >= cheat_count) return false;
 
-uint32 addr, len;
-uint8  data, type;
-  if(decode(code, addr, data, type) == false)return false;
+  uint32 addr, len;
+  uint8  data, type;
+  if(decode(code, addr, data, type) == false) return false;
 
-//disable current code and clear from code lookup table
+  //disable current code and clear from code lookup table
   index[n].enabled = false;
   clear(index[n].addr);
 
-//update code and enable in code lookup table
+  //update code and enable in code lookup table
   index[n].enabled = enable;
   index[n].addr = addr;
   index[n].data = data;
@@ -217,9 +218,9 @@ uint8  data, type;
 }
 
 bool Cheat::remove(uint32 n) {
-  if(n >= cheat_count)return false;
+  if(n >= cheat_count) return false;
 
-  for(int i = n; i < cheat_count; i++) {
+  for(unsigned i = n; i < cheat_count; i++) {
     index[i].enabled = index[i + 1].enabled;
     index[i].addr    = index[i + 1].addr;
     index[i].data    = index[i + 1].data;
@@ -233,7 +234,7 @@ bool Cheat::remove(uint32 n) {
 }
 
 bool Cheat::get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc) {
-  if(n >= cheat_count)return false;
+  if(n >= cheat_count) return false;
   enable = index[n].enabled;
   addr   = index[n].addr;
   data   = index[n].data;
@@ -247,19 +248,19 @@ bool Cheat::get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, c
  *****/
 
 bool Cheat::enabled(uint32 n) {
-  if(n >= cheat_count)return false;
+  if(n >= cheat_count) return false;
   return index[n].enabled;
 }
 
 void Cheat::enable(uint32 n) {
-  if(n >= cheat_count)return;
+  if(n >= cheat_count) return;
   index[n].enabled = true;
   set(index[n].addr);
   update_cheat_status();
 }
 
 void Cheat::disable(uint32 n) {
-  if(n >= cheat_count)return;
+  if(n >= cheat_count) return;
   index[n].enabled = false;
   clear(index[n].addr);
   update_cheat_status();
@@ -274,16 +275,16 @@ void Cheat::disable(uint32 n) {
 /* ... */
 
 bool Cheat::load(const char *fn) {
-string data;
+  string data;
   if(!fread(data, fn)) return false;
   replace(data, "\r\n", "\n");
   qreplace(data, "=", ",");
   qreplace(data, " ", "");
 
-lstring line;
+  lstring line;
   split(line, "\n", data);
-  for(int i = 0; i < ::count(line); i++) {
-  lstring part;
+  for(unsigned i = 0; i < ::count(line); i++) {
+    lstring part;
     split(part, ",", line[i]);
     if(::count(part) != 3) continue;
     trim(part[2], "\"");
@@ -294,9 +295,9 @@ lstring line;
 }
 
 bool Cheat::save(const char *fn) {
-FILE *fp = fopen(fn, "wb");
+  FILE *fp = fopen(fn, "wb");
   if(!fp) return false;
-  for(int i = 0; i < cheat_count; i++) {
+  for(unsigned i = 0; i < cheat_count; i++) {
     fprintf(fp, "%9s = %8s, \"%s\"\r\n",
       index[i].code,
       index[i].enabled ? "enabled" : "disabled",
@@ -314,7 +315,7 @@ void Cheat::clear() {
   cheat_enabled = false;
   cheat_count = 0;
   memset(mask, 0, 0x200000);
-  for(int i = 0; i <= CHEAT_LIMIT; i++) {
+  for(unsigned i = 0; i <= CheatLimit; i++) {
     index[i].enabled = false;
     index[i].addr = 0x000000;
     index[i].data = 0x00;

src/cheat/cheat.h

@@ -1,51 +1,51 @@
-#define CHEAT_LIMIT 1024
-
 class Cheat {
-public:
-  enum {
-    CT_PRO_ACTION_REPLAY,
-    CT_GAME_GENIE
+public:
+  enum { CheatLimit = 1024 };
+
+  enum Type {
+    ProActionReplay,
+    GameGenie,
   };
 
   struct CheatIndex {
-    bool   enabled;
+    bool enabled;
     uint32 addr;
-    uint8  data;
-    char   code[ 16 + 1];
-    char   desc[128 + 1];
-  } index[CHEAT_LIMIT + 1];
+    uint8 data;
+    char code[ 16 + 1];
+    char desc[128 + 1];
+  } index[CheatLimit + 1];
 
-  bool   cheat_enabled;
+  bool cheat_enabled;
   uint32 cheat_count;
-  uint8  mask[0x200000];
+  uint8 mask[0x200000];
 
   inline bool enabled() { return cheat_enabled; }
   inline uint count() { return cheat_count; }
   inline bool exists(uint32 addr) { return bool(mask[addr >> 3] & 1 << (addr & 7)); }
 
-  bool  decode(char *str, uint32 &addr, uint8 &data, uint8 &type);
-  bool  encode(char *str, uint32  addr, uint8  data, uint8  type);
+  bool decode(char *str, uint32 &addr, uint8 &data, uint8 &type);
+  bool encode(char *str, uint32  addr, uint8  data, uint8  type);
 
-  bool  read(uint32 addr, uint8 &data);
+  bool read(uint32 addr, uint8 &data);
 
-  void  update_cheat_status();
-  bool  add(bool enable, char *code, char *desc);
-  bool  edit(uint32 n, bool enable, char *code, char *desc);
-  bool  get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc);
-  bool  remove (uint32 n);
-  bool  enabled(uint32 n);
-  void  enable (uint32 n);
-  void  disable(uint32 n);
-  bool  load(const char *fn);
-  bool  save(const char *fn);
-  void  clear();
+  void update_cheat_status();
+  bool add(bool enable, char *code, char *desc);
+  bool edit(uint32 n, bool enable, char *code, char *desc);
+  bool get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc);
+  bool remove(uint32 n);
+  bool enabled(uint32 n);
+  void enable(uint32 n);
+  void disable(uint32 n);
+  bool load(const char *fn);
+  bool save(const char *fn);
+  void clear();
 
   Cheat();
 
 private:
-  uint  mirror_address(uint addr);
-  void  set(uint32 addr);
-  void  clear(uint32 addr);
+  uint mirror_address(uint addr);
+  void set(uint32 addr);
+  void clear(uint32 addr);
 };
 
 extern Cheat cheat;

src/chip/bsx/bsx.cpp

@@ -1,4 +1,5 @@
-#include "../../base.h"
+#include "../../base.h"
+#define BSX_CPP
 
 #include "bsx_base.cpp"
 #include "bsx_cart.cpp"

src/chip/bsx/bsx_base.cpp

@@ -1,3 +1,5 @@
+#ifdef BSX_CPP
+
 void BSXBase::init() {
 }
 
@@ -131,3 +133,5 @@ void BSXBase::mmio_write(uint addr, uint8 data) {
     } break;
   }
 }
+
+#endif //ifdef BSX_CPP

src/chip/bsx/bsx_cart.cpp

@@ -1,3 +1,5 @@
+#ifdef BSX_CPP
+
 void BSXCart::init() {
 }
 
@@ -18,7 +20,7 @@ void BSXCart::reset() {
 }
 
 void BSXCart::update_memory_map() {
-Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)psram;
+  Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)psram;
 
   if((regs.r[0x02] & 0x80) == 0x00) { //LoROM mapping
     bus.map(Bus::MapLinear, 0x00, 0x7d, 0x8000, 0xffff, cart);
@@ -57,7 +59,7 @@ Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)psra
 
 uint8 BSXCart::mmio_read(uint addr) {
   if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
-  uint8 n = (addr >> 16) & 15;
+    uint8 n = (addr >> 16) & 15;
     return regs.r[n];
   }
 
@@ -70,7 +72,7 @@ uint8 BSXCart::mmio_read(uint addr) {
 
 void BSXCart::mmio_write(uint addr, uint8 data) {
   if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
-  uint8 n = (addr >> 16) & 15;
+    uint8 n = (addr >> 16) & 15;
     regs.r[n] = data;
     if(n == 0x0e && data & 0x80) update_memory_map();
     return;
@@ -82,14 +84,16 @@ void BSXCart::mmio_write(uint addr, uint8 data) {
 }
 
 BSXCart::BSXCart() {
-  sram_data  = (uint8*)malloc( 32 * 1024);
-  psram_data = (uint8*)malloc(512 * 1024);
+  sram_data  = new uint8_t[ 32 * 1024];
+  psram_data = new uint8_t[512 * 1024];
 
   sram.map (sram_data,   32 * 1024);
   psram.map(psram_data, 512 * 1024);
 }
 
 BSXCart::~BSXCart() {
-  safe_free(sram_data);
-  safe_free(psram_data);
+  delete[] sram_data;
+  delete[] psram_data;
 }
+
+#endif //ifdef BSX_CPP

src/chip/bsx/bsx_flash.cpp

@@ -1,3 +1,5 @@
+#ifdef BSX_CPP
+
 void BSXFlash::init() {}
 void BSXFlash::enable() {}
 
@@ -107,3 +109,5 @@ void BSXFlash::write(uint addr, uint8 data) {
     }
   }
 }
+
+#endif //ifdef BSX_CPP

src/chip/chip.h

@@ -1,6 +1,7 @@
 #include "bsx/bsx.h"
 #include "srtc/srtc.h"
 #include "sdd1/sdd1.h"
+#include "spc7110/spc7110.h"
 #include "cx4/cx4.h"
 #include "dsp1/dsp1.h"
 #include "dsp2/dsp2.h"

src/chip/cx4/cx4.cpp

@@ -5,7 +5,8 @@
   Portions (c) anomie, Overload, zsKnight, Nach, byuu
 */
 
-#include "../../base.h"
+#include "../../base.h"
+#define CX4_CPP
 
 #include "cx4data.cpp"
 #include "cx4fn.cpp"

src/chip/cx4/cx4data.cpp

@@ -1,3 +1,5 @@
+#ifdef CX4_CPP
+
 const uint8 Cx4::immediate_data[48] = {
   0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff,
   0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x80, 0xff, 0xff, 0x7f,
@@ -181,3 +183,5 @@ const int16 Cx4::CosTable[512] = {
    32138,  32214,  32285,  32351,  32413,  32469,  32521,  32568,
    32610,  32647,  32679,  32706,  32728,  32745,  32758,  32765
 };
+
+#endif //ifdef CX4_CPP

src/chip/cx4/cx4fn.cpp

@@ -1,3 +1,5 @@
+#ifdef CX4_CPP
+
 #include <math.h>
 #define Tan(a) (CosTable[a] ? ((((int32)SinTable[a]) << 16) / CosTable[a]) : 0x80000000)
 #define sar(b, n) ((b) >> (n))
@@ -240,3 +242,5 @@ uint8 bit    = 0x80;
     LineY += D;
   }
 }
+
+#endif //ifdef CX4_CPP

src/chip/cx4/cx4oam.cpp

@@ -1,3 +1,5 @@
+#ifdef CX4_CPP
+
 //Build OAM
 void Cx4::op00_00() {
 uint32 oamptr = ram[0x626] << 2;
@@ -217,3 +219,5 @@ uint16 mask2   = 0x3f3f;
     destptr += 16;
   }
 }
+
+#endif //ifdef CX4_CPP

src/chip/cx4/cx4ops.cpp

@@ -1,3 +1,5 @@
+#ifdef CX4_CPP
+
 //Sprite Functions
 void Cx4::op00() {
   switch(reg[0x4d]) {
@@ -220,3 +222,5 @@ void Cx4::op89() {
   str(0, 0x054336);
   str(1, 0xffffff);
 }
+
+#endif //ifdef CX4_CPP

src/chip/dsp1/dsp1.cpp

@@ -1,4 +1,5 @@
-#include "../../base.h"
+#include "../../base.h"
+#define DSP1_CPP
 
 #include "dsp1emu.cpp"
 

src/chip/dsp1/dsp1emu.cpp

@@ -1,3 +1,5 @@
+#ifdef DSP1_CPP
+
 // DSP-1's emulation code
 //
 // Based on research by Overload, The Dumper, Neviksti and Andreas Naive
@@ -1620,3 +1622,4 @@ const int16 Dsp1::SinTable[256] = {
 
 //////////////////////////////////////////////////////////////////
 
+#endif //ifdef DSP1_CPP

src/chip/dsp2/dsp2.cpp

@@ -1,4 +1,5 @@
-#include "../../base.h"
+#include "../../base.h"
+#define DSP2_CPP
 
 #include "dsp2_op.cpp"
 

src/chip/dsp2/dsp2_op.cpp

@@ -1,3 +1,5 @@
+#ifdef DSP2_CPP
+
 //convert bitmap to bitplane tile
 void DSP2::op01() {
 //op01 size is always 32 bytes input and output
@@ -171,3 +173,5 @@ uint8  pixelarray[512];
     status.output[i] = (pixelarray[i << 1] << 4) | pixelarray[(i << 1) + 1];
   }
 }
+
+#endif //ifdef DSP2_CPP

src/chip/dsp3/dsp3.cpp

@@ -1,4 +1,5 @@
-#include "../../base.h"
+#include "../../base.h"
+#define DSP3_CPP
 
 namespace DSP3i {
   #define bool8 uint8

src/chip/dsp3/dsp3emu.c

@@ -1,3 +1,5 @@
+#ifdef DSP3_CPP
+
 //DSP-3 emulator code
 //Copyright (c) 2003-2006 John Weidman, Kris Bleakley, Lancer, z80 gaiden
 
@@ -1140,3 +1142,5 @@ void InitDSP3()
 {
   DSP3_Reset();
 }
+
+#endif //ifdef DSP3_CPP

src/chip/dsp4/dsp4.cpp

@@ -1,4 +1,5 @@
-#include "../../base.h"
+#include "../../base.h"
+#define DSP4_CPP
 
 namespace DSP4i {
   inline uint16 READ_WORD(uint8 *addr) {

src/chip/dsp4/dsp4emu.c

@@ -1,3 +1,5 @@
+#ifdef DSP4_CPP
+
 //DSP-4 emulator code
 //Copyright (c) 2004-2006 Dreamer Nom, John Weidman, Kris Bleakley, Nach, z80 gaiden
 
@@ -2144,3 +2146,5 @@ void DSP4GetByte()
     dsp4_byte = 0xff;
   }
 }
+
+#endif //ifdef DSP4_CPP

src/chip/sdd1/sdd1.cpp

@@ -1,4 +1,5 @@
-#include "../../base.h"
+#include "../../base.h"
+#define SDD1_CPP
 
 #include "sdd1emu.cpp"
 

src/chip/sdd1/sdd1emu.cpp

@@ -1,3 +1,5 @@
+#ifdef SDD1_CPP
+
 /************************************************************************
 
 S-DD1'algorithm emulation code
@@ -445,3 +447,5 @@ SDD1emu::SDD1emu() :
 }
 
 ///////////////////////////////////////////////////////////
+
+#endif //ifdef SDD1_CPP

src/chip/spc7110/codec.cpp

@@ -0,0 +1,697 @@
+const uint8_t SPC7110Codec::EvolutionTable[53][4] = {
+	//prob, nextlps, nextmps, toggle invert
+	{0x5a,  1,  1,1}, //0  l,m 
+	{0x25,  6,  2,0}, //1  l,m 
+	{0x11,  8,  3,0}, //2  l,m 
+	{0x08, 10,  4,0}, //3   ,m 
+	{0x03, 12,  5,0}, //4   ,m 
+	{0x01, 15,  5,0}, //5   ,m 
+
+	{0x5a,  7,  7,1}, //6  l, 
+	{0x3f, 19,  8,0}, //7  l,m 
+	{0x2c, 21,  9,0}, //8  l,m 
+	{0x20, 22, 10,0}, //9   ,m 
+	{0x17, 23, 11,0}, //10  ,m 
+	{0x11, 25, 12,0}, //11  ,m 
+	{0x0c, 26, 13,0}, //12  ,m 
+	{0x09, 28, 14,0}, //13  ,m 
+	{0x07, 29, 15,0}, //14  ,m 
+	{0x05, 31, 16,0}, //15  ,m 
+	{0x04, 32, 17,0}, //16  ,m 
+	{0x03, 34, 18,0}, //17  ,m 
+	{0x02, 35, 5,0},  //18  ,m 
+
+	{0x5a, 20, 20,1}, //19 l,m 
+	{0x48, 39, 21,0}, //20 l,m 
+	{0x3a, 40, 22,0}, //21 l,m 
+	{0x2e, 42, 23,0}, //22 l,m 
+	{0x26, 44, 24,0}, //23 l,m 
+	{0x1f, 45, 25,0}, //24 l,m 
+	{0x19, 46, 26,0}, //25 l,m 
+	{0x15, 25, 27,0}, //26 l,m 
+	{0x11, 26, 28,0}, //27 l,m 
+	{0x0e, 26, 29,0}, //28 l,m 
+	{0x0b, 27, 30,0}, //29  ,m 
+	{0x09, 28, 31,0}, //30  ,m 
+	{0x08, 29, 32,0}, //31 l,m 
+	{0x07, 30, 33,0}, //32 l,m 
+	{0x05, 31, 34,0}, //33 l,m  <--- changed lps 
+	{0x04, 33, 35,0}, //34  ,m ... this is NOT skipped 
+	{0x04, 33, 36,0}, //35  ,m 
+	{0x03, 34, 37,0}, //36  ,m 
+	{0x02, 35, 38,0}, //37  ,m ... this is NOT skipped 
+	{0x02, 36,  5,0}, //38  ,m 
+
+	{0x58, 39, 40,1}, //39 l,m 
+	{0x4d, 47, 41,0}, //40 l,m 
+	{0x43, 48, 42,0}, //41  ,m 
+	{0x3b, 49, 43,0}, //42  ,m 
+	{0x34, 50, 44,0}, //43 l,m 
+	{0x2e, 51, 45,0}, //44 l,m 
+	{0x29, 44, 46,0}, //45 l,m 
+	{0x25, 45, 24,0}, //46  ,m 
+
+	{0x56, 47, 48,1}, //47 l,m 
+	{0x4f, 47, 49,0}, //48 l,m 
+	{0x47, 48, 50,0}, //49 l,m 
+	{0x41, 49, 51,0}, //50 l,m 
+	{0x3c, 50, 52,0}, //51 l,m 
+	{0x37, 51, 43,0}  //52  ,m 
+};
+
+const uint8_t SPC7110Codec::Mode2ContextTable[32][4] = {
+	// "bit" = (lps^invert)
+	//next_0, use ref pixel, next_1, use ref pixel
+	// if use ref pixel, then add on the 0-4 bell number grouping
+	{1, 0, 2, 0}, //0
+
+	{3, 1, 8, 1}, //1  prev bit 0
+	{13,0, 14,0}, //2  prev bit 1
+
+	{15,0, 16,0}, //3  prev bit 00
+	{17,0, 18,0}, //4
+	{19,0, 20,0}, //5
+	{21,0, 22,0}, //6
+	{23,0, 24,0}, //7
+	{25,0, 26,0}, //8  prev bit 01
+	{25,0, 26,0}, //9
+	{25,0, 26,0}, //10
+	{25,0, 26,0}, //11
+	{25,0, 26,0}, //12
+	{27,0, 28,0}, //13 prev bit 10
+	{29,0, 30,0}, //14 prev bit 11
+
+	{31,0, 31,0}, //15  000 ref group 0
+	{31,0, 31,0}, //16  001 ref group 0
+	{31,0, 31,0}, //17  000 ref group 1
+	{31,0, 31,0}, //18  001 ref group 1
+	{31,0, 31,0}, //19  000 ref group 2
+	{31,0, 31,0}, //20  001 ref group 2
+	{31,0, 31,0}, //21  000 ref group 3
+	{31,0, 31,0}, //22  001 ref group 3
+	{31,0, 31,0}, //23  000 ref group 4
+	{31,0, 31,0}, //24  001 ref group 4
+	{31,0, 31,0}, //25  010
+	{31,0, 31,0}, //26  011
+	{31,0, 31,0}, //27  100
+	{31,0, 31,0}, //28  101
+	{31,0, 31,0}, //29  110
+	{31,0, 31,0}, //30  111
+
+	{31,0, 31,0} //31 -- used as a trap for testing purposes --
+};
+
+#define PROB(x) EvolutionTable[Contexts[x].index][0]
+#define NEXT_LPS(x) EvolutionTable[Contexts[x].index][1]
+#define NEXT_MPS(x) EvolutionTable[Contexts[x].index][2]
+#define TOGGLE_INVERT(x) EvolutionTable[Contexts[x].index][3]
+#define BIT(x,y) ((x>>y)&1)
+
+void SPC7110Codec::decomp_mode0(int len) {
+    uint8_t *datain  = buffer;
+    uint8_t *dataout = output;
+    static const unsigned NUM_CONTEXTS = 30;
+
+	uint8 top,val;
+	uint8 con,mps,prob;
+	uint8 flag_lps,shift,mask;
+
+	int out=0;
+	int inverts=0;
+	int lps=0;
+
+	unsigned char in;
+	int in_count;
+
+	int i,bit;
+
+	//setup 
+	top=0xFF;
+
+	val=*datain;
+	datain++;
+
+	in=*datain;
+	datain++;
+	in_count=8;
+
+	//reset context states
+	for(i=0;i<NUM_CONTEXTS;i++)
+	{
+		Contexts[i].index=0;
+		Contexts[i].invert=0;
+	}
+
+	for(i=0;i<len;i++)
+	{
+		if(i==-1800)
+		{
+			int k;
+			printf("\nEvolution table:\n");
+			//for(k=0;k<53;k++)
+				//printf("  %d,%d //%d\n",SeenEvolution[k][0],SeenEvolution[k][1],k);
+		}
+
+		
+		for(bit=0;bit<8;bit++)
+		{
+			//get context
+			mask = (1<<(bit&3)) - 1;
+			con = mask + ((inverts&mask)^(lps&mask));
+			if(bit>3)
+				con+=15;
+			
+			//get PROB and MPS
+			prob = PROB(con);
+			mps  = (BIT(out,15) ^ Contexts[con].invert);
+
+			if(i>=15 && i<=18 && 0)
+				printf("byte %d bit %d: val=%.2X top=%.2X prob=%.2X mps=%d   con=%d state=%d\n",
+					i,bit,val,top,prob,mps,con,Contexts[con].index); 
+
+			//get bit
+			if (val <= top-prob)
+			{
+				//mps
+				top = top - prob;
+				out = (out << 1) + mps;
+
+				flag_lps=0;
+			}
+			else
+			{
+				//lps
+				val = val - (top - (prob - 1));
+				top = prob - 1; 
+				out = (out << 1) + 1-mps;
+			
+				flag_lps=1;
+			}
+
+			// renormalize
+			shift=0;
+			while(top<0x7F) // NOTE: not 0x80, it's a strange border case 
+			{
+				shift++;
+
+				top = (top<<1)+1;
+				val = (val<<1)+(in>>7);
+
+				in = (in<<1);
+				if(--in_count==0)
+				{
+					in=*datain;
+					datain++;
+					in_count=8;
+				}
+			}
+
+			//update processing info
+			lps = (lps<<1) + flag_lps;
+			inverts  = (inverts<<1) + Contexts[con].invert;
+
+			//update context state
+			if(flag_lps & TOGGLE_INVERT(con))
+				Contexts[con].invert ^= 1;
+
+			if(flag_lps)
+			{
+				//SeenEvolution[Contexts[con].index][0]=1;
+				Contexts[con].index = NEXT_LPS(con);
+			}
+			else if(shift)
+			{
+				//SeenEvolution[Contexts[con].index][1]=1;
+				Contexts[con].index = NEXT_MPS(con);
+			}
+		}
+
+		//save byte
+		*dataout = (out & 0xFF);
+		dataout++;
+	}
+}
+
+void SPC7110Codec::decomp_mode1(int len) {
+    uint8_t *datain  = buffer;
+    uint8_t *dataout = output;
+    static const unsigned NUM_CONTEXTS = 15;
+
+	int pixelorder[4]={0,1,2,3};
+	int realorder[4];
+	int a,b,c;
+	int m,n;
+
+	uint8 top,val;
+	uint8 con,prob;
+	uint8 flag_lps,shift;
+
+	int out=0;
+	int inverts=0;
+	int lps=0;
+
+	unsigned char in;
+	int in_count;
+	int in_len=0;
+
+	int i,j,pixel;
+
+	//setup 
+	top=0xFF;
+
+	val=datain[in_len++];
+
+	in=datain[in_len++];
+	in_count=8;
+
+	//reset context states
+	for(i=0;i<NUM_CONTEXTS;i++)
+	{
+		Contexts[i].index=0;
+		Contexts[i].invert=0;
+	}
+
+	for(i=0;i<len;i+=2)
+	{
+		if(i!=0)
+		{
+			//turn pixel data into bitplanes
+			//and save as output
+			*dataout = (BIT(out,15)<<7) + (BIT(out,13)<<6) + (BIT(out,11)<<5) + (BIT(out,9)<<4)
+					+ (BIT(out,7)<<3) + (BIT(out,5)<<2) + (BIT(out,3)<<1) + BIT(out,1);
+			dataout++;
+			*dataout = (BIT(out,14)<<7) + (BIT(out,12)<<6) + (BIT(out,10)<<5) + (BIT(out,8)<<4)
+					+ (BIT(out,6)<<3) + (BIT(out,4)<<2) + (BIT(out,2)<<1) + BIT(out,0);
+			dataout++;
+		}
+		
+		for(pixel=0;pixel<8;pixel++)
+		{
+			//get first symbol context
+			a = ((out >> (1*2)) & 0x3);
+			b = ((out >> (7*2)) & 0x3);
+			c = ((out >> (8*2)) & 0x3);
+			if(a==b && b==c)
+				con=0;
+			else if (a==b && b!=c)
+				con=1;
+			else if (a!=b && b==c)
+				con=2;
+			else if (a==c && b!=c)
+				con=3;
+			else
+				con=4;
+
+			//update pixel order
+			for(m=0;m<4;m++)
+				if(pixelorder[m]==a)
+					break;
+			for(n=m;n>0;n--)
+			{
+				j=pixelorder[n-1];
+				pixelorder[n-1]=pixelorder[n];
+				pixelorder[n]=j;
+			}
+
+
+			//get PROB
+			prob = PROB(con);
+
+			//get symbol
+			if (val <= top-prob)
+			{
+				//mps
+				top = top - prob;
+				flag_lps=0;
+			}
+			else
+			{
+				//lps
+				val = val - (top - (prob - 1));
+				top = prob - 1; 
+				flag_lps=1;
+			}
+
+			// renormalize
+			shift=0;
+			while(top<0x7F)
+			{
+				shift++;
+
+				top = (top<<1)+1;
+				val = (val<<1)+(in>>7);
+
+				in = (in<<1);
+				if(--in_count==0)
+				{
+					in=datain[in_len++];
+					in_count=8;
+				}
+			}
+
+			//update processing info
+			lps = (lps<<1) + flag_lps;
+			inverts  = (inverts<<1) + Contexts[con].invert;
+
+			//update context state
+			if(flag_lps & TOGGLE_INVERT(con))
+				Contexts[con].invert ^= 1;
+			if(flag_lps)
+				Contexts[con].index = NEXT_LPS(con);
+			else if(shift)
+				Contexts[con].index = NEXT_MPS(con);
+
+			//get context of second symbol
+			con = 5 + con*2 + ((lps^inverts)&1);
+
+			//get PROB
+			prob = PROB(con);
+
+			//get symbol
+			if (val <= top-prob)
+			{
+				//mps
+				top = top - prob;
+				flag_lps=0;
+			}
+			else
+			{
+				//lps
+				val = val - (top - (prob - 1));
+				top = prob - 1; 
+				flag_lps=1;
+			}
+
+			// renormalize
+			shift=0;
+			while(top<0x7F)
+			{
+				shift++;
+
+				top = (top<<1)+1;
+				val = (val<<1)+(in>>7);
+
+				in = (in<<1);
+				if(--in_count==0)
+				{
+					in=datain[in_len++];
+					in_count=8;
+				}
+			}
+
+			//calculate the real pixel order
+			for(m=0;m<4;m++)
+				realorder[m]=pixelorder[m];
+			//shift refence pixel c value to top
+			for(m=0;m<4;m++)
+				if(realorder[m]==c)
+					break;
+			for(n=m;n>0;n--)
+			{
+				j=realorder[n-1];
+				realorder[n-1]=realorder[n];
+				realorder[n]=j;
+			}
+			//shift refence pixel b value to top
+			for(m=0;m<4;m++)
+				if(realorder[m]==b)
+					break;
+			for(n=m;n>0;n--)
+			{
+				j=realorder[n-1];
+				realorder[n-1]=realorder[n];
+				realorder[n]=j;
+			}
+			//shift refence pixel a value to top
+			for(m=0;m<4;m++)
+				if(realorder[m]==a)
+					break;
+			for(n=m;n>0;n--)
+			{
+				j=realorder[n-1];
+				realorder[n-1]=realorder[n];
+				realorder[n]=j;
+			}
+
+			
+			//update processing info
+			lps = (lps<<1) + flag_lps;
+			inverts  = (inverts<<1) + Contexts[con].invert;
+
+			//update context state
+			if(flag_lps & TOGGLE_INVERT(con))
+				Contexts[con].invert ^= 1;
+			if(flag_lps)
+				Contexts[con].index = NEXT_LPS(con);
+			else if(shift)
+				Contexts[con].index = NEXT_MPS(con);
+
+			//get pixel
+			b=realorder[(lps^inverts)&3];
+			out = (out<<2) + b;
+		}
+	}
+
+	//turn pixel data into bitplanes
+	//and save as output.. BUT don't save second byte unless asked to
+	*dataout = (BIT(out,15)<<7) + (BIT(out,13)<<6) + (BIT(out,11)<<5) + (BIT(out,9)<<4)
+			+ (BIT(out,7)<<3) + (BIT(out,5)<<2) + (BIT(out,3)<<1) + BIT(out,1);
+	dataout++;
+	if((len&1)==0)
+	{
+		*dataout = (BIT(out,14)<<7) + (BIT(out,12)<<6) + (BIT(out,10)<<5) + (BIT(out,8)<<4)
+				+ (BIT(out,6)<<3) + (BIT(out,4)<<2) + (BIT(out,2)<<1) + BIT(out,0);
+		dataout++;
+	}
+
+	if(in_count==8)
+		in_len--;
+	//printf("Used %d bytes of input.\n",in_len);
+	//return in_len;
+}
+
+void SPC7110Codec::decomp_mode2(int len) {
+    uint8_t *datain  = buffer;
+    uint8_t *dataout = output;
+    static const unsigned NUM_CONTEXTS = 32;
+
+	int pixelorder[16]={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
+	int realorder[16];
+	int a,b,c;
+	int m,n;
+
+	uint8 bitplanebuffer[16];
+	uint8 buf_idx=0;
+
+	uint8 top,val,prob;
+	uint8 con,refcon;
+	uint8 flag_lps,invertbit,shift;
+
+	int out=0;
+	int out2=0;
+	int inverts=0;
+	int lps=0;
+
+	unsigned char in;
+	int in_count;
+	int in_len=0;
+
+	int i,j,pixel,bit;
+
+	//setup 
+	top=0xFF;
+
+	val=datain[in_len++];
+
+	in=datain[in_len++];
+	in_count=8;
+
+	//reset context states
+	for(i=0;i<NUM_CONTEXTS;i++)
+	{
+		Contexts[i].index=0;
+		Contexts[i].invert=0;
+	}
+
+	for(i=0;i<len;i+=2)
+	{
+		for(pixel=0;pixel<8;pixel++)
+		{
+			//get first symbol context
+			a = ((out >> (0*4)) & 0x0F);
+			b = ((out >> (7*4)) & 0x0F);
+			c = ((out2>> (0*4)) & 0x0F);
+			if(a==b && b==c)
+				refcon=0;
+			else if (a==b && b!=c)
+				refcon=1;
+			else if (a!=b && b==c)
+				refcon=2;
+			else if (a==c && b!=c)
+				refcon=3;
+			else
+				refcon=4;
+
+			con=0;
+
+			//update pixel order
+			for(m=0;m<16;m++)
+				if(pixelorder[m]==a)
+					break;
+			for(n=m;n>0;n--)
+			{
+				j=pixelorder[n-1];
+				pixelorder[n-1]=pixelorder[n];
+				pixelorder[n]=j;
+			}
+
+			//calculate the real pixel order
+			for(m=0;m<16;m++)
+				realorder[m]=pixelorder[m];
+			//shift refence pixel c value to top
+			for(m=0;m<16;m++)
+				if(realorder[m]==c)
+					break;
+			for(n=m;n>0;n--)
+			{
+				j=realorder[n-1];
+				realorder[n-1]=realorder[n];
+				realorder[n]=j;
+			}
+			//shift refence pixel b value to top
+			for(m=0;m<16;m++)
+				if(realorder[m]==b)
+					break;
+			for(n=m;n>0;n--)
+			{
+				j=realorder[n-1];
+				realorder[n-1]=realorder[n];
+				realorder[n]=j;
+			}
+			//shift refence pixel a value to top
+			for(m=0;m<16;m++)
+				if(realorder[m]==a)
+					break;
+			for(n=m;n>0;n--)
+			{
+				j=realorder[n-1];
+				realorder[n-1]=realorder[n];
+				realorder[n]=j;
+			}
+
+			//get 4 symbols
+			for(bit=0;bit<4;bit++)
+			{
+				//get PROB
+				prob = PROB(con);
+
+				//get symbol
+				if (val <= top-prob)
+				{
+					//mps
+					top = top - prob;
+					flag_lps=0;
+				}
+				else
+				{
+					//lps
+					val = val - (top - (prob - 1));
+					top = prob - 1; 
+					flag_lps=1;
+				}
+
+				// renormalize
+				shift=0;
+				while(top<0x7F)
+				{
+					shift++;
+	
+					top = (top<<1)+1;
+					val = (val<<1)+(in>>7);
+
+					in = (in<<1);
+					if(--in_count==0)
+					{
+						in=datain[in_len++];
+						in_count=8;
+					}
+				}
+
+				//update processing info
+				lps = (lps<<1) + flag_lps;
+				invertbit = Contexts[con].invert;
+				inverts  = (inverts<<1) + Contexts[con].invert;
+
+				//update context state
+				if(flag_lps & TOGGLE_INVERT(con))
+					Contexts[con].invert ^= 1;
+				if(flag_lps)
+					Contexts[con].index = NEXT_LPS(con);
+				else if(shift)
+					Contexts[con].index = NEXT_MPS(con);
+
+				//get next context
+				if(Mode2ContextTable[con][2*(flag_lps^invertbit)+1])
+					con=Mode2ContextTable[con][2*(flag_lps^invertbit)]+refcon;		
+				else
+					con=Mode2ContextTable[con][2*(flag_lps^invertbit)];		
+			}
+
+			//get pixel
+			b=realorder[(lps^inverts)&0x0F];
+			out2 = (out2<<4) + ((out>>28)&0x0F);
+			out = (out<<4) + b;
+		}
+
+		//cludge to convert pixel data into bitplanes and respect len parameter for output buf
+		*dataout = (BIT(out,31)<<7) + (BIT(out,27)<<6) + (BIT(out,23)<<5) + (BIT(out,19)<<4)
+				+ (BIT(out,15)<<3) + (BIT(out,11)<<2) + (BIT(out,7)<<1) + BIT(out,3);
+		dataout++;
+
+		if((i+1)<len)
+		{
+			*dataout = (BIT(out,30)<<7) + (BIT(out,26)<<6) + (BIT(out,22)<<5) + (BIT(out,18)<<4)
+				+ (BIT(out,14)<<3) + (BIT(out,10)<<2) + (BIT(out,6)<<1) + BIT(out,2);
+			dataout++;
+		}
+
+		bitplanebuffer[buf_idx++] =
+				(BIT(out,29)<<7) + (BIT(out,25)<<6) + (BIT(out,21)<<5) + (BIT(out,17)<<4)
+				+ (BIT(out,13)<<3) + (BIT(out,9)<<2) + (BIT(out,5)<<1) + BIT(out,1);
+		bitplanebuffer[buf_idx++] =
+				(BIT(out,28)<<7) + (BIT(out,24)<<6) + (BIT(out,20)<<5) + (BIT(out,16)<<4)
+				+ (BIT(out,12)<<3) + (BIT(out,8)<<2) + (BIT(out,4)<<1) + BIT(out,0);
+
+		if(buf_idx==16)
+		{
+			for(m=0;m<16 && i+2<len;m++,i++)
+			{
+				*dataout = bitplanebuffer[m];
+				dataout++;
+			}
+
+			buf_idx=0;
+		}
+	}
+
+	if(in_count==8)
+		in_len--;
+	//printf("Used %d bytes of input.\n",in_len);
+	//return in_len;
+}
+
+#undef PROB
+#undef NEXT_LPS
+#undef NEXT_MPS
+#undef TOGGLE_INVERT
+#undef BIT
+
+SPC7110Codec::SPC7110Codec() {
+  buffer = new(zeromemory) uint8_t[65536];
+  output = new(zeromemory) uint8_t[65536];
+}
+
+SPC7110Codec::~SPC7110Codec() {
+  delete[] buffer;
+  delete[] output;
+}

src/chip/spc7110/codec.h

@@ -0,0 +1,20 @@
+class SPC7110Codec {
+public:
+  uint8_t *buffer;
+  uint8_t *output;
+
+  void decomp_mode0(int len);
+  void decomp_mode1(int len);
+  void decomp_mode2(int len);
+
+  SPC7110Codec();
+  ~SPC7110Codec();
+
+private:
+  static const uint8_t EvolutionTable[53][4];
+  static const uint8_t Mode2ContextTable[32][4];
+  struct ContextState {
+    uint8_t index;
+    uint8_t invert;
+  } Contexts[32];
+};

src/chip/spc7110/spc7110.cpp

@@ -0,0 +1,690 @@
+#include "../../base.h"
+#define SPC7110_CPP
+
+#include "codec.cpp"
+
+const unsigned SPC7110::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+void SPC7110::init() {}
+
+void SPC7110::enable() {
+  uint16_t limit = (cartridge.info.spc7110rtc ? 0x4842 : 0x483f);
+  for(uint16_t i = 0x4800; i <= limit; i++) memory::mmio.map(i, *this);
+}
+
+void SPC7110::power() {
+  reset();
+}
+
+void SPC7110::reset() {
+  r4801 = 0x00;
+  r4802 = 0x00;
+  r4803 = 0x00;
+  r4804 = 0x00;
+  r4805 = 0x00;
+  r4806 = 0x00;
+  r4807 = 0x00;
+  r4808 = 0x00;
+  r4809 = 0x00;
+  r480a = 0x00;
+  r480b = 0x00;
+  r480c = 0x00;
+
+  memset(codec.output, 0, 65536);
+  memset(codec.buffer, 0, 65536);
+  decomp_offset = 0;
+
+  r4811 = 0x00;
+  r4812 = 0x00;
+  r4813 = 0x00;
+  r4814 = 0x00;
+  r4815 = 0x00;
+  r4816 = 0x00;
+  r4817 = 0x00;
+  r4818 = 0x00;
+
+  r481x = 0x00;
+  r4814_latch = false;
+  r4815_latch = false;
+
+  r4820 = 0x00;
+  r4821 = 0x00;
+  r4822 = 0x00;
+  r4823 = 0x00;
+  r4824 = 0x00;
+  r4825 = 0x00;
+  r4826 = 0x00;
+  r4827 = 0x00;
+  r4828 = 0x00;
+  r4829 = 0x00;
+  r482a = 0x00;
+  r482b = 0x00;
+  r482c = 0x00;
+  r482d = 0x00;
+  r482e = 0x00;
+  r482f = 0x00;
+
+  r4830 = 0x00;
+  mmio_write(0x4831, 0);
+  mmio_write(0x4832, 1);
+  mmio_write(0x4833, 2);
+  r4834 = 0x00;
+
+  r4840 = 0x00;
+  r4841 = 0x00;
+  r4842 = 0x00;
+
+  if(cartridge.info.spc7110rtc) {
+    rtc_state = RTCS_Inactive;
+    rtc_mode  = RTCM_Linear;
+    rtc_index = 0;
+  }
+}
+
+unsigned SPC7110::datarom_addr(unsigned addr) {
+  unsigned size = memory::cartrom.size() - 0x100000;
+  while(addr >= size) addr -= size;
+  return addr + 0x100000;
+}
+
+unsigned SPC7110::data_pointer()   { return r4811 + (r4812 << 8) + (r4813 << 16); }
+unsigned SPC7110::data_adjust()    { return r4814 + (r4815 << 8); }
+unsigned SPC7110::data_increment() { return r4816 + (r4817 << 8); }
+void SPC7110::set_data_pointer(unsigned addr) { r4811 = addr; r4812 = addr >> 8; r4813 = addr >> 16; }
+void SPC7110::set_data_adjust(unsigned addr)  { r4814 = addr; r4815 = addr >> 8; }
+
+void SPC7110::update_time(int offset) {
+  time_t rtc_time;
+  rtc_time  = memory::cartrtc.read(16);
+  rtc_time |= memory::cartrtc.read(17) << 8;
+  rtc_time |= memory::cartrtc.read(18) << 16;
+  rtc_time |= memory::cartrtc.read(19) << 24;
+
+  bool update = true;
+  if(memory::cartrtc.read(13) & 1) update = false; //do not update if CR0 timer disable flag is set
+  if(memory::cartrtc.read(15) & 3) update = false; //do not update if CR2 timer disable flags are set
+
+  time_t current_time = time(0) - offset;
+  if(update && current_time > rtc_time) {
+    unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
+    unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
+    unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
+    unsigned day     = memory::cartrtc.read( 6) + memory::cartrtc.read( 7) * 10;
+    unsigned month   = memory::cartrtc.read( 8) + memory::cartrtc.read( 9) * 10;
+    unsigned year    = memory::cartrtc.read(10) + memory::cartrtc.read(11) * 10;
+    unsigned weekday = memory::cartrtc.read(12);
+
+    day--;
+    month--;
+    year += (year >= 90) ? 1900 : 2000; //range = 1990-2089
+
+    second += (unsigned)(current_time - rtc_time);
+    while(second >= 60) {
+      second -= 60;
+
+      minute++;
+      if(minute < 60) continue;
+      minute = 0;
+
+      hour++;
+      if(hour < 24) continue;
+      hour = 0;
+
+      day++;
+      weekday = (weekday + 1) % 7;
+      unsigned days = months[month % 12];
+      if(days == 28) {
+        bool leapyear = false;
+        if((year % 4) == 0) {
+          leapyear = true;
+          if((year % 100) == 0 && (year % 400) != 0) leapyear = false;
+        }
+        if(leapyear) days++;
+      }
+      if(day < days) continue;
+      day = 0;
+
+      month++;
+      if(month < 12) continue;
+      month = 0;
+
+      year++;
+    }
+
+    day++;
+    month++;
+    year %= 100;
+
+    memory::cartrtc.write( 0, second % 10);
+    memory::cartrtc.write( 1, second / 10);
+    memory::cartrtc.write( 2, minute % 10);
+    memory::cartrtc.write( 3, minute / 10);
+    memory::cartrtc.write( 4, hour % 10);
+    memory::cartrtc.write( 5, hour / 10);
+    memory::cartrtc.write( 6, day % 10);
+    memory::cartrtc.write( 7, day / 10);
+    memory::cartrtc.write( 8, month % 10);
+    memory::cartrtc.write( 9, month / 10);
+    memory::cartrtc.write(10, year % 10);
+    memory::cartrtc.write(11, (year / 10) % 10);
+    memory::cartrtc.write(12, weekday % 7);
+  }
+
+  memory::cartrtc.write(16, current_time);
+  memory::cartrtc.write(17, current_time >> 8);
+  memory::cartrtc.write(18, current_time >> 16);
+  memory::cartrtc.write(19, current_time >> 24);
+}
+
+uint8 SPC7110::mmio_read(uint addr) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    //==================
+    //decompression unit
+    //==================
+
+    case 0x4800: {
+      uint16 counter = (r4809 + (r480a << 8));
+      counter--;
+      r4809 = counter;
+      r480a = counter >> 8;
+      return codec.output[(decomp_offset++) & 0xffff];
+    }
+    case 0x4801: return r4801;
+    case 0x4802: return r4802;
+    case 0x4803: return r4803;
+    case 0x4804: return r4804;
+    case 0x4805: return r4805;
+    case 0x4806: return r4806;
+    case 0x4807: return r4807;
+    case 0x4808: return r4808;
+    case 0x4809: return r4809;
+    case 0x480a: return r480a;
+    case 0x480b: return r480b;
+    case 0x480c: {
+      uint8 status = r480c;
+      r480c &= 0x7f;
+      return status;
+    }
+
+    //==============
+    //data port unit
+    //==============
+
+    case 0x4810: {
+      if(r481x != 0x1f) return 0x00;
+
+      unsigned addr = data_pointer();
+      unsigned adjust = data_adjust();
+      if(r4818 & 8) adjust = (int16)adjust; //16-bit sign extend
+
+      unsigned adjustaddr = addr;
+      if(r4818 & 2) {
+        adjustaddr += adjust;
+        set_data_adjust(adjust + 1);
+      }
+
+      uint8 data = memory::cartrom.read(datarom_addr(adjustaddr));
+      if(!(r4818 & 2)) {
+        unsigned increment = (r4818 & 1) ? data_increment() : 1;
+        if(r4818 & 4) increment = (int16)increment; //16-bit sign extend
+
+        if((r4818 & 16) == 0) {
+          set_data_pointer(addr + increment);
+        } else {
+          set_data_adjust(adjust + increment);
+        }
+      }
+
+      return data;
+    }
+    case 0x4811: return r4811;
+    case 0x4812: return r4812;
+    case 0x4813: return r4813;
+    case 0x4814: return r4814;
+    case 0x4815: return r4815;
+    case 0x4816: return r4816;
+    case 0x4817: return r4817;
+    case 0x4818: return r4818;
+    case 0x481a: {
+      if(r481x != 0x1f) return 0x00;
+
+      unsigned addr = data_pointer();
+      unsigned adjust = data_adjust();
+      if(r4818 & 8) adjust = (int16)adjust; //16-bit sign extend
+
+      uint8 data = memory::cartrom.read(datarom_addr(addr + adjust));
+      if((r4818 & 0x60) == 0x60) {
+        if((r4818 & 16) == 0) {
+          set_data_pointer(addr + adjust);
+        } else {
+          set_data_adjust(adjust + adjust);
+        }
+      }
+
+      return data;
+    }
+
+    //=========
+    //math unit
+    //=========
+
+    case 0x4820: return r4820;
+    case 0x4821: return r4821;
+    case 0x4822: return r4822;
+    case 0x4823: return r4823;
+    case 0x4824: return r4824;
+    case 0x4825: return r4825;
+    case 0x4826: return r4826;
+    case 0x4827: return r4827;
+    case 0x4828: return r4828;
+    case 0x4829: return r4829;
+    case 0x482a: return r482a;
+    case 0x482b: return r482b;
+    case 0x482c: return r482c;
+    case 0x482d: return r482d;
+    case 0x482e: return r482e;
+    case 0x482f: {
+      uint8 status = r482f;
+      r482f &= 0x7f;
+      return status;
+    }
+
+    //===================
+    //memory mapping unit
+    //===================
+
+    case 0x4830: return r4830;
+    case 0x4831: return r4831;
+    case 0x4832: return r4832;
+    case 0x4833: return r4833;
+    case 0x4834: return r4834;
+
+    //====================
+    //real-time clock unit
+    //====================
+
+    case 0x4840: return r4840;
+    case 0x4841: {
+      if(rtc_state == RTCS_Inactive || rtc_state == RTCS_ModeSelect) return 0x00;
+
+      r4842 = 0x80;
+      uint8 data = memory::cartrtc.read(rtc_index);
+      rtc_index = (rtc_index + 1) & 15;
+      return data;
+    }
+    case 0x4842: {
+      uint8 status = r4842;
+      r4842 &= 0x7f;
+      return status;
+    }
+  }
+
+  return cpu.regs.mdr;
+}
+
+void SPC7110::mmio_write(uint addr, uint8 data) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    //==================
+    //decompression unit
+    //==================
+
+    case 0x4801: r4801 = data; break;
+    case 0x4802: r4802 = data; break;
+    case 0x4803: r4803 = data; break;
+    case 0x4804: r4804 = data; break;
+    case 0x4805: r4805 = data; break;
+    case 0x4806: {
+      r4806 = data;
+
+      unsigned table   = (r4801 + (r4802 << 8) + (r4803 << 16));
+      unsigned index   = (r4804 << 2);
+      unsigned length  = (r4809 + (r480a << 8));
+      unsigned addr    = datarom_addr(table + index);
+      unsigned mode    = (memory::cartrom.read(addr + 0));
+      unsigned offset  = (memory::cartrom.read(addr + 1) << 16)
+                       + (memory::cartrom.read(addr + 2) <<  8)
+                       + (memory::cartrom.read(addr + 3) <<  0);
+
+      //this can technically be 65536, but it has never been observed higher than 32768 ...
+      //really need a way to determine both compressed and decompressed lengths, though.
+      static const unsigned max_length = 32768;
+
+      offset = datarom_addr(offset);
+      for(unsigned i = 0; i < max_length; i++) codec.buffer[i] = memory::cartrom.read(offset + i);
+
+      #if 0
+      printf("decompression: 4805=$%0.2x,4806=$%0.2x,4807=$%0.2x,4808=$%0.2x,480b=$%0.2x\n",
+        r4805, r4806, r4807, r4808, r480b);
+      printf("table=$%0.6x,index=%3d,length=%5d,mode=%d,offset=$%0.6x\n",
+        table, r4804, length, mode, offset);
+      #endif
+
+      switch(mode) {
+        case 0: codec.decomp_mode0(max_length); break;
+        case 1: codec.decomp_mode1(max_length); break;
+        case 2: codec.decomp_mode2(max_length); break;
+      }
+
+      decomp_offset = (r4805 + (r4806 << 8)) << mode;
+      r480c = 0x80;
+    } break;
+
+    case 0x4807: r4807 = data; break;
+    case 0x4808: r4808 = data; break;
+    case 0x4809: r4809 = data; break;
+    case 0x480a: r480a = data; break;
+    case 0x480b: r480b = data; break;
+
+    //==============
+    //data port unit
+    //==============
+
+    case 0x4811: r4811 = data; r481x |= 0x01; break;
+    case 0x4812: r4812 = data; r481x |= 0x02; break;
+    case 0x4813: r4813 = data; r481x |= 0x04; break;
+    case 0x4814: {
+      r4814 = data;
+      r481x |= 0x08;
+      r4814_latch = true;
+      if(!r4815_latch) break;
+      if(!(r4818 & 2)) break;
+      if(r4818 & 0x10) break;
+
+      if((r4818 & 0x60) == 0x20) {
+        unsigned increment = data_adjust() & 0xff;
+        if(r4818 & 8) increment = (int8)increment; //8-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      } else if((r4818 & 0x60) == 0x40) {
+        unsigned increment = data_adjust();
+        if(r4818 & 8) increment = (int16)increment; //16-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      }
+    } break;
+    case 0x4815: {
+      r4815 = data;
+      r481x |= 0x10;
+      r4815_latch = true;
+      if(!r4814_latch) break;
+      if(!(r4818 & 2)) break;
+      if(r4818 & 0x10) break;
+
+      if((r4818 & 0x60) == 0x20) {
+        unsigned increment = data_adjust() & 0xff;
+        if(r4818 & 8) increment = (int8)increment; //8-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      } else if((r4818 & 0x60) == 0x40) {
+        unsigned increment = data_adjust();
+        if(r4818 & 8) increment = (int16)increment; //16-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      }
+    } break;
+    case 0x4816: r4816 = data; break;
+    case 0x4817: r4817 = data; break;
+    case 0x4818: {
+      if(r481x != 0x1f) break;
+
+      r4818 = data;
+      r4814_latch = r4815_latch = false;
+    } break;
+
+    //=========
+    //math unit
+    //=========
+
+    case 0x4820: r4820 = data; break;
+    case 0x4821: r4821 = data; break;
+    case 0x4822: r4822 = data; break;
+    case 0x4823: r4823 = data; break;
+    case 0x4824: r4824 = data; break;
+    case 0x4825: {
+      r4825 = data;
+
+      if(r482e & 1) {
+        //signed 16-bit x 16-bit multiplication
+        int16 r0 = (int16)(r4824 + (r4825 << 8));
+        int16 r1 = (int16)(r4820 + (r4821 << 8));
+
+        signed result = r0 * r1;
+        r4828 = result;
+        r4829 = result >> 8;
+        r482a = result >> 16;
+        r482b = result >> 24;
+      } else {
+        //unsigned 16-bit x 16-bit multiplication
+        uint16 r0 = (uint16)(r4824 + (r4825 << 8));
+        uint16 r1 = (uint16)(r4820 + (r4821 << 8));
+
+        unsigned result = r0 * r1;
+        r4828 = result;
+        r4829 = result >> 8;
+        r482a = result >> 16;
+        r482b = result >> 24;
+      }
+
+      r482f = 0x80;
+    } break;
+    case 0x4826: r4826 = data; break;
+    case 0x4827: {
+      r4827 = data;
+
+      if(r482e & 1) {
+        //signed 32-bit x 16-bit division
+        int32 dividend = (int32)(r4820 + (r4821 << 8) + (r4822 << 16) + (r4823 << 24));
+        int16 divisor  = (int16)(r4826 + (r4827 << 8));
+
+        int32 quotient;
+        int16 remainder;
+
+        if(divisor) {
+          quotient  = (int32)(dividend / divisor);
+          remainder = (int32)(dividend % divisor);
+        } else {
+          //illegal division by zero
+          quotient  = 0;
+          remainder = dividend & 0xffff;
+        }
+
+        r4828 = quotient;
+        r4829 = quotient >> 8;
+        r482a = quotient >> 16;
+        r482b = quotient >> 24;
+
+        r482c = remainder;
+        r482d = remainder >> 8;
+      } else {
+        //unsigned 32-bit x 16-bit division
+        uint32 dividend = (uint32)(r4820 + (r4821 << 8) + (r4822 << 16) + (r4823 << 24));
+        uint16 divisor  = (uint16)(r4826 + (r4827 << 8));
+
+        uint32 quotient;
+        uint16 remainder;
+
+        if(divisor) {
+          quotient  = (uint32)(dividend / divisor);
+          remainder = (uint16)(dividend % divisor);
+        } else {
+          //illegal division by zero
+          quotient  = 0;
+          remainder = dividend & 0xffff;
+        }
+
+        r4828 = quotient;
+        r4829 = quotient >> 8;
+        r482a = quotient >> 16;
+        r482b = quotient >> 24;
+
+        r482c = remainder;
+        r482d = remainder >> 8;
+      }
+
+      r482f = 0x80;
+    } break;
+
+    case 0x482e: {
+      //reset math unit
+      r4820 = r4821 = r4822 = r4823 = 0;
+      r4824 = r4825 = r4826 = r4827 = 0;
+      r4828 = r4829 = r482a = r482b = 0;
+      r482c = r482d = 0;
+
+      r482e = data;
+    } break;
+
+    //===================
+    //memory mapping unit
+    //===================
+
+    case 0x4830: r4830 = data; break;
+
+    case 0x4831: {
+      r4831 = data;
+      dx_offset = datarom_addr((data & 7) * 0x100000);
+    } break;
+
+    case 0x4832: {
+      r4832 = data;
+      ex_offset = datarom_addr((data & 7) * 0x100000);
+    } break;
+
+    case 0x4833: {
+      r4833 = data;
+      fx_offset = datarom_addr((data & 7) * 0x100000);
+    } break;
+
+    case 0x4834: r4834 = data; break;
+
+    //====================
+    //real-time clock unit
+    //====================
+
+    case 0x4840: {
+      r4840 = data;
+      if(!(r4840 & 1)) {
+        //disable RTC
+        rtc_state = RTCS_Inactive;
+        update_time();
+      } else {
+        //enable RTC
+        r4842 = 0x80;
+        rtc_state = RTCS_ModeSelect;
+      }
+    } break;
+
+    case 0x4841: {
+      r4841 = data;
+
+      switch(rtc_state) {
+        case RTCS_ModeSelect: {
+          if(data == RTCM_Linear || data == RTCM_Indexed) {
+            r4842 = 0x80;
+            rtc_state = RTCS_IndexSelect;
+            rtc_mode  = (RTC_Mode)data;
+            rtc_index = 0;
+          }
+        } break;
+
+        case RTCS_IndexSelect: {
+          r4842 = 0x80;
+          rtc_index = data & 15;
+          if(rtc_mode == RTCM_Linear) rtc_state = RTCS_Write;
+        } break;
+
+        case RTCS_Write: {
+          r4842 = 0x80;
+
+          //control register 0
+          if(rtc_index == 13) {
+            //increment second counter
+            if(data & 2) update_time(+1);
+
+            //round minute counter
+            if(data & 8) {
+              update_time();
+
+              unsigned second = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
+              //clear seconds
+              memory::cartrtc.write(0, 0);
+              memory::cartrtc.write(1, 0);
+
+              if(second >= 30) update_time(+60);
+            }
+          }
+
+          //control register 2
+          if(rtc_index == 15) {
+            //disable timer and clear second counter
+            if((data & 1) && !(memory::cartrtc.read(15) & 1)) {
+              update_time();
+
+              //clear seconds
+              memory::cartrtc.write(0, 0);
+              memory::cartrtc.write(1, 0);
+            }
+
+            //disable timer
+            if((data & 2) && !(memory::cartrtc.read(15) & 2)) {
+              update_time();
+            }
+          }
+
+          memory::cartrtc.write(rtc_index, data & 15);
+          rtc_index = (rtc_index + 1) & 15;
+        } break;
+      } //switch(rtc_state)
+    } break;
+  }
+}
+
+uint8 SPC7110::read(uint addr) {
+  if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
+    //$[00|30]:[6000-7fff]
+    return memory::cartram.read(addr & 0x1fff);
+  }
+
+  if((addr & 0x708000) == 0x008000) {
+    //$[00-0f|80-8f]:[8000-ffff]
+    return memory::cartrom.read(addr & 0x0fffff);
+  }
+
+  if((addr & 0xff0000) == 0x500000) {
+    //$[50]:[0000-ffff]
+    return mmio_read(0x4800);
+  }
+
+  if((addr & 0xf00000) == 0xc00000) {
+    //$[c0-cf]:[0000-ffff]
+    return memory::cartrom.read(addr & 0x0fffff);
+  }
+
+  if((addr & 0xf00000) == 0xd00000) {
+    //$[d0-df]:[0000-ffff]
+    return memory::cartrom.read(dx_offset + (addr & 0x0fffff));
+  }
+
+  if((addr & 0xf00000) == 0xe00000) {
+    //$[e0-ef]:[0000-ffff]
+    return memory::cartrom.read(ex_offset + (addr & 0x0fffff));
+  }
+
+  if((addr & 0xf00000) == 0xf00000) {
+    //$[f0-ff]:[0000-ffff]
+    return memory::cartrom.read(fx_offset + (addr & 0x0fffff));
+  }
+
+  return cpu.regs.mdr;
+}
+
+void SPC7110::write(uint addr, uint8 data) {
+  if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
+    //$[00|30]:[6000-7fff]
+    if(r4830 & 0x80) memory::cartram.write(addr & 0x1fff, data);
+    return;
+  }
+}
+
+SPC7110::SPC7110() {
+}

src/chip/spc7110/spc7110.h

@@ -0,0 +1,130 @@
+/*****
+ * SPC7110 emulator - version 0.1 (2008-07-19)
+ * Copyright (c) 2008, byuu and neviksti
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * The software is provided "as is" and the author disclaims all warranties
+ * with regard to this software including all implied warranties of
+ * merchantibility and fitness, in no event shall the author be liable for
+ * any special, direct, indirect, or consequential damages or any damages
+ * whatsoever resulting from loss of use, data or profits, whether in an
+ * action of contract, negligence or other tortious action, arising out of
+ * or in connection with the use or performance of this software.
+ *****/
+
+#include "codec.h"
+
+class SPC7110 : public MMIO, public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  unsigned datarom_addr(unsigned addr);
+
+  unsigned data_pointer();
+  unsigned data_adjust();
+  unsigned data_increment();
+  void set_data_pointer(unsigned addr);
+  void set_data_adjust(unsigned addr);
+
+  void update_time(int offset = 0);
+  time_t create_time();
+
+  uint8 mmio_read (uint addr);
+  void  mmio_write(uint addr, uint8 data);
+
+  uint8 read (uint addr);
+  void  write(uint addr, uint8 data);
+
+  SPC7110();
+
+private:
+  //==================
+  //decompression unit
+  //==================
+  uint8 r4801; //compression table low
+  uint8 r4802; //compression table high
+  uint8 r4803; //compression table bank
+  uint8 r4804; //compression table index
+  uint8 r4805; //decompression buffer index low
+  uint8 r4806; //decompression buffer index high
+  uint8 r4807; //???
+  uint8 r4808; //???
+  uint8 r4809; //compression length low
+  uint8 r480a; //compression length high
+  uint8 r480b; //decompression control register
+  uint8 r480c; //decompression status
+
+  SPC7110Codec codec;
+  uint16 decomp_offset;
+
+  //==============
+  //data port unit
+  //==============
+  uint8 r4811; //data pointer low
+  uint8 r4812; //data pointer high
+  uint8 r4813; //data pointer bank
+  uint8 r4814; //data adjust low
+  uint8 r4815; //data adjust high
+  uint8 r4816; //data increment low
+  uint8 r4817; //data increment high
+  uint8 r4818; //data port control register
+
+  uint8 r481x;
+
+  bool r4814_latch;
+  bool r4815_latch;
+
+  //=========
+  //math unit
+  //=========
+  uint8 r4820; //16-bit multiplicand B0, 32-bit dividend B0
+  uint8 r4821; //16-bit multiplicand B1, 32-bit dividend B1
+  uint8 r4822; //32-bit dividend B2
+  uint8 r4823; //32-bit dividend B3
+  uint8 r4824; //16-bit multiplier B0
+  uint8 r4825; //16-bit multiplier B1
+  uint8 r4826; //16-bit divisor B0
+  uint8 r4827; //16-bit divisor B1
+  uint8 r4828; //32-bit product B0, 32-bit quotient B0
+  uint8 r4829; //32-bit product B1, 32-bit quotient B1
+  uint8 r482a; //32-bit product B2, 32-bit quotient B2
+  uint8 r482b; //32-bit product B3, 32-bit quotient B3
+  uint8 r482c; //16-bit remainder B0
+  uint8 r482d; //16-bit remainder B1
+  uint8 r482e; //math control register
+  uint8 r482f; //math status
+
+  //===================
+  //memory mapping unit
+  //===================
+  uint8 r4830; //SRAM write enable
+  uint8 r4831; //$[d0-df]:[0000-ffff] mapping
+  uint8 r4832; //$[e0-ef]:[0000-ffff] mapping
+  uint8 r4833; //$[f0-ff]:[0000-ffff] mapping
+  uint8 r4834; //???
+
+  unsigned dx_offset;
+  unsigned ex_offset;
+  unsigned fx_offset;
+
+  //====================
+  //real-time clock unit
+  //====================
+  uint8 r4840; //RTC latch
+  uint8 r4841; //RTC index/data port
+  uint8 r4842; //RTC status
+
+  enum RTC_State { RTCS_Inactive, RTCS_ModeSelect, RTCS_IndexSelect, RTCS_Write } rtc_state;
+  enum RTC_Mode  { RTCM_Linear = 0x03, RTCM_Indexed = 0x0c } rtc_mode;
+  unsigned rtc_index;
+
+  static const unsigned months[12];
+};
+
+extern SPC7110 spc7110;

src/chip/srtc/srtc.cpp

@@ -1,189 +1,213 @@
-/*
-  S-RTC chip emulation
-  Used by Hudson Soft in Dai Kaijuu Monogatari II and Far East of Eden Zero.
-  Currently, only the former is supported by bsnes.
-
-  Original S-RTC emulation code via John Weidman/SNES9x
-  Rewritten for compatibility with bsnes via byuu
-
-  The S-RTC is a real-time clock chip that was added to the above two carts
-  to allow the games to maintain the current time, even when the game was not
-  powered on. Thus allowing special events at certain times, and on certain
-  dates. Hudson Soft called this the PLG (Player's Life Gameplay System).
-
-  This chip is a special case to the term 'emulation' itself.
-  There are a few different ways to go about emulating this chip, and each
-  result in a different style of emulation.
-
-  The first is to simply return the current PC system time when the S-RTC is
-  read from. This emulates the original S-RTC in the sense that it always
-  returns the true current time, ignoring the speed that the SNES itself is
-  running at. The downside to this method is that you lose the ability to set
-  the time to whatever you choose inside the game itself. It will always return
-  the true time, regardless. This can be overcome by changing the PC system time,
-  which actually adds a greater degree of control over event timing, very useful
-  for emulation. It also has a timeshifting flaw discussed below.
-
-  The second is to run the S-RTC relative to the SNES speed. This means that
-  if the emulator is sped up (via fast forward key, frameskipping, etc), or
-  slowed down (via slowdown key, system bottlenecking, etc); the time increments
-  slower, thus ~60 frames on the SNES equal one second. Without this, timeshifting
-  will occur between the S-RTC and the real SNES.
-
-  The third and final method is to save a copy of the local system time when the
-  S-RTC is initially set, and compare the current system time against this value
-  when setting the S-RTC time. This overcomes the first methods' shortcoming of
-  not allowing the player to set the time in-game, however a new problem arises.
-  You now have to save the time when the RTC was initially set to both savestates
-  and to save-game data. This would require an extra file, or the breaking of
-  perhaps the only standard format (.srm savegame backups) in the entire SNES
-  emulation scene. You also give up the control of being able to override the
-  RTC clock at will via the PC system time outside of emulation.
-  The first method has another advantage over the third: Dai Kaijuu Monogatari II
-  only allows dates in the range of the years 1996-2199. The first method gets
-  around this limitation. But who knows, maybe it will break something in the
-  game if the date exceeds 2199... I guess we'll worry about that in two hundred
-  years from now.
-
-  For my implementation, I chose to go with the first method. Both for simplicity
-  and because I did not wish to create a new method for saving the system time
-  whenever the RTC is set.
-*/
-
-#include "../../base.h"
-
-void SRTC::set_time() {
-time_t rawtime;
-tm *t;
-  ::time(&rawtime);
-  t = localtime(&rawtime);
-
-//see srtc.h for format of srtc.data[]
-  srtc.data[0]  = t->tm_sec % 10;
-  srtc.data[1]  = t->tm_sec / 10;
-  srtc.data[2]  = t->tm_min % 10;
-  srtc.data[3]  = t->tm_min / 10;
-  srtc.data[4]  = t->tm_hour % 10;
-  srtc.data[5]  = t->tm_hour / 10;
-  srtc.data[6]  = t->tm_mday % 10;
-  srtc.data[7]  = t->tm_mday / 10;
-  srtc.data[8]  = t->tm_mon + 1;
-  srtc.data[9]  = t->tm_year % 10;
-  srtc.data[10] = (t->tm_year / 10) % 10;
-  srtc.data[11] = 9 + (t->tm_year / 100);
-  srtc.data[12] = t->tm_wday;
-}
-
-void SRTC::init() {}
-
-void SRTC::enable() {
-  memory::mmio.map(0x2800, *this);
-  memory::mmio.map(0x2801, *this);
-}
-
-void SRTC::power() {
-  memset(&srtc, 0, sizeof(srtc));
-  reset();
-}
-
-void SRTC::reset() {
-  srtc.index = -1;
-  srtc.mode  = SRTC_READ;
-}
-
-uint8 SRTC::mmio_read(uint addr) {
-  switch(addr & 0xffff) {
-
-  case 0x2800: {
-    if(srtc.mode == SRTC_READ) {
-      if(srtc.index < 0) {
-        set_time();
-        srtc.index++;
-        return 0x0f; //send start message
-      } else if(srtc.index > MAX_SRTC_INDEX) {
-        srtc.index = -1;
-        return 0x0f; //send finished message
-      } else {
-        return srtc.data[srtc.index++];
-      }
-    } else {
-      return 0x00;
-    }
-  } break;
-
-  case 0x2801: {
-  } break;
-
-  }
-
-  return cpu.regs.mdr;
-}
-
-//Please see notes above about the implementation of the S-RTC
-//Writes are stored the srtc.data[] array, but they are ignored
-//as reads will refresh the data array with the current system
-//time. The write method is only here for the sake of faux
-//emulation of the real hardware.
-void SRTC::mmio_write(uint addr, uint8 data) {
-  switch(addr & 0xffff) {
-
-  case 0x2800: {
-  } break;
-
-  case 0x2801: {
-    data &= 0x0f; //only the low four bits are used
-
-    if(data >= 0x0d) {
-      switch(data) {
-      case 0x0d:
-        srtc.mode  = SRTC_READ;
-        srtc.index = -1;
-        break;
-      case 0x0e:
-        srtc.mode = SRTC_COMMAND;
-        break;
-      case 0x0f:
-      //unknown behaviour
-        break;
-      }
-      return;
-    }
-
-    if(srtc.mode == SRTC_WRITE) {
-      if(srtc.index >= 0 && srtc.index < MAX_SRTC_INDEX) {
-        srtc.data[srtc.index++] = data;
-
-        if(srtc.index == MAX_SRTC_INDEX) {
-        //all S-RTC data has been loaded by program
-          srtc.data[srtc.index++] = 0x00; //day_of_week
-        }
-      }
-    } else if(srtc.mode == SRTC_COMMAND) {
-      switch(data) {
-      case SRTC_COMMAND_CLEAR:
-        memset(srtc.data, 0, MAX_SRTC_INDEX + 1);
-        srtc.index = -1;
-        srtc.mode  = SRTC_READY;
-        break;
-      case SRTC_COMMAND_WRITE:
-        srtc.index = 0;
-        srtc.mode  = SRTC_WRITE;
-        break;
-      default:
-      //unknown behaviour
-        srtc.mode  = SRTC_READY;
-        break;
-      }
-    } else {
-      if(srtc.mode == SRTC_READ) {
-      //ignore writes while in read mode
-      } else if(srtc.mode == SRTC_READY) {
-      //unknown behaviour
-      }
-    }
-  } break;
-
-  }
-}
-
-SRTC::SRTC() {}
+#include "../../base.h"
+
+const unsigned SRTC::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+void SRTC::init() {
+}
+
+void SRTC::enable() {
+  memory::mmio.map(0x2800, *this);
+  memory::mmio.map(0x2801, *this);
+}
+
+void SRTC::power() {
+  reset();
+}
+
+void SRTC::reset() {
+  rtc_mode = RTCM_Read;
+  rtc_index = -1;
+  update_time();
+}
+
+void SRTC::update_time() {
+  time_t rtc_time;
+  rtc_time  = memory::cartrtc.read(16);
+  rtc_time |= memory::cartrtc.read(17) << 8;
+  rtc_time |= memory::cartrtc.read(18) << 16;
+  rtc_time |= memory::cartrtc.read(19) << 24;
+
+  time_t current_time = time(0);
+  if(current_time > rtc_time) {
+    unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
+    unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
+    unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
+    unsigned day     = memory::cartrtc.read( 6) + memory::cartrtc.read( 7) * 10;
+    unsigned month   = memory::cartrtc.read( 8);
+    unsigned year    = memory::cartrtc.read( 9) + memory::cartrtc.read(10) * 10 + memory::cartrtc.read(11) * 100;
+    unsigned weekday = memory::cartrtc.read(12);
+
+    day--;
+    month--;
+    year += 1000;
+
+    second += (unsigned)(current_time - rtc_time);
+
+    while(second >= 60) {
+      second -= 60;
+
+      minute++;
+      if(minute < 60) continue;
+      minute = 0;
+
+      hour++;
+      if(hour < 24) continue;
+      hour = 0;
+
+      day++;
+      weekday = (weekday + 1) % 7;
+      unsigned days = months[month % 12];
+      if(days == 28) {
+        bool leapyear = false;
+        if((year % 4) == 0) {
+          leapyear = true;
+          if((year % 100) == 0 && (year % 400) != 0) leapyear = false;
+        }
+        if(leapyear) days++;
+      }
+      if(day < days) continue;
+      day = 0;
+
+      month++;
+      if(month < 12) continue;
+      month = 0;
+
+      year++;
+    }
+
+    day++;
+    month++;
+    year -= 1000;
+
+    memory::cartrtc.write( 0, second % 10);
+    memory::cartrtc.write( 1, second / 10);
+    memory::cartrtc.write( 2, minute % 10);
+    memory::cartrtc.write( 3, minute / 10);
+    memory::cartrtc.write( 4, hour % 10);
+    memory::cartrtc.write( 5, hour / 10);
+    memory::cartrtc.write( 6, day % 10);
+    memory::cartrtc.write( 7, day / 10);
+    memory::cartrtc.write( 8, month);
+    memory::cartrtc.write( 9, year % 10);
+    memory::cartrtc.write(10, (year / 10) % 10);
+    memory::cartrtc.write(11, year / 100);
+    memory::cartrtc.write(12, weekday % 7);
+  }
+
+  memory::cartrtc.write(16, current_time);
+  memory::cartrtc.write(17, current_time >> 8);
+  memory::cartrtc.write(18, current_time >> 16);
+  memory::cartrtc.write(19, current_time >> 24);
+}
+
+//returns day of week for specified date
+//eg 0 = Sunday, 1 = Monday, ... 6 = Saturday
+//usage: weekday(2008, 1, 1) returns weekday of January 1st, 2008
+unsigned SRTC::weekday(unsigned year, unsigned month, unsigned day) {
+  unsigned y = 1900, m = 1; //epoch is 1900-01-01
+  unsigned sum = 0; //number of days passed since epoch
+
+  year = max(1900, year);
+  month = max(1, min(12, month));
+  day = max(1, min(31, day));
+
+  while(y < year) {
+    bool leapyear = false;
+    if((y % 4) == 0) {
+      leapyear = true;
+      if((y % 100) == 0 && (y % 400) != 0) leapyear = false;
+    }
+    sum += leapyear ? 366 : 365;
+    y++;
+  }
+
+  while(m < month) {
+    unsigned days = months[m - 1];
+    if(days == 28) {
+      bool leapyear = false;
+      if((y % 4) == 0) {
+        leapyear = true;
+        if((y % 100) == 0 && (y % 400) != 0) leapyear = false;
+      }
+      if(leapyear) days++;
+    }
+    sum += days;
+    m++;
+  }
+
+  sum += day - 1;
+  return (sum + 1) % 7; //1900-01-01 was a Monday
+}
+
+uint8 SRTC::mmio_read(uint addr) {
+  addr &= 0xffff;
+
+  if(addr == 0x2800) {
+    if(rtc_mode != RTCM_Read) return 0x00;
+
+    if(rtc_index < 0) {
+      update_time();
+      rtc_index++;
+      return 0x0f;
+    } else if(rtc_index > 12) {
+      rtc_index = -1;
+      return 0x0f;
+    } else {
+      return memory::cartrtc.read(rtc_index++);
+    }
+  }
+
+  return cpu.regs.mdr;
+}
+
+void SRTC::mmio_write(uint addr, uint8 data) {
+  addr &= 0xffff;
+
+  if(addr == 0x2801) {
+    data &= 0x0f; //only the low four bits are used
+
+    if(data == 0x0d) {
+      rtc_mode = RTCM_Read;
+      rtc_index = -1;
+      return;
+    }
+
+    if(data == 0x0e) {
+      rtc_mode = RTCM_Command;
+      return;
+    }
+
+    if(data == 0x0f) return; //unknown behavior
+
+    if(rtc_mode == RTCM_Write) {
+      if(rtc_index >= 0 && rtc_index < 12) {
+        memory::cartrtc.write(rtc_index++, data);
+
+        if(rtc_index == 12) {
+          //day of week is automatically calculated and written
+          unsigned day   = memory::cartrtc.read( 6) + memory::cartrtc.read( 7) * 10;
+          unsigned month = memory::cartrtc.read( 8);
+          unsigned year  = memory::cartrtc.read( 9) + memory::cartrtc.read(10) * 10 + memory::cartrtc.read(11) * 100;
+          year += 1000;
+
+          memory::cartrtc.write(rtc_index++, weekday(year, month, day));
+        }
+      }
+    } else if(rtc_mode == RTCM_Command) {
+      if(data == 0) {
+        rtc_mode = RTCM_Write;
+        rtc_index = 0;
+      } else if(data == 4) {
+        rtc_mode = RTCM_Ready;
+        rtc_index = -1;
+        for(unsigned i = 0; i < 13; i++) memory::cartrtc.write(i, 0);
+      } else {
+        //unknown behavior
+        rtc_mode = RTCM_Ready;
+      }
+    }
+  }
+}
+
+SRTC::SRTC() {
+}

src/chip/srtc/srtc.h

@@ -1,52 +1,22 @@
-class SRTC : public MMIO {
-public:
-enum { MAX_SRTC_INDEX = 0x0c };
-
-enum {
-  SRTC_READ = 0,
-  SRTC_WRITE,
-  SRTC_COMMAND,
-  SRTC_READY
-};
-
-enum {
-  SRTC_COMMAND_WRITE = 0,
-  SRTC_COMMAND_CLEAR = 4
-};
-
-/******************************
-[srtc.data structure]
-Index  Description   Range
------  -----------   -----
-    0  Seconds low   0-9
-    1  Seconds high  0-5
-    2  Minutes low   0-9
-    3  Minutes high  0-5
-    4  Hour low      0-9
-    5  Hour high     0-2
-    6  Day low       0-9
-    7  Day high      0-3
-    8  Month         1-12
-    9  Year ones     0-9
-   10  Year tens     0-9
-   11  Year hundreds 9-11 (9=19xx, 10=20xx, 11=21xx)
-   12  Day of week   0-6  (0=Sunday, ...)
-******************************/
-struct {
-  int8  index;
-  uint8 mode;
-  uint8 data[MAX_SRTC_INDEX + 1];
-} srtc;
-  void  set_time();
-  void  init();
-  void  enable();
-  void  power();
-  void  reset();
-
-  uint8 mmio_read (uint addr);
-  void  mmio_write(uint addr, uint8 data);
-
-  SRTC();
-};
-
-extern SRTC srtc;
+class SRTC : public MMIO {
+public:
+  void update_time();
+  unsigned weekday(unsigned year, unsigned month, unsigned day);
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read (uint addr);
+  void  mmio_write(uint addr, uint8 data);
+
+  SRTC();
+
+private:
+  static const unsigned months[12];
+  enum RTC_Mode { RTCM_Ready, RTCM_Command, RTCM_Read, RTCM_Write } rtc_mode;
+  signed rtc_index;
+};
+
+extern SRTC srtc;

src/chip/st010/st010.cpp

@@ -1,4 +1,6 @@
-#include "../../base.h"
+#include "../../base.h"
+#define ST010_CPP
+
 #include "st010_data.h"
 #include "st010_op.cpp"
 

src/chip/st010/st010_op.cpp

@@ -1,3 +1,5 @@
+#ifdef ST010_CPP
+
 //ST-010 emulation code - Copyright (C) 2003 The Dumper, Matthew Kendora, Overload, Feather
 //bsnes port - Copyright (C) 2007 byuu
 
@@ -255,3 +257,5 @@ int16 x1, y1;
   writew(0x0010, x1);
   writew(0x0012, y1);
 }
+
+#endif //ifdef ST010_CPP

src/config/config.cpp

@@ -1,66 +1,67 @@
 namespace config {
 
 configuration& config() {
-static configuration config;
+  static configuration config;
   return config;
-}
+}
+
+integral_setting File::autodetect_type(config(), "file.autodetect_type",
+  "Auto-detect file type by inspecting file header, rather than by file extension.\n"
+  "In other words, if a .zip file is renamed to .smc, it will still be correctly\n"
+  "identified as a .zip file. However, there is an infinitesimal (1:~500,000,000)\n"
+  "chance of a false detection when loading an uncompressed image file, if this\n"
+  "option is enabled.",
+  integral_setting::boolean, false);
+
+integral_setting File::bypass_patch_crc32(config(), "file.bypass_patch_crc32",
+  "UPS patches contain CRC32s to validate that a patch was applied successfully.\n"
+  "By default, if this validation fails, said patch will not be applied.\n"
+  "Setting this option to true will bypass the validation,\n"
+  "which may or may not result in a working image.\n"
+  "Enabling this option is strongly discouraged.",
+  integral_setting::boolean, false);
 
 string file_updatepath(const char *req_file, const char *req_path) {
-string file(req_file);
+  string file(req_file);
   replace(file, "\\", "/");
   if(!req_path || strlen(req_path) == 0) { return file; }
 
-string path(req_path);
+  string path(req_path);
   replace(path, "\\", "/");
   if(!strend(path, "/")) { strcat(path, "/"); }
 
   if(strbegin(path, "./")) {
     ltrim(path(), "./");
-  string temp;
+    string temp;
     strcpy(temp, config::path.base);
     strcat(temp, path);
     strcpy(path, temp);
   }
 
-lstring part;
+  lstring part;
   split(part, "/", file);
   strcat(path, part[count(part) - 1]);
   return path;
 }
 
-string_setting Path::base("path.base",
-  "Path that bsnes resides in", "");
+string_setting Path::base("path.base", "Path that bsnes resides in", "");
+string_setting Path::user("path.user", "Path to user folder", "");
+
 string_setting Path::rom(config(), "path.rom",
-  "Default path to look for ROM files in (\"\" = use default directory)", "");
-string_setting Path::save(config(), "path.save",
-  "Default path for all save RAM and cheat files (\"\" = use current directory)", "");
+  "Default path to look for ROM files in (\"\" = use default directory)", "");
+string_setting Path::patch(config(), "path.patch",
+  "Default path for all UPS patch files (\"\" = use current directory)", "");
+string_setting Path::save(config(), "path.save",
+  "Default path for all save RAM files (\"\" = use current directory)", "");
+string_setting Path::cheat(config(), "path.cheat",
+  "Default path for all cheat files (\"\" = use current directory)", "");
 string_setting Path::bsx(config(), "path.bsx", "", "");
 string_setting Path::st(config(), "path.st", "", "");
 
-integral_setting SNES::gamma_ramp(config(), "snes.colorfilter.gamma_ramp",
-  "Use precalculated TV-style gamma ramp", integral_setting::boolean, true);
-integral_setting SNES::sepia(config(), "snes.colorfilter.sepia",
-  "Convert color to sepia tone", integral_setting::boolean, false);
-integral_setting SNES::grayscale(config(), "snes.colorfilter.grayscale",
-  "Convert color to grayscale tone", integral_setting::boolean, false);
-integral_setting SNES::invert(config(), "snes.colorfilter.invert",
-  "Invert output image colors", integral_setting::boolean, false);
-integral_setting SNES::contrast(config(), "snes.colorfilter.contrast",
-  "Contrast", integral_setting::decimal, 0);
-integral_setting SNES::brightness(config(), "snes.colorfilter.brightness",
-  "Brightness", integral_setting::decimal, 0);
-integral_setting SNES::gamma(config(), "snes.colorfilter.gamma",
-  "Gamma", integral_setting::decimal, 80);
-
-integral_setting SNES::ntsc_merge_fields(config(), "snes.ntsc_merge_fields",
-  "Merge fields in NTSC video filter\n"
-  "Set to true if using filter at any refresh rate other than 60hz\n"
-  "", integral_setting::boolean, true);
-
 integral_setting SNES::controller_port0(config(), "snes.controller_port_1",
-  "Controller attached to SNES port 1", integral_setting::decimal, ::SNES::DEVICEID_JOYPAD1);
+  "Controller attached to SNES port 1", integral_setting::decimal, ::SNES::Input::DeviceIDJoypad1);
 integral_setting SNES::controller_port1(config(), "snes.controller_port_2",
-  "Controller attached to SNES port 2", integral_setting::decimal, ::SNES::DEVICEID_JOYPAD2);
+  "Controller attached to SNES port 2", integral_setting::decimal, ::SNES::Input::DeviceIDJoypad2);
 
 integral_setting CPU::ntsc_clock_rate(config(), "cpu.ntsc_clock_rate",
   "NTSC S-CPU clock rate (in hz)", integral_setting::decimal, 21477272);
@@ -126,4 +127,4 @@ integral_setting PPU::oam_pri1_enable("ppu.oam_pri1_enable", "Enable OAM Priorit
 integral_setting PPU::oam_pri2_enable("ppu.oam_pri2_enable", "Enable OAM Priority 2", integral_setting::boolean, true);
 integral_setting PPU::oam_pri3_enable("ppu.oam_pri3_enable", "Enable OAM Priority 3", integral_setting::boolean, true);
 
-};
+} //namespace config

src/config/config.h

@@ -2,16 +2,19 @@ namespace config {
 
 extern configuration& config();
 
-string file_updatepath(const char *, const char *);
+string file_updatepath(const char*, const char*);
+
+extern struct File {
+  static integral_setting autodetect_type;
+  static integral_setting bypass_patch_crc32;
+} file;
 
 extern struct Path {
-  static string_setting base, rom, save;
+  static string_setting base, user, rom, patch, save, cheat;
   static string_setting bsx, st;
 } path;
 
 extern struct SNES {
-  static integral_setting gamma_ramp, sepia, grayscale, invert, contrast, brightness, gamma;
-  static integral_setting ntsc_merge_fields;
   static integral_setting controller_port0;
   static integral_setting controller_port1;
 } snes;

src/cpu/cpu.cpp

@@ -1,4 +1,6 @@
-#include "../base.h"
+#include "../base.h"
+#define CPU_CPP
+
 #include "dcpu.cpp"
 
 CPU::CPU() {

src/cpu/cpu.h

@@ -4,81 +4,75 @@ class CPU : public MMIO {
 public:
   virtual void enter() = 0;
 
-public:
-//CPU version number
-//* 1 and 2 are known
-//* reported by $4210
-//* affects DRAM refresh behavior
-uint8 cpu_version;
+  //CPU version number
+  //* 1 and 2 are known
+  //* reported by $4210
+  //* affects DRAM refresh behavior
+  uint8 cpu_version;
 
-//timing
+  //timing
   virtual uint16 vcounter() = 0;
   virtual uint16 hcounter() = 0;
-  virtual uint16 hclock() = 0;
-  virtual bool   interlace() = 0;
-  virtual bool   interlace_field() = 0;
-  virtual bool   overscan() = 0;
-  virtual uint16 region_scanlines() = 0;
-  virtual void   set_interlace(bool r) = 0;
-  virtual void   set_overscan (bool r) = 0;
-
-CPURegs regs;
-  virtual uint8 port_read (uint8 port) = 0;
-  virtual void  port_write(uint8 port, uint8 value) = 0;
+  virtual uint16 hdot() = 0;
 
+  virtual uint8 pio_status() = 0;
+  virtual uint8 port_read(uint8 port) = 0;
+  virtual void port_write(uint8 port, uint8 value) = 0;
+
+  CPURegs regs;
   enum {
     FLAG_N = 0x80, FLAG_V = 0x40,
     FLAG_M = 0x20, FLAG_X = 0x10,
     FLAG_D = 0x08, FLAG_I = 0x04,
     FLAG_Z = 0x02, FLAG_C = 0x01
   };
-  virtual uint8  pio_status() = 0;
-  virtual void   scanline() = 0;
-  virtual void   frame() = 0;
-  virtual void   power() = 0;
-  virtual void   reset() = 0;
+
+  virtual void scanline() = 0;
+  virtual void frame() = 0;
+  virtual void power() = 0;
+  virtual void reset() = 0;
 
-/*****
- * in opcode-based CPU emulators, the main emulation routine
- * will only be able to call the disassemble_opcode() function
- * on clean opcode edges. but with cycle-based CPU emulators,
- * the CPU may be in the middle of executing an opcode when the
- * emulator (e.g. debugger) wants to disassemble an opcode. this
- * would mean that important registers may not reflect what they
- * did at the start of the opcode (especially regs.pc), so in
- * cycle-based emulators, this function should be overridden to
- * reflect whether or not an opcode has only been partially
- * executed. if not, the debugger should abort attempts to skip,
- * disable, or disassemble the current opcode.
- *****/
+  /*****
+   * in opcode-based CPU emulators, the main emulation routine
+   * will only be able to call the disassemble_opcode() function
+   * on clean opcode edges. but with cycle-based CPU emulators,
+   * the CPU may be in the middle of executing an opcode when the
+   * emulator (e.g. debugger) wants to disassemble an opcode. this
+   * would mean that important registers may not reflect what they
+   * did at the start of the opcode (especially regs.pc), so in
+   * cycle-based emulators, this function should be overridden to
+   * reflect whether or not an opcode has only been partially
+   * executed. if not, the debugger should abort attempts to skip,
+   * disable, or disassemble the current opcode.
+   *****/
   virtual bool in_opcode() { return false; }
 
-/*****
- * opcode disassembler
- *****/
-enum {
-  OPTYPE_DP = 0,    //dp
-  OPTYPE_DPX,       //dp,x
-  OPTYPE_DPY,       //dp,y
-  OPTYPE_IDP,       //(dp)
-  OPTYPE_IDPX,      //(dp,x)
-  OPTYPE_IDPY,      //(dp),y
-  OPTYPE_ILDP,      //[dp]
-  OPTYPE_ILDPY,     //[dp],y
-  OPTYPE_ADDR,      //addr
-  OPTYPE_ADDRX,     //addr,x
-  OPTYPE_ADDRY,     //addr,y
-  OPTYPE_IADDRX,    //(addr,x)
-  OPTYPE_ILADDR,    //[addr]
-  OPTYPE_LONG,      //long
-  OPTYPE_LONGX,     //long, x
-  OPTYPE_SR,        //sr,s
-  OPTYPE_ISRY,      //(sr,s),y
-  OPTYPE_ADDR_PC,   //pbr:addr
-  OPTYPE_IADDR_PC,  //pbr:(addr)
-  OPTYPE_RELB,      //relb
-  OPTYPE_RELW,      //relw
-};
+  /*****
+   * opcode disassembler
+   *****/
+  enum {
+    OPTYPE_DP = 0,    //dp
+    OPTYPE_DPX,       //dp,x
+    OPTYPE_DPY,       //dp,y
+    OPTYPE_IDP,       //(dp)
+    OPTYPE_IDPX,      //(dp,x)
+    OPTYPE_IDPY,      //(dp),y
+    OPTYPE_ILDP,      //[dp]
+    OPTYPE_ILDPY,     //[dp],y
+    OPTYPE_ADDR,      //addr
+    OPTYPE_ADDRX,     //addr,x
+    OPTYPE_ADDRY,     //addr,y
+    OPTYPE_IADDRX,    //(addr,x)
+    OPTYPE_ILADDR,    //[addr]
+    OPTYPE_LONG,      //long
+    OPTYPE_LONGX,     //long, x
+    OPTYPE_SR,        //sr,s
+    OPTYPE_ISRY,      //(sr,s),y
+    OPTYPE_ADDR_PC,   //pbr:addr
+    OPTYPE_IADDR_PC,  //pbr:(addr)
+    OPTYPE_RELB,      //relb
+    OPTYPE_RELW,      //relw
+  };
 
   void   disassemble_opcode(char *output);
   uint8  dreadb(uint32 addr);

src/cpu/cpuregs.h

@@ -1,75 +1,88 @@
+template<int mask>
+struct CPUFlag {
+  uint8 &data;
+
+  inline operator bool() const { return data & mask; }
+  inline CPUFlag& operator=(bool i) { data = (data & ~mask) | (-i & mask); return *this; }
+
+  CPUFlag(uint8 &data_) : data(data_) {}
+};
+
 class CPURegFlags {
-public:
-union {
-  uint8 data;
-  struct {
-    bool order_msb8(n:1, v:1, m:1, x:1, d:1, i:1, z:1, c:1);
-  };
-};
+public:
+  uint8 data;
+  CPUFlag<0x80> n;
+  CPUFlag<0x40> v;
+  CPUFlag<0x20> m;
+  CPUFlag<0x10> x;
+  CPUFlag<0x08> d;
+  CPUFlag<0x04> i;
+  CPUFlag<0x02> z;
+  CPUFlag<0x01> c;
 
   inline operator unsigned() const { return data; }
-  template<typename T> inline unsigned operator  = (const T i) { data  = i; return data; }
-  template<typename T> inline unsigned operator |= (const T i) { data |= i; return data; }
-  template<typename T> inline unsigned operator ^= (const T i) { data ^= i; return data; }
-  template<typename T> inline unsigned operator &= (const T i) { data &= i; return data; }
+  inline unsigned operator  = (unsigned i) { data  = i; return data; }
+  inline unsigned operator |= (unsigned i) { data |= i; return data; }
+  inline unsigned operator ^= (unsigned i) { data ^= i; return data; }
+  inline unsigned operator &= (unsigned i) { data &= i; return data; }
 
-  CPURegFlags() : data(0) {}
+  CPURegFlags() : data(0), n(data), v(data), m(data), x(data), d(data), i(data), z(data), c(data) {}
 };
 
 class CPUReg16 {
 public:
-union {
-  uint16 w;
-  struct { uint8 order_lsb2(l, h); };
-};
+  union {
+    uint16 w;
+    struct { uint8 order_lsb2(l, h); };
+  };
 
   inline operator unsigned() const { return w; }
-  template<typename T> inline unsigned operator   = (const T i) { w   = i; return w; }
-  template<typename T> inline unsigned operator  |= (const T i) { w  |= i; return w; }
-  template<typename T> inline unsigned operator  ^= (const T i) { w  ^= i; return w; }
-  template<typename T> inline unsigned operator  &= (const T i) { w  &= i; return w; }
-  template<typename T> inline unsigned operator <<= (const T i) { w <<= i; return w; }
-  template<typename T> inline unsigned operator >>= (const T i) { w >>= i; return w; }
-  template<typename T> inline unsigned operator  += (const T i) { w  += i; return w; }
-  template<typename T> inline unsigned operator  -= (const T i) { w  -= i; return w; }
-  template<typename T> inline unsigned operator  *= (const T i) { w  *= i; return w; }
-  template<typename T> inline unsigned operator  /= (const T i) { w  /= i; return w; }
-  template<typename T> inline unsigned operator  %= (const T i) { w  %= i; return w; }
+  inline unsigned operator   = (unsigned i) { w   = i; return w; }
+  inline unsigned operator  |= (unsigned i) { w  |= i; return w; }
+  inline unsigned operator  ^= (unsigned i) { w  ^= i; return w; }
+  inline unsigned operator  &= (unsigned i) { w  &= i; return w; }
+  inline unsigned operator <<= (unsigned i) { w <<= i; return w; }
+  inline unsigned operator >>= (unsigned i) { w >>= i; return w; }
+  inline unsigned operator  += (unsigned i) { w  += i; return w; }
+  inline unsigned operator  -= (unsigned i) { w  -= i; return w; }
+  inline unsigned operator  *= (unsigned i) { w  *= i; return w; }
+  inline unsigned operator  /= (unsigned i) { w  /= i; return w; }
+  inline unsigned operator  %= (unsigned i) { w  %= i; return w; }
 
   CPUReg16() : w(0) {}
 };
 
 class CPUReg24 {
 public:
-union {
-  uint32 d;
-  struct { uint16 order_lsb2(w, wh); };
-  struct { uint8  order_lsb4(l, h, b, bh); };
-};
+  union {
+    uint32 d;
+    struct { uint16 order_lsb2(w, wh); };
+    struct { uint8  order_lsb4(l, h, b, bh); };
+  };
 
   inline operator unsigned() const { return d; }
-  template<typename T> inline unsigned operator   = (const T i) { d = uclip<24>(i);      return d; }
-  template<typename T> inline unsigned operator  |= (const T i) { d = uclip<24>(d  | i); return d; }
-  template<typename T> inline unsigned operator  ^= (const T i) { d = uclip<24>(d  ^ i); return d; }
-  template<typename T> inline unsigned operator  &= (const T i) { d = uclip<24>(d  & i); return d; }
-  template<typename T> inline unsigned operator <<= (const T i) { d = uclip<24>(d << i); return d; }
-  template<typename T> inline unsigned operator >>= (const T i) { d = uclip<24>(d >> i); return d; }
-  template<typename T> inline unsigned operator  += (const T i) { d = uclip<24>(d  + i); return d; }
-  template<typename T> inline unsigned operator  -= (const T i) { d = uclip<24>(d  - i); return d; }
-  template<typename T> inline unsigned operator  *= (const T i) { d = uclip<24>(d  * i); return d; }
-  template<typename T> inline unsigned operator  /= (const T i) { d = uclip<24>(d  / i); return d; }
-  template<typename T> inline unsigned operator  %= (const T i) { d = uclip<24>(d  % i); return d; }
+  inline unsigned operator   = (unsigned i) { d = uclip<24>(i);      return d; }
+  inline unsigned operator  |= (unsigned i) { d = uclip<24>(d  | i); return d; }
+  inline unsigned operator  ^= (unsigned i) { d = uclip<24>(d  ^ i); return d; }
+  inline unsigned operator  &= (unsigned i) { d = uclip<24>(d  & i); return d; }
+  inline unsigned operator <<= (unsigned i) { d = uclip<24>(d << i); return d; }
+  inline unsigned operator >>= (unsigned i) { d = uclip<24>(d >> i); return d; }
+  inline unsigned operator  += (unsigned i) { d = uclip<24>(d  + i); return d; }
+  inline unsigned operator  -= (unsigned i) { d = uclip<24>(d  - i); return d; }
+  inline unsigned operator  *= (unsigned i) { d = uclip<24>(d  * i); return d; }
+  inline unsigned operator  /= (unsigned i) { d = uclip<24>(d  / i); return d; }
+  inline unsigned operator  %= (unsigned i) { d = uclip<24>(d  % i); return d; }
 
   CPUReg24() : d(0) {}
 };
 
 class CPURegs {
 public:
-CPUReg24 pc;
-CPUReg16 a, x, y, s, d;
-CPURegFlags p;
-uint8 db;
-uint8 mdr;
-bool  e;
-  CPURegs() : db(0), mdr(0x00), e(false) {}
+  CPUReg24 pc;
+  CPUReg16 a, x, y, s, d;
+  CPURegFlags p;
+  uint8 db;
+  uint8 mdr;
+  bool e;
+  CPURegs() : db(0), mdr(0), e(false) {}
 };

src/cpu/dcpu.cpp

@@ -1,3 +1,5 @@
+#ifdef CPU_CPP
+
 uint8  CPU::dreadb(uint32 addr) {
   if((addr & 0x40ffff) >= 0x2000 && (addr & 0x40ffff) <= 0x5fff) {
   //$[00-3f|80-bf]:[2000-5fff]
@@ -423,7 +425,7 @@ uint8 op2 = dreadb(pc.d);
   strcat(s, t);
   strcat(s, " ");
 
-  sprintf(t, "V:%3d H:%4d", vcounter(), hclock());
+  sprintf(t, "V:%3d H:%4d", vcounter(), hcounter());
   strcat(s, t);
 }
 
@@ -473,3 +475,5 @@ static uint8 op_len_tbl[256] = {
   if(len == 6)return (regs.e || regs.p.x) ? 2 : 3;
   return len;
 }
+
+#endif //ifdef CPU_CPP

src/cpu/scpu/core/cc.bat

@@ -1,3 +0,0 @@
-cl /nologo /O2 scpugen.cpp
-@pause
-@del *.obj

src/cpu/scpu/core/cc.sh

@@ -0,0 +1,4 @@
+g++ -c scpugen.cpp -I../../../lib
+g++ -c ../../../lib/nall/string.cpp -I../../../lib
+g++ -o scpugen scpugen.o string.o
+rm *.o

src/cpu/scpu/core/clean.bat

@@ -1 +0,0 @@
-@del *.exe

src/cpu/scpu/core/clean.sh

@@ -0,0 +1 @@
+rm scpugen

src/cpu/scpu/core/core.cpp

@@ -1,11 +1,7 @@
+#ifdef SCPU_CPP
+
 #include "opfn.cpp"
 
-#include "op_read.cpp"
-#include "op_write.cpp"
-#include "op_rmw.cpp"
-#include "op_pc.cpp"
-#include "op_misc.cpp"
-
 void sCPU::enter() { loop:
   if(event.irq) {
     event.irq = false;
@@ -22,7 +18,13 @@ void sCPU::enter() { loop:
   tracer.trace_cpuop(); //traces CPU opcode (only if tracer is enabled)
 
   status.in_opcode = true;
-  (this->*optbl[op_readpc()])();
+  switch(op_readpc()) {
+    #include "op_read.cpp"
+    #include "op_write.cpp"
+    #include "op_rmw.cpp"
+    #include "op_pc.cpp"
+    #include "op_misc.cpp"
+  }
   status.in_opcode = false;
 
   goto loop;
@@ -41,10 +43,25 @@ void sCPU::op_irq() {
   regs.p.d  = 0;
   rd.h = op_read(event.irq_vector + 1);
   regs.pc.w = rd.w;
+}
+
+//immediate, 2-cycle opcodes with I/O cycle will become bus read
+//when an IRQ is to be triggered immediately after opcode completion
+//this affects the following opcodes:
+//  clc, cld, cli, clv, sec, sed, sei,
+//  tax, tay, txa, txy, tya, tyx,
+//  tcd, tcs, tdc, tsc, tsx, tcs,
+//  inc, inx, iny, dec, dex, dey,
+//  asl, lsr, rol, ror, nop, xce.
+alwaysinline void sCPU::op_io_irq() {
+  if(event.irq) {
+    //IRQ pending, modify I/O cycle to bus read cycle, do not increment PC
+    op_read(regs.pc.d);
+  } else {
+    op_io();
+  }
 }
 
-//
-
 alwaysinline void sCPU::op_io_cond2() {
   if(regs.d.l != 0x00) {
     op_io();
@@ -62,3 +79,5 @@ alwaysinline void sCPU::op_io_cond6(uint16 addr) {
     op_io();
   }
 }
+
+#endif //ifdef SCPU_CPP

src/cpu/scpu/core/core.h

@@ -1,57 +1,54 @@
-void (sCPU::*optbl[256])();
+  CPUReg24 aa, rd;
+  uint8_t dp, sp;
 
-CPUReg24 aa, rd;
-uint8    dp, sp;
-
-  void   op_irq();
+  void op_irq();
 
   inline bool in_opcode() { return status.in_opcode; }
 
-//op_read
-  void   op_adc_b();
-  void   op_adc_w();
-  void   op_and_b();
-  void   op_and_w();
-  void   op_bit_b();
-  void   op_bit_w();
-  void   op_cmp_b();
-  void   op_cmp_w();
-  void   op_cpx_b();
-  void   op_cpx_w();
-  void   op_cpy_b();
-  void   op_cpy_w();
-  void   op_eor_b();
-  void   op_eor_w();
-  void   op_lda_b();
-  void   op_lda_w();
-  void   op_ldx_b();
-  void   op_ldx_w();
-  void   op_ldy_b();
-  void   op_ldy_w();
-  void   op_ora_b();
-  void   op_ora_w();
-  void   op_sbc_b();
-  void   op_sbc_w();
-//op_rmw
-  void   op_inc_b();
-  void   op_inc_w();
-  void   op_dec_b();
-  void   op_dec_w();
-  void   op_asl_b();
-  void   op_asl_w();
-  void   op_lsr_b();
-  void   op_lsr_w();
-  void   op_rol_b();
-  void   op_rol_w();
-  void   op_ror_b();
-  void   op_ror_w();
-  void   op_trb_b();
-  void   op_trb_w();
-  void   op_tsb_b();
-  void   op_tsb_w();
-
-  void   op_io_cond2();
-  void   op_io_cond4(uint16 x, uint16 y);
-  void   op_io_cond6(uint16 addr);
-
-#include "op.h"
+  //op_read
+  void op_adc_b();
+  void op_adc_w();
+  void op_and_b();
+  void op_and_w();
+  void op_bit_b();
+  void op_bit_w();
+  void op_cmp_b();
+  void op_cmp_w();
+  void op_cpx_b();
+  void op_cpx_w();
+  void op_cpy_b();
+  void op_cpy_w();
+  void op_eor_b();
+  void op_eor_w();
+  void op_lda_b();
+  void op_lda_w();
+  void op_ldx_b();
+  void op_ldx_w();
+  void op_ldy_b();
+  void op_ldy_w();
+  void op_ora_b();
+  void op_ora_w();
+  void op_sbc_b();
+  void op_sbc_w();
+  //op_rmw
+  void op_inc_b();
+  void op_inc_w();
+  void op_dec_b();
+  void op_dec_w();
+  void op_asl_b();
+  void op_asl_w();
+  void op_lsr_b();
+  void op_lsr_w();
+  void op_rol_b();
+  void op_rol_w();
+  void op_ror_b();
+  void op_ror_w();
+  void op_trb_b();
+  void op_trb_w();
+  void op_tsb_b();
+  void op_tsb_w();
+
+  void op_io_irq();
+  void op_io_cond2();
+  void op_io_cond4(uint16 x, uint16 y);
+  void op_io_cond6(uint16 addr);

src/cpu/scpu/core/op.h

@@ -1,256 +0,0 @@
-void op_adc_const();
-void op_and_const();
-void op_cmp_const();
-void op_cpx_const();
-void op_cpy_const();
-void op_eor_const();
-void op_lda_const();
-void op_ldx_const();
-void op_ldy_const();
-void op_ora_const();
-void op_sbc_const();
-void op_adc_addr();
-void op_and_addr();
-void op_bit_addr();
-void op_cmp_addr();
-void op_cpx_addr();
-void op_cpy_addr();
-void op_eor_addr();
-void op_lda_addr();
-void op_ldx_addr();
-void op_ldy_addr();
-void op_ora_addr();
-void op_sbc_addr();
-void op_adc_addrx();
-void op_and_addrx();
-void op_bit_addrx();
-void op_cmp_addrx();
-void op_eor_addrx();
-void op_lda_addrx();
-void op_ldy_addrx();
-void op_ora_addrx();
-void op_sbc_addrx();
-void op_adc_addry();
-void op_and_addry();
-void op_cmp_addry();
-void op_eor_addry();
-void op_lda_addry();
-void op_ldx_addry();
-void op_ora_addry();
-void op_sbc_addry();
-void op_adc_long();
-void op_and_long();
-void op_cmp_long();
-void op_eor_long();
-void op_lda_long();
-void op_ora_long();
-void op_sbc_long();
-void op_adc_longx();
-void op_and_longx();
-void op_cmp_longx();
-void op_eor_longx();
-void op_lda_longx();
-void op_ora_longx();
-void op_sbc_longx();
-void op_adc_dp();
-void op_and_dp();
-void op_bit_dp();
-void op_cmp_dp();
-void op_cpx_dp();
-void op_cpy_dp();
-void op_eor_dp();
-void op_lda_dp();
-void op_ldx_dp();
-void op_ldy_dp();
-void op_ora_dp();
-void op_sbc_dp();
-void op_adc_dpx();
-void op_and_dpx();
-void op_bit_dpx();
-void op_cmp_dpx();
-void op_eor_dpx();
-void op_lda_dpx();
-void op_ldy_dpx();
-void op_ora_dpx();
-void op_sbc_dpx();
-void op_ldx_dpy();
-void op_adc_idp();
-void op_and_idp();
-void op_cmp_idp();
-void op_eor_idp();
-void op_lda_idp();
-void op_ora_idp();
-void op_sbc_idp();
-void op_adc_idpx();
-void op_and_idpx();
-void op_cmp_idpx();
-void op_eor_idpx();
-void op_lda_idpx();
-void op_ora_idpx();
-void op_sbc_idpx();
-void op_adc_idpy();
-void op_and_idpy();
-void op_cmp_idpy();
-void op_eor_idpy();
-void op_lda_idpy();
-void op_ora_idpy();
-void op_sbc_idpy();
-void op_adc_ildp();
-void op_and_ildp();
-void op_cmp_ildp();
-void op_eor_ildp();
-void op_lda_ildp();
-void op_ora_ildp();
-void op_sbc_ildp();
-void op_adc_ildpy();
-void op_and_ildpy();
-void op_cmp_ildpy();
-void op_eor_ildpy();
-void op_lda_ildpy();
-void op_ora_ildpy();
-void op_sbc_ildpy();
-void op_adc_sr();
-void op_and_sr();
-void op_cmp_sr();
-void op_eor_sr();
-void op_lda_sr();
-void op_ora_sr();
-void op_sbc_sr();
-void op_adc_isry();
-void op_and_isry();
-void op_cmp_isry();
-void op_eor_isry();
-void op_lda_isry();
-void op_ora_isry();
-void op_sbc_isry();
-void op_bit_const();
-void op_sta_addr();
-void op_stx_addr();
-void op_sty_addr();
-void op_stz_addr();
-void op_sta_addrx();
-void op_stz_addrx();
-void op_sta_addry();
-void op_sta_long();
-void op_sta_longx();
-void op_sta_dp();
-void op_stx_dp();
-void op_sty_dp();
-void op_stz_dp();
-void op_sta_dpx();
-void op_sty_dpx();
-void op_stz_dpx();
-void op_stx_dpy();
-void op_sta_idp();
-void op_sta_ildp();
-void op_sta_idpx();
-void op_sta_idpy();
-void op_sta_ildpy();
-void op_sta_sr();
-void op_sta_isry();
-void op_inc();
-void op_inx();
-void op_iny();
-void op_dec();
-void op_dex();
-void op_dey();
-void op_asl();
-void op_lsr();
-void op_rol();
-void op_ror();
-void op_inc_addr();
-void op_dec_addr();
-void op_asl_addr();
-void op_lsr_addr();
-void op_rol_addr();
-void op_ror_addr();
-void op_trb_addr();
-void op_tsb_addr();
-void op_inc_addrx();
-void op_dec_addrx();
-void op_asl_addrx();
-void op_lsr_addrx();
-void op_rol_addrx();
-void op_ror_addrx();
-void op_inc_dp();
-void op_dec_dp();
-void op_asl_dp();
-void op_lsr_dp();
-void op_rol_dp();
-void op_ror_dp();
-void op_trb_dp();
-void op_tsb_dp();
-void op_inc_dpx();
-void op_dec_dpx();
-void op_asl_dpx();
-void op_lsr_dpx();
-void op_rol_dpx();
-void op_ror_dpx();
-void op_bcc();
-void op_bcs();
-void op_bne();
-void op_beq();
-void op_bpl();
-void op_bmi();
-void op_bvc();
-void op_bvs();
-void op_bra();
-void op_brl();
-void op_jmp_addr();
-void op_jmp_long();
-void op_jmp_iaddr();
-void op_jmp_iaddrx();
-void op_jmp_iladdr();
-void op_jsr_addr();
-void op_jsr_long();
-void op_jsr_iaddrx();
-void op_rti();
-void op_rts();
-void op_rtl();
-void op_nop();
-void op_wdm();
-void op_xba();
-void op_mvn();
-void op_mvp();
-void op_brk();
-void op_cop();
-void op_stp();
-void op_wai();
-void op_xce();
-void op_clc();
-void op_cld();
-void op_cli();
-void op_clv();
-void op_sec();
-void op_sed();
-void op_sei();
-void op_rep();
-void op_sep();
-void op_tax();
-void op_tay();
-void op_txa();
-void op_txy();
-void op_tya();
-void op_tyx();
-void op_tcd();
-void op_tcs();
-void op_tdc();
-void op_tsc();
-void op_tsx();
-void op_txs();
-void op_pha();
-void op_phx();
-void op_phy();
-void op_phd();
-void op_phb();
-void op_phk();
-void op_php();
-void op_pla();
-void op_plx();
-void op_ply();
-void op_pld();
-void op_plb();
-void op_plp();
-void op_pea();
-void op_pei();
-void op_per();

src/cpu/scpu/core/op_misc.b

@@ -1,6 +1,6 @@
 nop(0xea) {
-1:last_cycle();
-  op_io();
+1:last_cycle();
+  op_io_irq();
 }
 
 wdm(0x42) {
@@ -36,34 +36,33 @@ mvp(0x44, --) {
   }
 6:last_cycle();
   op_io();
-  if(regs.a.w--)regs.pc.w -= 3;
+  if(regs.a.w--) regs.pc.w -= 3;
 }
 
 brk(0x00, 0xfffe, 0xffff, 0xffe6, 0xffe7),
 cop(0x02, 0xfff4, 0xfff5, 0xffe4, 0xffe5) {
 1:op_readpc();
-2:if(!regs.e)op_writestack(regs.pc.b);
+2:if(!regs.e) op_writestack(regs.pc.b);
 3:op_writestack(regs.pc.h);
 4:op_writestack(regs.pc.l);
 5:op_writestack(regs.p);
-6:rd.l = op_readlong((regs.e) ? $1 : $3);
+6:rd.l = op_readlong(regs.e ? $1 : $3);
   regs.pc.b = 0x00;
   regs.p.i  = 1;
   regs.p.d  = 0;
 7:last_cycle();
-  rd.h = op_readlong((regs.e) ? $2 : $4);
+  rd.h = op_readlong(regs.e ? $2 : $4);
   regs.pc.w = rd.w;
 }
 
 stp(0xdb) {
 1:op_io();
 2:last_cycle();
-  while(1) { op_io(); }
+  while(true) op_io();
 }
 
 wai(0xcb) {
-//last_cycle() will set event.wai to false
-//once an NMI / IRQ edge is reached
+//last_cycle() will clear event.wai once an NMI / IRQ edge is reached
 1:event.wai = true;
   while(event.wai) {
     last_cycle();
@@ -73,9 +72,9 @@ wai(0xcb) {
 }
 
 xce(0xfb) {
-1:last_cycle();
-  op_io();
-bool carry = regs.p.c;
+1:last_cycle();
+  op_io_irq();
+  bool carry = regs.p.c;
   regs.p.c = regs.e;
   regs.e = carry;
   if(regs.e) {
@@ -96,7 +95,7 @@ sec(0x38, regs.p.c = 1),
 sed(0xf8, regs.p.d = 1),
 sei(0x78, regs.p.i = 1) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   $1;
 }
 
@@ -106,7 +105,7 @@ sep(0xe2, |=) {
 2:last_cycle();
   op_io();
   regs.p $1 rd.l;
-  if(regs.e)regs.p |= 0x30;
+  if(regs.e) regs.p |= 0x30;
   if(regs.p.x) {
     regs.x.h = 0x00;
     regs.y.h = 0x00;
@@ -120,7 +119,7 @@ txy(0x9b, regs.p.x, y, x),
 tya(0x98, regs.p.m, a, y),
 tyx(0xbb, regs.p.x, x, y) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   if($1) {
     regs.$2.l = regs.$3.l;
     regs.p.n = !!(regs.$2.l & 0x80);
@@ -134,7 +133,7 @@ tyx(0xbb, regs.p.x, x, y) {
 
 tcd(0x5b) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   regs.d.w = regs.a.w;
   regs.p.n = !!(regs.d.w & 0x8000);
   regs.p.z = (regs.d.w == 0);
@@ -142,14 +141,14 @@ tcd(0x5b) {
 
 tcs(0x1b) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   regs.s.w = regs.a.w;
-  if(regs.e)regs.s.h = 0x01;
+  if(regs.e) regs.s.h = 0x01;
 }
 
 tdc(0x7b) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   regs.a.w = regs.d.w;
   regs.p.n = !!(regs.a.w & 0x8000);
   regs.p.z = (regs.a.w == 0);
@@ -157,7 +156,7 @@ tdc(0x7b) {
 
 tsc(0x3b) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   regs.a.w = regs.s.w;
   if(regs.e) {
     regs.p.n = !!(regs.a.l & 0x80);
@@ -170,7 +169,7 @@ tsc(0x3b) {
 
 tsx(0xba) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.x.l = regs.s.l;
     regs.p.n = !!(regs.x.l & 0x80);
@@ -184,7 +183,7 @@ tsx(0xba) {
 
 txs(0x9a) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.e) {
     regs.s.l = regs.x.l;
   } else {
@@ -206,7 +205,7 @@ phd(0x0b) {
 2:op_writestackn(regs.d.h);
 3:last_cycle();
   op_writestackn(regs.d.l);
-  if(regs.e)regs.s.h = 0x01;
+  if(regs.e) regs.s.h = 0x01;
 }
 
 phb(0x8b, regs.db),
@@ -243,7 +242,7 @@ pld(0x2b) {
   regs.d.h = op_readstackn();
   regs.p.n = !!(regs.d.w & 0x8000);
   regs.p.z = (regs.d.w == 0);
-  if(regs.e)regs.s.h = 0x01;
+  if(regs.e) regs.s.h = 0x01;
 }
 
 plb(0xab) {
@@ -260,7 +259,7 @@ plp(0x28) {
 2:op_io();
 3:last_cycle();
   regs.p = op_readstack();
-  if(regs.e)regs.p |= 0x30;
+  if(regs.e) regs.p |= 0x30;
   if(regs.p.x) {
     regs.x.h = 0x00;
     regs.y.h = 0x00;
@@ -273,7 +272,7 @@ pea(0xf4) {
 3:op_writestackn(aa.h);
 4:last_cycle();
   op_writestackn(aa.l);
-  if(regs.e)regs.s.h = 0x01;
+  if(regs.e) regs.s.h = 0x01;
 }
 
 pei(0xd4) {
@@ -284,7 +283,7 @@ pei(0xd4) {
 5:op_writestackn(aa.h);
 6:last_cycle();
   op_writestackn(aa.l);
-  if(regs.e)regs.s.h = 0x01;
+  if(regs.e) regs.s.h = 0x01;
 }
 
 per(0x62) {
@@ -295,5 +294,5 @@ per(0x62) {
 4:op_writestackn(rd.h);
 5:last_cycle();
   op_writestackn(rd.l);
-  if(regs.e)regs.s.h = 0x01;
+  if(regs.e) regs.s.h = 0x01;
 }

src/cpu/scpu/core/op_misc.cpp

@@ -1,14 +1,17 @@
-void sCPU::op_nop() {
+//nop
+case 0xea: {
   last_cycle();
-  op_io();
-}
+  op_io_irq();
+} break;
 
-void sCPU::op_wdm() {
+//wdm
+case 0x42: {
   last_cycle();
   op_readpc();
-}
+} break;
 
-void sCPU::op_xba() {
+//xba
+case 0xeb: {
   op_io();
   last_cycle();
   op_io();
@@ -17,9 +20,10 @@ void sCPU::op_xba() {
   regs.a.l ^= regs.a.h;
   regs.p.n = !!(regs.a.l & 0x80);
   regs.p.z = (regs.a.l == 0);
-}
+} break;
 
-void sCPU::op_mvn() {
+//mvn
+case 0x54: {
   dp = op_readpc();
   sp = op_readpc();
   regs.db = dp;
@@ -35,10 +39,11 @@ void sCPU::op_mvn() {
   }
   last_cycle();
   op_io();
-  if(regs.a.w--)regs.pc.w -= 3;
-}
+  if(regs.a.w--) regs.pc.w -= 3;
+} break;
 
-void sCPU::op_mvp() {
+//mvp
+case 0x44: {
   dp = op_readpc();
   sp = op_readpc();
   regs.db = dp;
@@ -54,60 +59,64 @@ void sCPU::op_mvp() {
   }
   last_cycle();
   op_io();
-  if(regs.a.w--)regs.pc.w -= 3;
-}
+  if(regs.a.w--) regs.pc.w -= 3;
+} break;
 
-void sCPU::op_brk() {
+//brk
+case 0x00: {
   op_readpc();
-  if(!regs.e)op_writestack(regs.pc.b);
+  if(!regs.e) op_writestack(regs.pc.b);
   op_writestack(regs.pc.h);
   op_writestack(regs.pc.l);
   op_writestack(regs.p);
-  rd.l = op_readlong((regs.e) ? 0xfffe : 0xffe6);
+  rd.l = op_readlong(regs.e ? 0xfffe : 0xffe6);
   regs.pc.b = 0x00;
   regs.p.i  = 1;
   regs.p.d  = 0;
   last_cycle();
-  rd.h = op_readlong((regs.e) ? 0xffff : 0xffe7);
+  rd.h = op_readlong(regs.e ? 0xffff : 0xffe7);
   regs.pc.w = rd.w;
-}
+} break;
 
-void sCPU::op_cop() {
+//cop
+case 0x02: {
   op_readpc();
-  if(!regs.e)op_writestack(regs.pc.b);
+  if(!regs.e) op_writestack(regs.pc.b);
   op_writestack(regs.pc.h);
   op_writestack(regs.pc.l);
   op_writestack(regs.p);
-  rd.l = op_readlong((regs.e) ? 0xfff4 : 0xffe4);
+  rd.l = op_readlong(regs.e ? 0xfff4 : 0xffe4);
   regs.pc.b = 0x00;
   regs.p.i  = 1;
   regs.p.d  = 0;
   last_cycle();
-  rd.h = op_readlong((regs.e) ? 0xfff5 : 0xffe5);
+  rd.h = op_readlong(regs.e ? 0xfff5 : 0xffe5);
   regs.pc.w = rd.w;
-}
+} break;
 
-void sCPU::op_stp() {
+//stp
+case 0xdb: {
   op_io();
   last_cycle();
-  while(1) { op_io(); }
-}
+  while(true) op_io();
+} break;
 
-void sCPU::op_wai() {
-  //last_cycle() will set event.wai to false
-//once an NMI / IRQ edge is reached
+//wai
+case 0xcb: {
+  //last_cycle() will clear event.wai once an NMI / IRQ edge is reached
   event.wai = true;
   while(event.wai) {
     last_cycle();
     op_io();
   }
   op_io();
-}
+} break;
 
-void sCPU::op_xce() {
+//xce
+case 0xfb: {
   last_cycle();
-  op_io();
-bool carry = regs.p.c;
+  op_io_irq();
+  bool carry = regs.p.c;
   regs.p.c = regs.e;
   regs.e = carry;
   if(regs.e) {
@@ -118,77 +127,87 @@ bool carry = regs.p.c;
     regs.x.h = 0x00;
     regs.y.h = 0x00;
   }
-}
+} break;
 
-void sCPU::op_clc() {
+//clc
+case 0x18: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.p.c = 0;
-}
+} break;
 
-void sCPU::op_cld() {
+//cld
+case 0xd8: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.p.d = 0;
-}
+} break;
 
-void sCPU::op_cli() {
+//cli
+case 0x58: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.p.i = 0;
-}
+} break;
 
-void sCPU::op_clv() {
+//clv
+case 0xb8: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.p.v = 0;
-}
+} break;
 
-void sCPU::op_sec() {
+//sec
+case 0x38: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.p.c = 1;
-}
+} break;
 
-void sCPU::op_sed() {
+//sed
+case 0xf8: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.p.d = 1;
-}
+} break;
 
-void sCPU::op_sei() {
+//sei
+case 0x78: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.p.i = 1;
-}
+} break;
 
-void sCPU::op_rep() {
+//rep
+case 0xc2: {
   rd.l = op_readpc();
   last_cycle();
   op_io();
   regs.p &=~ rd.l;
-  if(regs.e)regs.p |= 0x30;
+  if(regs.e) regs.p |= 0x30;
   if(regs.p.x) {
     regs.x.h = 0x00;
     regs.y.h = 0x00;
   }
-}
+} break;
 
-void sCPU::op_sep() {
+//sep
+case 0xe2: {
   rd.l = op_readpc();
   last_cycle();
   op_io();
   regs.p |= rd.l;
-  if(regs.e)regs.p |= 0x30;
+  if(regs.e) regs.p |= 0x30;
   if(regs.p.x) {
     regs.x.h = 0x00;
     regs.y.h = 0x00;
   }
-}
+} break;
 
-void sCPU::op_tax() {
+//tax
+case 0xaa: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.x.l = regs.a.l;
     regs.p.n = !!(regs.x.l & 0x80);
@@ -198,11 +217,12 @@ void sCPU::op_tax() {
     regs.p.n = !!(regs.x.w & 0x8000);
     regs.p.z = (regs.x.w == 0);
   }
-}
+} break;
 
-void sCPU::op_tay() {
+//tay
+case 0xa8: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.y.l = regs.a.l;
     regs.p.n = !!(regs.y.l & 0x80);
@@ -212,11 +232,12 @@ void sCPU::op_tay() {
     regs.p.n = !!(regs.y.w & 0x8000);
     regs.p.z = (regs.y.w == 0);
   }
-}
+} break;
 
-void sCPU::op_txa() {
+//txa
+case 0x8a: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.m) {
     regs.a.l = regs.x.l;
     regs.p.n = !!(regs.a.l & 0x80);
@@ -226,11 +247,12 @@ void sCPU::op_txa() {
     regs.p.n = !!(regs.a.w & 0x8000);
     regs.p.z = (regs.a.w == 0);
   }
-}
+} break;
 
-void sCPU::op_txy() {
+//txy
+case 0x9b: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.y.l = regs.x.l;
     regs.p.n = !!(regs.y.l & 0x80);
@@ -240,11 +262,12 @@ void sCPU::op_txy() {
     regs.p.n = !!(regs.y.w & 0x8000);
     regs.p.z = (regs.y.w == 0);
   }
-}
+} break;
 
-void sCPU::op_tya() {
+//tya
+case 0x98: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.m) {
     regs.a.l = regs.y.l;
     regs.p.n = !!(regs.a.l & 0x80);
@@ -254,11 +277,12 @@ void sCPU::op_tya() {
     regs.p.n = !!(regs.a.w & 0x8000);
     regs.p.z = (regs.a.w == 0);
   }
-}
+} break;
 
-void sCPU::op_tyx() {
+//tyx
+case 0xbb: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.x.l = regs.y.l;
     regs.p.n = !!(regs.x.l & 0x80);
@@ -268,34 +292,38 @@ void sCPU::op_tyx() {
     regs.p.n = !!(regs.x.w & 0x8000);
     regs.p.z = (regs.x.w == 0);
   }
-}
+} break;
 
-void sCPU::op_tcd() {
+//tcd
+case 0x5b: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.d.w = regs.a.w;
   regs.p.n = !!(regs.d.w & 0x8000);
   regs.p.z = (regs.d.w == 0);
-}
+} break;
 
-void sCPU::op_tcs() {
+//tcs
+case 0x1b: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.s.w = regs.a.w;
-  if(regs.e)regs.s.h = 0x01;
-}
+  if(regs.e) regs.s.h = 0x01;
+} break;
 
-void sCPU::op_tdc() {
+//tdc
+case 0x7b: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.a.w = regs.d.w;
   regs.p.n = !!(regs.a.w & 0x8000);
   regs.p.z = (regs.a.w == 0);
-}
+} break;
 
-void sCPU::op_tsc() {
+//tsc
+case 0x3b: {
   last_cycle();
-  op_io();
+  op_io_irq();
   regs.a.w = regs.s.w;
   if(regs.e) {
     regs.p.n = !!(regs.a.l & 0x80);
@@ -304,11 +332,12 @@ void sCPU::op_tsc() {
     regs.p.n = !!(regs.a.w & 0x8000);
     regs.p.z = (regs.a.w == 0);
   }
-}
+} break;
 
-void sCPU::op_tsx() {
+//tsx
+case 0xba: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.x.l = regs.s.l;
     regs.p.n = !!(regs.x.l & 0x80);
@@ -318,66 +347,75 @@ void sCPU::op_tsx() {
     regs.p.n = !!(regs.x.w & 0x8000);
     regs.p.z = (regs.x.w == 0);
   }
-}
+} break;
 
-void sCPU::op_txs() {
+//txs
+case 0x9a: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.e) {
     regs.s.l = regs.x.l;
   } else {
     regs.s.w = regs.x.w;
   }
-}
+} break;
 
-void sCPU::op_pha() {
+//pha
+case 0x48: {
   op_io();
   if(!regs.p.m)op_writestack(regs.a.h);
   last_cycle();
   op_writestack(regs.a.l);
-}
+} break;
 
-void sCPU::op_phx() {
+//phx
+case 0xda: {
   op_io();
   if(!regs.p.x)op_writestack(regs.x.h);
   last_cycle();
   op_writestack(regs.x.l);
-}
+} break;
 
-void sCPU::op_phy() {
+//phy
+case 0x5a: {
   op_io();
   if(!regs.p.x)op_writestack(regs.y.h);
   last_cycle();
   op_writestack(regs.y.l);
-}
+} break;
 
-void sCPU::op_phd() {
+//phd
+case 0x0b: {
   op_io();
   op_writestackn(regs.d.h);
   last_cycle();
   op_writestackn(regs.d.l);
-  if(regs.e)regs.s.h = 0x01;
-}
+  if(regs.e) regs.s.h = 0x01;
+} break;
 
-void sCPU::op_phb() {
+//phb
+case 0x8b: {
   op_io();
   last_cycle();
   op_writestack(regs.db);
-}
+} break;
 
-void sCPU::op_phk() {
+//phk
+case 0x4b: {
   op_io();
   last_cycle();
   op_writestack(regs.pc.b);
-}
+} break;
 
-void sCPU::op_php() {
+//php
+case 0x08: {
   op_io();
   last_cycle();
   op_writestack(regs.p);
-}
+} break;
 
-void sCPU::op_pla() {
+//pla
+case 0x68: {
   op_io();
   op_io();
   if(regs.p.m)last_cycle();
@@ -385,15 +423,16 @@ void sCPU::op_pla() {
   if(regs.p.m) {
     regs.p.n = !!(regs.a.l & 0x80);
     regs.p.z = (regs.a.l == 0);
-    return;
+    break;
   }
   last_cycle();
   regs.a.h = op_readstack();
   regs.p.n = !!(regs.a.w & 0x8000);
   regs.p.z = (regs.a.w == 0);
-}
+} break;
 
-void sCPU::op_plx() {
+//plx
+case 0xfa: {
   op_io();
   op_io();
   if(regs.p.x)last_cycle();
@@ -401,15 +440,16 @@ void sCPU::op_plx() {
   if(regs.p.x) {
     regs.p.n = !!(regs.x.l & 0x80);
     regs.p.z = (regs.x.l == 0);
-    return;
+    break;
   }
   last_cycle();
   regs.x.h = op_readstack();
   regs.p.n = !!(regs.x.w & 0x8000);
   regs.p.z = (regs.x.w == 0);
-}
+} break;
 
-void sCPU::op_ply() {
+//ply
+case 0x7a: {
   op_io();
   op_io();
   if(regs.p.x)last_cycle();
@@ -417,15 +457,16 @@ void sCPU::op_ply() {
   if(regs.p.x) {
     regs.p.n = !!(regs.y.l & 0x80);
     regs.p.z = (regs.y.l == 0);
-    return;
+    break;
   }
   last_cycle();
   regs.y.h = op_readstack();
   regs.p.n = !!(regs.y.w & 0x8000);
   regs.p.z = (regs.y.w == 0);
-}
+} break;
 
-void sCPU::op_pld() {
+//pld
+case 0x2b: {
   op_io();
   op_io();
   regs.d.l = op_readstackn();
@@ -433,40 +474,44 @@ void sCPU::op_pld() {
   regs.d.h = op_readstackn();
   regs.p.n = !!(regs.d.w & 0x8000);
   regs.p.z = (regs.d.w == 0);
-  if(regs.e)regs.s.h = 0x01;
-}
+  if(regs.e) regs.s.h = 0x01;
+} break;
 
-void sCPU::op_plb() {
+//plb
+case 0xab: {
   op_io();
   op_io();
   last_cycle();
   regs.db = op_readstack();
   regs.p.n = !!(regs.db & 0x80);
   regs.p.z = (regs.db == 0);
-}
+} break;
 
-void sCPU::op_plp() {
+//plp
+case 0x28: {
   op_io();
   op_io();
   last_cycle();
   regs.p = op_readstack();
-  if(regs.e)regs.p |= 0x30;
+  if(regs.e) regs.p |= 0x30;
   if(regs.p.x) {
     regs.x.h = 0x00;
     regs.y.h = 0x00;
   }
-}
+} break;
 
-void sCPU::op_pea() {
+//pea
+case 0xf4: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_writestackn(aa.h);
   last_cycle();
   op_writestackn(aa.l);
-  if(regs.e)regs.s.h = 0x01;
-}
+  if(regs.e) regs.s.h = 0x01;
+} break;
 
-void sCPU::op_pei() {
+//pei
+case 0xd4: {
   dp = op_readpc();
   op_io_cond2();
   aa.l = op_readdp(dp);
@@ -474,10 +519,11 @@ void sCPU::op_pei() {
   op_writestackn(aa.h);
   last_cycle();
   op_writestackn(aa.l);
-  if(regs.e)regs.s.h = 0x01;
-}
+  if(regs.e) regs.s.h = 0x01;
+} break;
 
-void sCPU::op_per() {
+//per
+case 0x62: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
@@ -485,6 +531,6 @@ void sCPU::op_per() {
   op_writestackn(rd.h);
   last_cycle();
   op_writestackn(rd.l);
-  if(regs.e)regs.s.h = 0x01;
-}
+  if(regs.e) regs.s.h = 0x01;
+} break;
 

src/cpu/scpu/core/op_pc.b

@@ -6,7 +6,7 @@ bpl(0x10, !regs.p.n),
 bmi(0x30, regs.p.n),
 bvc(0x50, !regs.p.v),
 bvs(0x70, regs.p.v) {
-1:if(!$1)last_cycle();
+1:if(!$1) last_cycle();
   rd.l = op_readpc();
   if($1) {
     aa.w = regs.pc.d + (int8)rd.l;
@@ -102,7 +102,7 @@ jsr_long(0x22) {
 7:last_cycle();
   op_writestackn(regs.pc.l);
   regs.pc.d = aa.d & 0xffffff;
-  if(regs.e)regs.s.h = 0x01;
+  if(regs.e) regs.s.h = 0x01;
 }
 
 jsr_iaddrx(0xfc) {
@@ -115,20 +115,20 @@ jsr_iaddrx(0xfc) {
 7:last_cycle();
   rd.h = op_readpbr(aa.w + regs.x.w + 1);
   regs.pc.w = rd.w;
-  if(regs.e)regs.s.h = 0x01;
+  if(regs.e) regs.s.h = 0x01;
 }
 
 rti(0x40) {
 1:op_io();
 2:op_io();
 3:regs.p = op_readstack();
-  if(regs.e)regs.p |= 0x30;
+  if(regs.e) regs.p |= 0x30;
   if(regs.p.x) {
     regs.x.h = 0x00;
     regs.y.h = 0x00;
   }
 4:rd.l = op_readstack();
-5:if(regs.e)last_cycle();
+5:if(regs.e) last_cycle();
   rd.h = op_readstack();
   if(regs.e) {
     regs.pc.w = rd.w;
@@ -159,5 +159,5 @@ rtl(0x6b) {
   rd.b = op_readstackn();
   regs.pc.d = rd.d & 0xffffff;
   regs.pc.w++;
-  if(regs.e)regs.s.h = 0x01;
+  if(regs.e) regs.s.h = 0x01;
 }

src/cpu/scpu/core/op_pc.cpp

@@ -1,157 +1,171 @@
-void sCPU::op_bcc() {
-  if(!!regs.p.c)last_cycle();
+//bcc
+case 0x90: {
+  if(!!regs.p.c) last_cycle();
   rd.l = op_readpc();
   if(!regs.p.c) {
     aa.w = regs.pc.d + (int8)rd.l;
     regs.pc.w = aa.w;
   } else {
-    return;
+    break;
   }
   op_io_cond6(aa.w);
   last_cycle();
   op_io();
-}
+} break;
 
-void sCPU::op_bcs() {
-  if(!regs.p.c)last_cycle();
+//bcs
+case 0xb0: {
+  if(!regs.p.c) last_cycle();
   rd.l = op_readpc();
   if(regs.p.c) {
     aa.w = regs.pc.d + (int8)rd.l;
     regs.pc.w = aa.w;
   } else {
-    return;
+    break;
   }
   op_io_cond6(aa.w);
   last_cycle();
   op_io();
-}
+} break;
 
-void sCPU::op_bne() {
-  if(!!regs.p.z)last_cycle();
+//bne
+case 0xd0: {
+  if(!!regs.p.z) last_cycle();
   rd.l = op_readpc();
   if(!regs.p.z) {
     aa.w = regs.pc.d + (int8)rd.l;
     regs.pc.w = aa.w;
   } else {
-    return;
+    break;
   }
   op_io_cond6(aa.w);
   last_cycle();
   op_io();
-}
+} break;
 
-void sCPU::op_beq() {
-  if(!regs.p.z)last_cycle();
+//beq
+case 0xf0: {
+  if(!regs.p.z) last_cycle();
   rd.l = op_readpc();
   if(regs.p.z) {
     aa.w = regs.pc.d + (int8)rd.l;
     regs.pc.w = aa.w;
   } else {
-    return;
+    break;
   }
   op_io_cond6(aa.w);
   last_cycle();
   op_io();
-}
+} break;
 
-void sCPU::op_bpl() {
-  if(!!regs.p.n)last_cycle();
+//bpl
+case 0x10: {
+  if(!!regs.p.n) last_cycle();
   rd.l = op_readpc();
   if(!regs.p.n) {
     aa.w = regs.pc.d + (int8)rd.l;
     regs.pc.w = aa.w;
   } else {
-    return;
+    break;
   }
   op_io_cond6(aa.w);
   last_cycle();
   op_io();
-}
+} break;
 
-void sCPU::op_bmi() {
-  if(!regs.p.n)last_cycle();
+//bmi
+case 0x30: {
+  if(!regs.p.n) last_cycle();
   rd.l = op_readpc();
   if(regs.p.n) {
     aa.w = regs.pc.d + (int8)rd.l;
     regs.pc.w = aa.w;
   } else {
-    return;
+    break;
   }
   op_io_cond6(aa.w);
   last_cycle();
   op_io();
-}
+} break;
 
-void sCPU::op_bvc() {
-  if(!!regs.p.v)last_cycle();
+//bvc
+case 0x50: {
+  if(!!regs.p.v) last_cycle();
   rd.l = op_readpc();
   if(!regs.p.v) {
     aa.w = regs.pc.d + (int8)rd.l;
     regs.pc.w = aa.w;
   } else {
-    return;
+    break;
   }
   op_io_cond6(aa.w);
   last_cycle();
   op_io();
-}
+} break;
 
-void sCPU::op_bvs() {
-  if(!regs.p.v)last_cycle();
+//bvs
+case 0x70: {
+  if(!regs.p.v) last_cycle();
   rd.l = op_readpc();
   if(regs.p.v) {
     aa.w = regs.pc.d + (int8)rd.l;
     regs.pc.w = aa.w;
   } else {
-    return;
+    break;
   }
   op_io_cond6(aa.w);
   last_cycle();
   op_io();
-}
+} break;
 
-void sCPU::op_bra() {
+//bra
+case 0x80: {
   rd.l = op_readpc();
   aa.w = regs.pc.d + (int8)rd.l;
   regs.pc.w = aa.w;
   op_io_cond6(aa.w);
   last_cycle();
   op_io();
-}
+} break;
 
-void sCPU::op_brl() {
+//brl
+case 0x82: {
   rd.l = op_readpc();
   rd.h = op_readpc();
   last_cycle();
   op_io();
   regs.pc.w = regs.pc.d + (int16)rd.w;
-}
+} break;
 
-void sCPU::op_jmp_addr() {
+//jmp_addr
+case 0x4c: {
   rd.l = op_readpc();
   last_cycle();
   rd.h = op_readpc();
   regs.pc.w = rd.w;
-}
+} break;
 
-void sCPU::op_jmp_long() {
+//jmp_long
+case 0x5c: {
   rd.l = op_readpc();
   rd.h = op_readpc();
   last_cycle();
   rd.b = op_readpc();
   regs.pc.d = rd.d & 0xffffff;
-}
+} break;
 
-void sCPU::op_jmp_iaddr() {
+//jmp_iaddr
+case 0x6c: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readaddr(aa.w);
   last_cycle();
   rd.h = op_readaddr(aa.w + 1);
   regs.pc.w = rd.w;
-}
+} break;
 
-void sCPU::op_jmp_iaddrx() {
+//jmp_iaddrx
+case 0x7c: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
@@ -159,9 +173,10 @@ void sCPU::op_jmp_iaddrx() {
   last_cycle();
   rd.h = op_readpbr(aa.w + regs.x.w + 1);
   regs.pc.w = rd.w;
-}
+} break;
 
-void sCPU::op_jmp_iladdr() {
+//jmp_iladdr
+case 0xdc: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readaddr(aa.w);
@@ -169,9 +184,10 @@ void sCPU::op_jmp_iladdr() {
   last_cycle();
   rd.b = op_readaddr(aa.w + 2);
   regs.pc.d = rd.d & 0xffffff;
-}
+} break;
 
-void sCPU::op_jsr_addr() {
+//jsr_addr
+case 0x20: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
@@ -180,9 +196,10 @@ void sCPU::op_jsr_addr() {
   last_cycle();
   op_writestack(regs.pc.l);
   regs.pc.w = aa.w;
-}
+} break;
 
-void sCPU::op_jsr_long() {
+//jsr_long
+case 0x22: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_writestackn(regs.pc.b);
@@ -193,10 +210,11 @@ void sCPU::op_jsr_long() {
   last_cycle();
   op_writestackn(regs.pc.l);
   regs.pc.d = aa.d & 0xffffff;
-  if(regs.e)regs.s.h = 0x01;
-}
+  if(regs.e) regs.s.h = 0x01;
+} break;
 
-void sCPU::op_jsr_iaddrx() {
+//jsr_iaddrx
+case 0xfc: {
   aa.l = op_readpc();
   op_writestackn(regs.pc.h);
   op_writestackn(regs.pc.l);
@@ -206,31 +224,33 @@ void sCPU::op_jsr_iaddrx() {
   last_cycle();
   rd.h = op_readpbr(aa.w + regs.x.w + 1);
   regs.pc.w = rd.w;
-  if(regs.e)regs.s.h = 0x01;
-}
+  if(regs.e) regs.s.h = 0x01;
+} break;
 
-void sCPU::op_rti() {
+//rti
+case 0x40: {
   op_io();
   op_io();
   regs.p = op_readstack();
-  if(regs.e)regs.p |= 0x30;
+  if(regs.e) regs.p |= 0x30;
   if(regs.p.x) {
     regs.x.h = 0x00;
     regs.y.h = 0x00;
   }
   rd.l = op_readstack();
-  if(regs.e)last_cycle();
+  if(regs.e) last_cycle();
   rd.h = op_readstack();
   if(regs.e) {
     regs.pc.w = rd.w;
-    return;
+    break;
   }
   last_cycle();
   rd.b = op_readstack();
   regs.pc.d = rd.d & 0xffffff;
-}
+} break;
 
-void sCPU::op_rts() {
+//rts
+case 0x60: {
   op_io();
   op_io();
   rd.l = op_readstack();
@@ -239,9 +259,10 @@ void sCPU::op_rts() {
   op_io();
   regs.pc.w = rd.w;
   regs.pc.w++;
-}
+} break;
 
-void sCPU::op_rtl() {
+//rtl
+case 0x6b: {
   op_io();
   op_io();
   rd.l = op_readstackn();
@@ -250,6 +271,6 @@ void sCPU::op_rtl() {
   rd.b = op_readstackn();
   regs.pc.d = rd.d & 0xffffff;
   regs.pc.w++;
-  if(regs.e)regs.s.h = 0x01;
-}
+  if(regs.e) regs.s.h = 0x01;
+} break;
 

src/cpu/scpu/core/op_read.b

@@ -9,7 +9,7 @@ ldx_const(0xa2, ldx, regs.p.x),
 ldy_const(0xa0, ldy, regs.p.x),
 ora_const(0x09, ora, regs.p.m),
 sbc_const(0xe9, sbc, regs.p.m) {
-1:if($2)last_cycle();
+1:if($2) last_cycle();
   rd.l = op_readpc();
   if($2) { op_$1_b(); end; }
 2:last_cycle();
@@ -31,7 +31,7 @@ ora_addr(0x0d, ora, regs.p.m),
 sbc_addr(0xed, sbc, regs.p.m) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
-3:if($2)last_cycle();
+3:if($2) last_cycle();
   rd.l = op_readdbr(aa.w);
   if($2) { op_$1_b(); end; }
 4:last_cycle();
@@ -51,7 +51,7 @@ sbc_addrx(0xfd, sbc, regs.p.m) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
 3:op_io_cond4(aa.w, aa.w + regs.x.w);
-4:if($2)last_cycle();
+4:if($2) last_cycle();
   rd.l = op_readdbr(aa.w + regs.x.w);
   if($2) { op_$1_b(); end; }
 5:last_cycle();
@@ -70,7 +70,7 @@ sbc_addry(0xf9, sbc, regs.p.m) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
 3:op_io_cond4(aa.w, aa.w + regs.y.w);
-4:if($2)last_cycle();
+4:if($2) last_cycle();
   rd.l = op_readdbr(aa.w + regs.y.w);
   if($2) { op_$1_b(); end; }
 5:last_cycle();
@@ -88,7 +88,7 @@ sbc_long(0xef, sbc, regs.p.m) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
 3:aa.b = op_readpc();
-4:if($2)last_cycle();
+4:if($2) last_cycle();
   rd.l = op_readlong(aa.d);
   if($2) { op_$1_b(); end; }
 5:last_cycle();
@@ -106,7 +106,7 @@ sbc_longx(0xff, sbc, regs.p.m) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
 3:aa.b = op_readpc();
-4:if($2)last_cycle();
+4:if($2) last_cycle();
   rd.l = op_readlong(aa.d + regs.x.w);
   if($2) { op_$1_b(); end; }
 5:last_cycle();
@@ -128,7 +128,7 @@ ora_dp(0x05, ora, regs.p.m),
 sbc_dp(0xe5, sbc, regs.p.m) {
 1:dp = op_readpc();
 2:op_io_cond2();
-3:if($2)last_cycle();
+3:if($2) last_cycle();
   rd.l = op_readdp(dp);
   if($2) { op_$1_b(); end; }
 4:last_cycle();
@@ -148,7 +148,7 @@ sbc_dpx(0xf5, sbc, regs.p.m) {
 1:dp = op_readpc();
 2:op_io_cond2();
 3:op_io();
-4:if($2)last_cycle();
+4:if($2) last_cycle();
   rd.l = op_readdp(dp + regs.x.w);
   if($2) { op_$1_b(); end; }
 5:last_cycle();
@@ -160,7 +160,7 @@ ldx_dpy(0xb6, ldx, regs.p.x) {
 1:dp = op_readpc();
 2:op_io_cond2();
 3:op_io();
-4:if($2)last_cycle();
+4:if($2) last_cycle();
   rd.l = op_readdp(dp + regs.y.w);
   if($2) { op_$1_b(); end; }
 5:last_cycle();
@@ -179,7 +179,7 @@ sbc_idp(0xf2, sbc, regs.p.m) {
 2:op_io_cond2();
 3:aa.l = op_readdp(dp);
 4:aa.h = op_readdp(dp + 1);
-5:if($2)last_cycle();
+5:if($2) last_cycle();
   rd.l = op_readdbr(aa.w);
   if($2) { op_$1_b(); end; }
 6:last_cycle();
@@ -199,7 +199,7 @@ sbc_idpx(0xe1, sbc, regs.p.m) {
 3:op_io();
 4:aa.l = op_readdp(dp + regs.x.w);
 5:aa.h = op_readdp(dp + regs.x.w + 1);
-6:if($2)last_cycle();
+6:if($2) last_cycle();
   rd.l = op_readdbr(aa.w);
   if($2) { op_$1_b(); end; }
 7:last_cycle();
@@ -219,7 +219,7 @@ sbc_idpy(0xf1, sbc, regs.p.m) {
 3:aa.l = op_readdp(dp);
 4:aa.h = op_readdp(dp + 1);
 5:op_io_cond4(aa.w, aa.w + regs.y.w);
-6:if($2)last_cycle();
+6:if($2) last_cycle();
   rd.l = op_readdbr(aa.w + regs.y.w);
   if($2) { op_$1_b(); end; }
 7:last_cycle();
@@ -239,7 +239,7 @@ sbc_ildp(0xe7, sbc, regs.p.m) {
 3:aa.l = op_readdp(dp);
 4:aa.h = op_readdp(dp + 1);
 5:aa.b = op_readdp(dp + 2);
-6:if($2)last_cycle();
+6:if($2) last_cycle();
   rd.l = op_readlong(aa.d);
   if($2) { op_$1_b(); end; }
 7:last_cycle();
@@ -259,7 +259,7 @@ sbc_ildpy(0xf7, sbc, regs.p.m) {
 3:aa.l = op_readdp(dp);
 4:aa.h = op_readdp(dp + 1);
 5:aa.b = op_readdp(dp + 2);
-6:if($2)last_cycle();
+6:if($2) last_cycle();
   rd.l = op_readlong(aa.d + regs.y.w);
   if($2) { op_$1_b(); end; }
 7:last_cycle();
@@ -276,7 +276,7 @@ ora_sr(0x03, ora, regs.p.m),
 sbc_sr(0xe3, sbc, regs.p.m) {
 1:sp = op_readpc();
 2:op_io();
-3:if($2)last_cycle();
+3:if($2) last_cycle();
   rd.l = op_readsp(sp);
   if($2) { op_$1_b(); end; }
 4:last_cycle();
@@ -296,7 +296,7 @@ sbc_isry(0xf3, sbc) {
 3:aa.l = op_readsp(sp);
 4:aa.h = op_readsp(sp + 1);
 5:op_io();
-6:if(regs.p.m)last_cycle();
+6:if(regs.p.m) last_cycle();
   rd.l = op_readdbr(aa.w + regs.y.w);
   if(regs.p.m) { op_$1_b(); end; }
 7:last_cycle();
@@ -305,7 +305,7 @@ sbc_isry(0xf3, sbc) {
 }
 
 bit_const(0x89) {
-1:if(regs.p.m)last_cycle();
+1:if(regs.p.m) last_cycle();
   rd.l = op_readpc();
   if(regs.p.m) {
     regs.p.z = ((rd.l & regs.a.l) == 0);

src/cpu/scpu/core/op_rmw.b

@@ -2,7 +2,7 @@ inc(0x1a, regs.p.m, a),
 inx(0xe8, regs.p.x, x),
 iny(0xc8, regs.p.x, y) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   if($1) {
     regs.$2.l++;
     regs.p.n = !!(regs.$2.l & 0x80);
@@ -18,7 +18,7 @@ dec(0x3a, regs.p.m, a),
 dex(0xca, regs.p.x, x),
 dey(0x88, regs.p.x, y) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   if($1) {
     regs.$2.l--;
     regs.p.n = !!(regs.$2.l & 0x80);
@@ -32,7 +32,7 @@ dey(0x88, regs.p.x, y) {
 
 asl(0x0a) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.m) {
     regs.p.c = !!(regs.a.l & 0x80);
     regs.a.l <<= 1;
@@ -48,7 +48,7 @@ asl(0x0a) {
 
 lsr(0x4a) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.m) {
     regs.p.c = regs.a.l & 1;
     regs.a.l >>= 1;
@@ -64,7 +64,7 @@ lsr(0x4a) {
 
 rol(0x2a) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   uint16 c = regs.p.c;
   if(regs.p.m) {
     regs.p.c = !!(regs.a.l & 0x80);
@@ -83,17 +83,17 @@ rol(0x2a) {
 
 ror(0x6a) {
 1:last_cycle();
-  op_io();
+  op_io_irq();
   uint16 c;
   if(regs.p.m) {
-    c = (regs.p.c)?0x80:0;
+    c = regs.p.c ? 0x80 : 0;
     regs.p.c = regs.a.l & 1;
     regs.a.l >>= 1;
     regs.a.l |= c;
     regs.p.n = !!(regs.a.l & 0x80);
     regs.p.z = (regs.a.l == 0);
   } else {
-    c = (regs.p.c)?0x8000:0;
+    c = regs.p.c ? 0x8000 : 0;
     regs.p.c = regs.a.w & 1;
     regs.a.w >>= 1;
     regs.a.w |= c;
@@ -113,7 +113,7 @@ tsb_addr(0x0c, tsb) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
 3:rd.l = op_readdbr(aa.w);
-4:if(!regs.p.m)rd.h = op_readdbr(aa.w + 1);
+4:if(!regs.p.m) rd.h = op_readdbr(aa.w + 1);
 5:op_io();
   if(regs.p.m) { op_$1_b(); }
   else { op_$1_w();
@@ -132,7 +132,7 @@ ror_addrx(0x7e, ror) {
 2:aa.h = op_readpc();
 3:op_io();
 4:rd.l = op_readdbr(aa.w + regs.x.w);
-5:if(!regs.p.m)rd.h = op_readdbr(aa.w + regs.x.w + 1);
+5:if(!regs.p.m) rd.h = op_readdbr(aa.w + regs.x.w + 1);
 6:op_io();
   if(regs.p.m) { op_$1_b(); }
   else { op_$1_w();
@@ -152,7 +152,7 @@ tsb_dp(0x04, tsb) {
 1:dp = op_readpc();
 2:op_io_cond2();
 3:rd.l = op_readdp(dp);
-4:if(!regs.p.m)rd.h = op_readdp(dp + 1);
+4:if(!regs.p.m) rd.h = op_readdp(dp + 1);
 5:op_io();
   if(regs.p.m) { op_$1_b(); }
   else { op_$1_w();
@@ -171,7 +171,7 @@ ror_dpx(0x76, ror) {
 2:op_io_cond2();
 3:op_io();
 4:rd.l = op_readdp(dp + regs.x.w);
-5:if(!regs.p.m)rd.h = op_readdp(dp + regs.x.w + 1);
+5:if(!regs.p.m) rd.h = op_readdp(dp + regs.x.w + 1);
 6:op_io();
   if(regs.p.m) { op_$1_b(); }
   else { op_$1_w();

src/cpu/scpu/core/op_rmw.cpp

@@ -1,6 +1,7 @@
-void sCPU::op_inc() {
+//inc
+case 0x1a: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.m) {
     regs.a.l++;
     regs.p.n = !!(regs.a.l & 0x80);
@@ -10,11 +11,12 @@ void sCPU::op_inc() {
     regs.p.n = !!(regs.a.w & 0x8000);
     regs.p.z = (regs.a.w == 0);
   }
-}
+} break;
 
-void sCPU::op_inx() {
+//inx
+case 0xe8: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.x.l++;
     regs.p.n = !!(regs.x.l & 0x80);
@@ -24,11 +26,12 @@ void sCPU::op_inx() {
     regs.p.n = !!(regs.x.w & 0x8000);
     regs.p.z = (regs.x.w == 0);
   }
-}
+} break;
 
-void sCPU::op_iny() {
+//iny
+case 0xc8: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.y.l++;
     regs.p.n = !!(regs.y.l & 0x80);
@@ -38,11 +41,12 @@ void sCPU::op_iny() {
     regs.p.n = !!(regs.y.w & 0x8000);
     regs.p.z = (regs.y.w == 0);
   }
-}
+} break;
 
-void sCPU::op_dec() {
+//dec
+case 0x3a: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.m) {
     regs.a.l--;
     regs.p.n = !!(regs.a.l & 0x80);
@@ -52,11 +56,12 @@ void sCPU::op_dec() {
     regs.p.n = !!(regs.a.w & 0x8000);
     regs.p.z = (regs.a.w == 0);
   }
-}
+} break;
 
-void sCPU::op_dex() {
+//dex
+case 0xca: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.x.l--;
     regs.p.n = !!(regs.x.l & 0x80);
@@ -66,11 +71,12 @@ void sCPU::op_dex() {
     regs.p.n = !!(regs.x.w & 0x8000);
     regs.p.z = (regs.x.w == 0);
   }
-}
+} break;
 
-void sCPU::op_dey() {
+//dey
+case 0x88: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.x) {
     regs.y.l--;
     regs.p.n = !!(regs.y.l & 0x80);
@@ -80,11 +86,12 @@ void sCPU::op_dey() {
     regs.p.n = !!(regs.y.w & 0x8000);
     regs.p.z = (regs.y.w == 0);
   }
-}
+} break;
 
-void sCPU::op_asl() {
+//asl
+case 0x0a: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.m) {
     regs.p.c = !!(regs.a.l & 0x80);
     regs.a.l <<= 1;
@@ -96,11 +103,12 @@ void sCPU::op_asl() {
     regs.p.n = !!(regs.a.w & 0x8000);
     regs.p.z = (regs.a.w == 0);
   }
-}
+} break;
 
-void sCPU::op_lsr() {
+//lsr
+case 0x4a: {
   last_cycle();
-  op_io();
+  op_io_irq();
   if(regs.p.m) {
     regs.p.c = regs.a.l & 1;
     regs.a.l >>= 1;
@@ -112,11 +120,12 @@ void sCPU::op_lsr() {
     regs.p.n = !!(regs.a.w & 0x8000);
     regs.p.z = (regs.a.w == 0);
   }
-}
+} break;
 
-void sCPU::op_rol() {
+//rol
+case 0x2a: {
   last_cycle();
-  op_io();
+  op_io_irq();
   uint16 c = regs.p.c;
   if(regs.p.m) {
     regs.p.c = !!(regs.a.l & 0x80);
@@ -131,402 +140,431 @@ void sCPU::op_rol() {
     regs.p.n = !!(regs.a.w & 0x8000);
     regs.p.z = (regs.a.w == 0);
   }
-}
+} break;
 
-void sCPU::op_ror() {
+//ror
+case 0x6a: {
   last_cycle();
-  op_io();
+  op_io_irq();
   uint16 c;
   if(regs.p.m) {
-    c = (regs.p.c)?0x80:0;
+    c = regs.p.c ? 0x80 : 0;
     regs.p.c = regs.a.l & 1;
     regs.a.l >>= 1;
     regs.a.l |= c;
     regs.p.n = !!(regs.a.l & 0x80);
     regs.p.z = (regs.a.l == 0);
   } else {
-    c = (regs.p.c)?0x8000:0;
+    c = regs.p.c ? 0x8000 : 0;
     regs.p.c = regs.a.w & 1;
     regs.a.w >>= 1;
     regs.a.w |= c;
     regs.p.n = !!(regs.a.w & 0x8000);
     regs.p.z = (regs.a.w == 0);
   }
-}
+} break;
 
-void sCPU::op_inc_addr() {
+//inc_addr
+case 0xee: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readdbr(aa.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + 1);
   op_io();
   if(regs.p.m) { op_inc_b(); }
   else { op_inc_w();
   op_writedbr(aa.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w,     rd.l);
-}
+} break;
 
-void sCPU::op_dec_addr() {
+//dec_addr
+case 0xce: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readdbr(aa.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + 1);
   op_io();
   if(regs.p.m) { op_dec_b(); }
   else { op_dec_w();
   op_writedbr(aa.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w,     rd.l);
-}
+} break;
 
-void sCPU::op_asl_addr() {
+//asl_addr
+case 0x0e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readdbr(aa.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + 1);
   op_io();
   if(regs.p.m) { op_asl_b(); }
   else { op_asl_w();
   op_writedbr(aa.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w,     rd.l);
-}
+} break;
 
-void sCPU::op_lsr_addr() {
+//lsr_addr
+case 0x4e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readdbr(aa.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + 1);
   op_io();
   if(regs.p.m) { op_lsr_b(); }
   else { op_lsr_w();
   op_writedbr(aa.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w,     rd.l);
-}
+} break;
 
-void sCPU::op_rol_addr() {
+//rol_addr
+case 0x2e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readdbr(aa.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + 1);
   op_io();
   if(regs.p.m) { op_rol_b(); }
   else { op_rol_w();
   op_writedbr(aa.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w,     rd.l);
-}
+} break;
 
-void sCPU::op_ror_addr() {
+//ror_addr
+case 0x6e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readdbr(aa.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + 1);
   op_io();
   if(regs.p.m) { op_ror_b(); }
   else { op_ror_w();
   op_writedbr(aa.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w,     rd.l);
-}
+} break;
 
-void sCPU::op_trb_addr() {
+//trb_addr
+case 0x1c: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readdbr(aa.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + 1);
   op_io();
   if(regs.p.m) { op_trb_b(); }
   else { op_trb_w();
   op_writedbr(aa.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w,     rd.l);
-}
+} break;
 
-void sCPU::op_tsb_addr() {
+//tsb_addr
+case 0x0c: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   rd.l = op_readdbr(aa.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + 1);
   op_io();
   if(regs.p.m) { op_tsb_b(); }
   else { op_tsb_w();
   op_writedbr(aa.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w,     rd.l);
-}
+} break;
 
-void sCPU::op_inc_addrx() {
+//inc_addrx
+case 0xfe: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
   rd.l = op_readdbr(aa.w + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_inc_b(); }
   else { op_inc_w();
   op_writedbr(aa.w + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_dec_addrx() {
+//dec_addrx
+case 0xde: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
   rd.l = op_readdbr(aa.w + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_dec_b(); }
   else { op_dec_w();
   op_writedbr(aa.w + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_asl_addrx() {
+//asl_addrx
+case 0x1e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
   rd.l = op_readdbr(aa.w + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_asl_b(); }
   else { op_asl_w();
   op_writedbr(aa.w + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_lsr_addrx() {
+//lsr_addrx
+case 0x5e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
   rd.l = op_readdbr(aa.w + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_lsr_b(); }
   else { op_lsr_w();
   op_writedbr(aa.w + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_rol_addrx() {
+//rol_addrx
+case 0x3e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
   rd.l = op_readdbr(aa.w + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_rol_b(); }
   else { op_rol_w();
   op_writedbr(aa.w + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_ror_addrx() {
+//ror_addrx
+case 0x7e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
   rd.l = op_readdbr(aa.w + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdbr(aa.w + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdbr(aa.w + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_ror_b(); }
   else { op_ror_w();
   op_writedbr(aa.w + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedbr(aa.w + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_inc_dp() {
+//inc_dp
+case 0xe6: {
   dp = op_readpc();
   op_io_cond2();
   rd.l = op_readdp(dp);
-  if(!regs.p.m)rd.h = op_readdp(dp + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + 1);
   op_io();
   if(regs.p.m) { op_inc_b(); }
   else { op_inc_w();
   op_writedp(dp + 1, rd.h); }
   last_cycle();
   op_writedp(dp,     rd.l);
-}
+} break;
 
-void sCPU::op_dec_dp() {
+//dec_dp
+case 0xc6: {
   dp = op_readpc();
   op_io_cond2();
   rd.l = op_readdp(dp);
-  if(!regs.p.m)rd.h = op_readdp(dp + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + 1);
   op_io();
   if(regs.p.m) { op_dec_b(); }
   else { op_dec_w();
   op_writedp(dp + 1, rd.h); }
   last_cycle();
   op_writedp(dp,     rd.l);
-}
+} break;
 
-void sCPU::op_asl_dp() {
+//asl_dp
+case 0x06: {
   dp = op_readpc();
   op_io_cond2();
   rd.l = op_readdp(dp);
-  if(!regs.p.m)rd.h = op_readdp(dp + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + 1);
   op_io();
   if(regs.p.m) { op_asl_b(); }
   else { op_asl_w();
   op_writedp(dp + 1, rd.h); }
   last_cycle();
   op_writedp(dp,     rd.l);
-}
+} break;
 
-void sCPU::op_lsr_dp() {
+//lsr_dp
+case 0x46: {
   dp = op_readpc();
   op_io_cond2();
   rd.l = op_readdp(dp);
-  if(!regs.p.m)rd.h = op_readdp(dp + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + 1);
   op_io();
   if(regs.p.m) { op_lsr_b(); }
   else { op_lsr_w();
   op_writedp(dp + 1, rd.h); }
   last_cycle();
   op_writedp(dp,     rd.l);
-}
+} break;
 
-void sCPU::op_rol_dp() {
+//rol_dp
+case 0x26: {
   dp = op_readpc();
   op_io_cond2();
   rd.l = op_readdp(dp);
-  if(!regs.p.m)rd.h = op_readdp(dp + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + 1);
   op_io();
   if(regs.p.m) { op_rol_b(); }
   else { op_rol_w();
   op_writedp(dp + 1, rd.h); }
   last_cycle();
   op_writedp(dp,     rd.l);
-}
+} break;
 
-void sCPU::op_ror_dp() {
+//ror_dp
+case 0x66: {
   dp = op_readpc();
   op_io_cond2();
   rd.l = op_readdp(dp);
-  if(!regs.p.m)rd.h = op_readdp(dp + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + 1);
   op_io();
   if(regs.p.m) { op_ror_b(); }
   else { op_ror_w();
   op_writedp(dp + 1, rd.h); }
   last_cycle();
   op_writedp(dp,     rd.l);
-}
+} break;
 
-void sCPU::op_trb_dp() {
+//trb_dp
+case 0x14: {
   dp = op_readpc();
   op_io_cond2();
   rd.l = op_readdp(dp);
-  if(!regs.p.m)rd.h = op_readdp(dp + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + 1);
   op_io();
   if(regs.p.m) { op_trb_b(); }
   else { op_trb_w();
   op_writedp(dp + 1, rd.h); }
   last_cycle();
   op_writedp(dp,     rd.l);
-}
+} break;
 
-void sCPU::op_tsb_dp() {
+//tsb_dp
+case 0x04: {
   dp = op_readpc();
   op_io_cond2();
   rd.l = op_readdp(dp);
-  if(!regs.p.m)rd.h = op_readdp(dp + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + 1);
   op_io();
   if(regs.p.m) { op_tsb_b(); }
   else { op_tsb_w();
   op_writedp(dp + 1, rd.h); }
   last_cycle();
   op_writedp(dp,     rd.l);
-}
+} break;
 
-void sCPU::op_inc_dpx() {
+//inc_dpx
+case 0xf6: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
   rd.l = op_readdp(dp + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdp(dp + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_inc_b(); }
   else { op_inc_w();
   op_writedp(dp + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedp(dp + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_dec_dpx() {
+//dec_dpx
+case 0xd6: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
   rd.l = op_readdp(dp + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdp(dp + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_dec_b(); }
   else { op_dec_w();
   op_writedp(dp + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedp(dp + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_asl_dpx() {
+//asl_dpx
+case 0x16: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
   rd.l = op_readdp(dp + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdp(dp + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_asl_b(); }
   else { op_asl_w();
   op_writedp(dp + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedp(dp + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_lsr_dpx() {
+//lsr_dpx
+case 0x56: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
   rd.l = op_readdp(dp + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdp(dp + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_lsr_b(); }
   else { op_lsr_w();
   op_writedp(dp + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedp(dp + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_rol_dpx() {
+//rol_dpx
+case 0x36: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
   rd.l = op_readdp(dp + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdp(dp + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_rol_b(); }
   else { op_rol_w();
   op_writedp(dp + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedp(dp + regs.x.w,     rd.l);
-}
+} break;
 
-void sCPU::op_ror_dpx() {
+//ror_dpx
+case 0x76: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
   rd.l = op_readdp(dp + regs.x.w);
-  if(!regs.p.m)rd.h = op_readdp(dp + regs.x.w + 1);
+  if(!regs.p.m) rd.h = op_readdp(dp + regs.x.w + 1);
   op_io();
   if(regs.p.m) { op_ror_b(); }
   else { op_ror_w();
   op_writedp(dp + regs.x.w + 1, rd.h); }
   last_cycle();
   op_writedp(dp + regs.x.w,     rd.l);
-}
+} break;
 

src/cpu/scpu/core/op_write.b

@@ -4,9 +4,9 @@ sty_addr(0x8c, regs.p.x, regs.y.w),
 stz_addr(0x9c, regs.p.m, 0x0000) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
-3:if($1)last_cycle();
+3:if($1) last_cycle();
   op_writedbr(aa.w,     $2);
-  if($1)end;
+  if($1) end;
 4:last_cycle();
   op_writedbr(aa.w + 1, $2 >> 8);
 }
@@ -16,9 +16,9 @@ stz_addrx(0x9e, regs.p.m, 0x0000) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
 3:op_io();
-4:if($1)last_cycle();
+4:if($1) last_cycle();
   op_writedbr(aa.w + regs.x.w,     $2);
-  if($1)end;
+  if($1) end;
 5:last_cycle();
   op_writedbr(aa.w + regs.x.w + 1, $2 >> 8);
 }
@@ -27,9 +27,9 @@ sta_addry(0x99) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
 3:op_io();
-4:if(regs.p.m)last_cycle();
+4:if(regs.p.m) last_cycle();
   op_writedbr(aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 5:last_cycle();
   op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
 }
@@ -38,9 +38,9 @@ sta_long(0x8f) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
 3:aa.b = op_readpc();
-4:if(regs.p.m)last_cycle();
+4:if(regs.p.m) last_cycle();
   op_writelong(aa.d,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 5:last_cycle();
   op_writelong(aa.d + 1, regs.a.h);
 }
@@ -49,9 +49,9 @@ sta_longx(0x9f) {
 1:aa.l = op_readpc();
 2:aa.h = op_readpc();
 3:aa.b = op_readpc();
-4:if(regs.p.m)last_cycle();
+4:if(regs.p.m) last_cycle();
   op_writelong(aa.d + regs.x.w,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 5:last_cycle();
   op_writelong(aa.d + regs.x.w + 1, regs.a.h);
 }
@@ -62,9 +62,9 @@ sty_dp(0x84, regs.p.x, regs.y.w),
 stz_dp(0x64, regs.p.m, 0x0000) {
 1:dp = op_readpc();
 2:op_io_cond2();
-3:if($1)last_cycle();
+3:if($1) last_cycle();
   op_writedp(dp,     $2);
-  if($1)end;
+  if($1) end;
 4:last_cycle();
   op_writedp(dp + 1, $2 >> 8);
 }
@@ -75,9 +75,9 @@ stz_dpx(0x74, regs.p.m, 0x0000) {
 1:dp = op_readpc();
 2:op_io_cond2();
 3:op_io();
-4:if($1)last_cycle();
+4:if($1) last_cycle();
   op_writedp(dp + regs.x.w,     $2);
-  if($1)end;
+  if($1) end;
 5:last_cycle();
   op_writedp(dp + regs.x.w + 1, $2 >> 8);
 }
@@ -86,9 +86,9 @@ stx_dpy(0x96) {
 1:dp = op_readpc();
 2:op_io_cond2();
 3:op_io();
-4:if(regs.p.x)last_cycle();
+4:if(regs.p.x) last_cycle();
   op_writedp(dp + regs.y.w,     regs.x.l);
-  if(regs.p.x)end;
+  if(regs.p.x) end;
 5:last_cycle();
   op_writedp(dp + regs.y.w + 1, regs.x.h);
 }
@@ -98,9 +98,9 @@ sta_idp(0x92) {
 2:op_io_cond2();
 3:aa.l = op_readdp(dp);
 4:aa.h = op_readdp(dp + 1);
-5:if(regs.p.m)last_cycle();
+5:if(regs.p.m) last_cycle();
   op_writedbr(aa.w,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 6:last_cycle();
   op_writedbr(aa.w + 1, regs.a.h);
 }
@@ -111,9 +111,9 @@ sta_ildp(0x87) {
 3:aa.l = op_readdp(dp);
 4:aa.h = op_readdp(dp + 1);
 5:aa.b = op_readdp(dp + 2);
-6:if(regs.p.m)last_cycle();
+6:if(regs.p.m) last_cycle();
   op_writelong(aa.d,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 7:last_cycle();
   op_writelong(aa.d + 1, regs.a.h);
 }
@@ -124,9 +124,9 @@ sta_idpx(0x81) {
 3:op_io();
 4:aa.l = op_readdp(dp + regs.x.w);
 5:aa.h = op_readdp(dp + regs.x.w + 1);
-6:if(regs.p.m)last_cycle();
+6:if(regs.p.m) last_cycle();
   op_writedbr(aa.w,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 7:last_cycle();
   op_writedbr(aa.w + 1, regs.a.h);
 }
@@ -137,9 +137,9 @@ sta_idpy(0x91) {
 3:aa.l = op_readdp(dp);
 4:aa.h = op_readdp(dp + 1);
 5:op_io();
-6:if(regs.p.m)last_cycle();
+6:if(regs.p.m) last_cycle();
   op_writedbr(aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 7:last_cycle();
   op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
 }
@@ -150,9 +150,9 @@ sta_ildpy(0x97) {
 3:aa.l = op_readdp(dp);
 4:aa.h = op_readdp(dp + 1);
 5:aa.b = op_readdp(dp + 2);
-6:if(regs.p.m)last_cycle();
+6:if(regs.p.m) last_cycle();
   op_writelong(aa.d + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 7:last_cycle();
   op_writelong(aa.d + regs.y.w + 1, regs.a.h);
 }
@@ -160,9 +160,9 @@ sta_ildpy(0x97) {
 sta_sr(0x83) {
 1:sp = op_readpc();
 2:op_io();
-3:if(regs.p.m)last_cycle();
+3:if(regs.p.m) last_cycle();
   op_writesp(sp,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 4:last_cycle();
   op_writesp(sp + 1, regs.a.h);
 }
@@ -173,9 +173,9 @@ sta_isry(0x93) {
 3:aa.l = op_readsp(sp);
 4:aa.h = op_readsp(sp + 1);
 5:op_io();
-6:if(regs.p.m)last_cycle();
+6:if(regs.p.m) last_cycle();
   op_writedbr(aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
+  if(regs.p.m) end;
 7:last_cycle();
   op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
 }

src/cpu/scpu/core/op_write.cpp

@@ -1,266 +1,290 @@
-void sCPU::op_sta_addr() {
+//sta_addr
+case 0x8d: {
   aa.l = op_readpc();
   aa.h = op_readpc();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedbr(aa.w,     regs.a.w);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedbr(aa.w + 1, regs.a.w >> 8);
-}
+} break;
 
-void sCPU::op_stx_addr() {
+//stx_addr
+case 0x8e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
-  if(regs.p.x)last_cycle();
+  if(regs.p.x) last_cycle();
   op_writedbr(aa.w,     regs.x.w);
-  if(regs.p.x)return;
+  if(regs.p.x) break;
   last_cycle();
   op_writedbr(aa.w + 1, regs.x.w >> 8);
-}
+} break;
 
-void sCPU::op_sty_addr() {
+//sty_addr
+case 0x8c: {
   aa.l = op_readpc();
   aa.h = op_readpc();
-  if(regs.p.x)last_cycle();
+  if(regs.p.x) last_cycle();
   op_writedbr(aa.w,     regs.y.w);
-  if(regs.p.x)return;
+  if(regs.p.x) break;
   last_cycle();
   op_writedbr(aa.w + 1, regs.y.w >> 8);
-}
+} break;
 
-void sCPU::op_stz_addr() {
+//stz_addr
+case 0x9c: {
   aa.l = op_readpc();
   aa.h = op_readpc();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedbr(aa.w,     0x0000);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedbr(aa.w + 1, 0x0000 >> 8);
-}
+} break;
 
-void sCPU::op_sta_addrx() {
+//sta_addrx
+case 0x9d: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedbr(aa.w + regs.x.w,     regs.a.w);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedbr(aa.w + regs.x.w + 1, regs.a.w >> 8);
-}
+} break;
 
-void sCPU::op_stz_addrx() {
+//stz_addrx
+case 0x9e: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedbr(aa.w + regs.x.w,     0x0000);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedbr(aa.w + regs.x.w + 1, 0x0000 >> 8);
-}
+} break;
 
-void sCPU::op_sta_addry() {
+//sta_addry
+case 0x99: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   op_io();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedbr(aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
-}
+} break;
 
-void sCPU::op_sta_long() {
+//sta_long
+case 0x8f: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   aa.b = op_readpc();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writelong(aa.d,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writelong(aa.d + 1, regs.a.h);
-}
+} break;
 
-void sCPU::op_sta_longx() {
+//sta_longx
+case 0x9f: {
   aa.l = op_readpc();
   aa.h = op_readpc();
   aa.b = op_readpc();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writelong(aa.d + regs.x.w,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writelong(aa.d + regs.x.w + 1, regs.a.h);
-}
+} break;
 
-void sCPU::op_sta_dp() {
+//sta_dp
+case 0x85: {
   dp = op_readpc();
   op_io_cond2();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedp(dp,     regs.a.w);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedp(dp + 1, regs.a.w >> 8);
-}
+} break;
 
-void sCPU::op_stx_dp() {
+//stx_dp
+case 0x86: {
   dp = op_readpc();
   op_io_cond2();
-  if(regs.p.x)last_cycle();
+  if(regs.p.x) last_cycle();
   op_writedp(dp,     regs.x.w);
-  if(regs.p.x)return;
+  if(regs.p.x) break;
   last_cycle();
   op_writedp(dp + 1, regs.x.w >> 8);
-}
+} break;
 
-void sCPU::op_sty_dp() {
+//sty_dp
+case 0x84: {
   dp = op_readpc();
   op_io_cond2();
-  if(regs.p.x)last_cycle();
+  if(regs.p.x) last_cycle();
   op_writedp(dp,     regs.y.w);
-  if(regs.p.x)return;
+  if(regs.p.x) break;
   last_cycle();
   op_writedp(dp + 1, regs.y.w >> 8);
-}
+} break;
 
-void sCPU::op_stz_dp() {
+//stz_dp
+case 0x64: {
   dp = op_readpc();
   op_io_cond2();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedp(dp,     0x0000);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedp(dp + 1, 0x0000 >> 8);
-}
+} break;
 
-void sCPU::op_sta_dpx() {
+//sta_dpx
+case 0x95: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedp(dp + regs.x.w,     regs.a.w);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedp(dp + regs.x.w + 1, regs.a.w >> 8);
-}
+} break;
 
-void sCPU::op_sty_dpx() {
+//sty_dpx
+case 0x94: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
-  if(regs.p.x)last_cycle();
+  if(regs.p.x) last_cycle();
   op_writedp(dp + regs.x.w,     regs.y.w);
-  if(regs.p.x)return;
+  if(regs.p.x) break;
   last_cycle();
   op_writedp(dp + regs.x.w + 1, regs.y.w >> 8);
-}
+} break;
 
-void sCPU::op_stz_dpx() {
+//stz_dpx
+case 0x74: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedp(dp + regs.x.w,     0x0000);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedp(dp + regs.x.w + 1, 0x0000 >> 8);
-}
+} break;
 
-void sCPU::op_stx_dpy() {
+//stx_dpy
+case 0x96: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
-  if(regs.p.x)last_cycle();
+  if(regs.p.x) last_cycle();
   op_writedp(dp + regs.y.w,     regs.x.l);
-  if(regs.p.x)return;
+  if(regs.p.x) break;
   last_cycle();
   op_writedp(dp + regs.y.w + 1, regs.x.h);
-}
+} break;
 
-void sCPU::op_sta_idp() {
+//sta_idp
+case 0x92: {
   dp = op_readpc();
   op_io_cond2();
   aa.l = op_readdp(dp);
   aa.h = op_readdp(dp + 1);
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedbr(aa.w,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedbr(aa.w + 1, regs.a.h);
-}
+} break;
 
-void sCPU::op_sta_ildp() {
+//sta_ildp
+case 0x87: {
   dp = op_readpc();
   op_io_cond2();
   aa.l = op_readdp(dp);
   aa.h = op_readdp(dp + 1);
   aa.b = op_readdp(dp + 2);
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writelong(aa.d,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writelong(aa.d + 1, regs.a.h);
-}
+} break;
 
-void sCPU::op_sta_idpx() {
+//sta_idpx
+case 0x81: {
   dp = op_readpc();
   op_io_cond2();
   op_io();
   aa.l = op_readdp(dp + regs.x.w);
   aa.h = op_readdp(dp + regs.x.w + 1);
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedbr(aa.w,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedbr(aa.w + 1, regs.a.h);
-}
+} break;
 
-void sCPU::op_sta_idpy() {
+//sta_idpy
+case 0x91: {
   dp = op_readpc();
   op_io_cond2();
   aa.l = op_readdp(dp);
   aa.h = op_readdp(dp + 1);
   op_io();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedbr(aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
-}
+} break;
 
-void sCPU::op_sta_ildpy() {
+//sta_ildpy
+case 0x97: {
   dp = op_readpc();
   op_io_cond2();
   aa.l = op_readdp(dp);
   aa.h = op_readdp(dp + 1);
   aa.b = op_readdp(dp + 2);
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writelong(aa.d + regs.y.w,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writelong(aa.d + regs.y.w + 1, regs.a.h);
-}
+} break;
 
-void sCPU::op_sta_sr() {
+//sta_sr
+case 0x83: {
   sp = op_readpc();
   op_io();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writesp(sp,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writesp(sp + 1, regs.a.h);
-}
+} break;
 
-void sCPU::op_sta_isry() {
+//sta_isry
+case 0x93: {
   sp = op_readpc();
   op_io();
   aa.l = op_readsp(sp);
   aa.h = op_readsp(sp + 1);
   op_io();
-  if(regs.p.m)last_cycle();
+  if(regs.p.m) last_cycle();
   op_writedbr(aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)return;
+  if(regs.p.m) break;
   last_cycle();
   op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
-}
+} break;
 

src/cpu/scpu/core/opfn.cpp

@@ -1,209 +1,205 @@
+#ifdef SCPU_CPP
+
 //op_read
 inline void sCPU::op_adc_b() {
-int32 r = regs.a.l + rd.l + regs.p.c;
+  int r;
   if(regs.p.d) {
-  uint8 n0 = (regs.a.l     ) & 15;
-  uint8 n1 = (regs.a.l >> 4) & 15;
-    n0 += ((rd.l) & 15) + regs.p.c;
+    uint8 n0 = (regs.a.l     ) & 15;
+    uint8 n1 = (regs.a.l >> 4) & 15;
+    n0 += (rd.l & 15) + regs.p.c;
     if(n0 > 9) {
-      n0 -= 10;
-      n0 &= 15;
+      n0 = (n0 - 10) & 15;
       n1++;
     }
     n1 += ((rd.l >> 4) & 15);
     if(n1 > 9) {
-      n1 -= 10;
-      n1 &= 15;
+      n1 = (n1 - 10) & 15;
       regs.p.c = 1;
     } else {
       regs.p.c = 0;
     }
-    r = (n1 << 4) | (n0);
+    r = (n1 << 4) | n0;
   } else {
     r = regs.a.l + rd.l + regs.p.c;
-    regs.p.c = (r > 0xff);
+    regs.p.c = r > 0xff;
   }
-  regs.p.n = !!(r & 0x80);
-  regs.p.v = !!(~(regs.a.l ^ rd.l) & (regs.a.l ^ r) & 0x80);
-  regs.p.z = ((uint8)r == 0);
+  regs.p.n = r & 0x80;
+  regs.p.v = ~(regs.a.l ^ rd.l) & (regs.a.l ^ r) & 0x80;
+  regs.p.z = (uint8)r == 0;
   regs.a.l = r;
 }
 
 inline void sCPU::op_adc_w() {
-int32 r;
+  int r;
   if(regs.p.d) {
-  uint8 n0 = (regs.a.w      ) & 15;
-  uint8 n1 = (regs.a.w >>  4) & 15;
-  uint8 n2 = (regs.a.w >>  8) & 15;
-  uint8 n3 = (regs.a.w >> 12) & 15;
-    n0 += ((rd.w) & 15) + regs.p.c;
+    uint8 n0 = (regs.a.w      ) & 15;
+    uint8 n1 = (regs.a.w >>  4) & 15;
+    uint8 n2 = (regs.a.w >>  8) & 15;
+    uint8 n3 = (regs.a.w >> 12) & 15;
+    n0 += (rd.w & 15) + regs.p.c;
     if(n0 > 9) {
-      n0 -= 10;
-      n0 &= 15;
+      n0 = (n0 - 10) & 15;
       n1++;
     }
     n1 += ((rd.w >> 4) & 15);
     if(n1 > 9) {
-      n1 -= 10;
-      n1 &= 15;
+      n1 = (n1 - 10) & 15;
       n2++;
     }
     n2 += ((rd.w >> 8) & 15);
     if(n2 > 9) {
-      n2 -= 10;
-      n2 &= 15;
+      n2 = (n2 - 10) & 15;
       n3++;
     }
     n3 += ((rd.w >> 12) & 15);
     if(n3 > 9) {
-      n3 -= 10;
-      n3 &= 15;
+      n3 = (n3 - 10) & 15;
       regs.p.c = 1;
     } else {
       regs.p.c = 0;
     }
-    r = (n3 << 12) | (n2 << 8) | (n1 << 4) | (n0);
+    r = (n3 << 12) | (n2 << 8) | (n1 << 4) | n0;
   } else {
     r = regs.a.w + rd.w + regs.p.c;
-    regs.p.c = (r > 0xffff);
+    regs.p.c = r > 0xffff;
   }
-  regs.p.n = !!(r & 0x8000);
-  regs.p.v = !!(~(regs.a.w ^ rd.w) & (regs.a.w ^ r) & 0x8000);
-  regs.p.z = ((uint16)r == 0);
+  regs.p.n = r & 0x8000;
+  regs.p.v = ~(regs.a.w ^ rd.w) & (regs.a.w ^ r) & 0x8000;
+  regs.p.z = (uint16)r == 0;
   regs.a.w = r;
 }
 
 inline void sCPU::op_and_b() {
   regs.a.l &= rd.l;
-  regs.p.n = !!(regs.a.l & 0x80);
-  regs.p.z = (regs.a.l == 0);
+  regs.p.n = regs.a.l & 0x80;
+  regs.p.z = regs.a.l == 0;
 }
 
 inline void sCPU::op_and_w() {
   regs.a.w &= rd.w;
-  regs.p.n = !!(regs.a.w & 0x8000);
-  regs.p.z = (regs.a.w == 0);
+  regs.p.n = regs.a.w & 0x8000;
+  regs.p.z = regs.a.w == 0;
 }
 
 inline void sCPU::op_bit_b() {
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.v = !!(rd.l & 0x40);
-  regs.p.z = ((rd.l & regs.a.l) == 0);
+  regs.p.n = rd.l & 0x80;
+  regs.p.v = rd.l & 0x40;
+  regs.p.z = (rd.l & regs.a.l) == 0;
 }
 
 inline void sCPU::op_bit_w() {
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.v = !!(rd.w & 0x4000);
-  regs.p.z = ((rd.w & regs.a.w) == 0);
+  regs.p.n = rd.w & 0x8000;
+  regs.p.v = rd.w & 0x4000;
+  regs.p.z = (rd.w & regs.a.w) == 0;
 }
 
 inline void sCPU::op_cmp_b() {
-int32 r = regs.a.l - rd.l;
-  regs.p.n = !!(r & 0x80);
-  regs.p.z = ((uint8)r == 0);
-  regs.p.c = (r >= 0);
+  int r = regs.a.l - rd.l;
+  regs.p.n = r & 0x80;
+  regs.p.z = (uint8)r == 0;
+  regs.p.c = r >= 0;
 }
 
 inline void sCPU::op_cmp_w() {
-int32 r = regs.a.w - rd.w;
-  regs.p.n = !!(r & 0x8000);
-  regs.p.z = ((uint16)r == 0);
-  regs.p.c = (r >= 0);
+  int r = regs.a.w - rd.w;
+  regs.p.n = r & 0x8000;
+  regs.p.z = (uint16)r == 0;
+  regs.p.c = r >= 0;
 }
 
 inline void sCPU::op_cpx_b() {
-int32 r = regs.x.l - rd.l;
-  regs.p.n = !!(r & 0x80);
-  regs.p.z = ((uint8)r == 0);
-  regs.p.c = (r >= 0);
+  int r = regs.x.l - rd.l;
+  regs.p.n = r & 0x80;
+  regs.p.z = (uint8)r == 0;
+  regs.p.c = r >= 0;
 }
 
 inline void sCPU::op_cpx_w() {
-int32 r = regs.x.w - rd.w;
-  regs.p.n = !!(r & 0x8000);
-  regs.p.z = ((uint16)r == 0);
-  regs.p.c = (r >= 0);
+  int r = regs.x.w - rd.w;
+  regs.p.n = r & 0x8000;
+  regs.p.z = (uint16)r == 0;
+  regs.p.c = r >= 0;
 }
 
 inline void sCPU::op_cpy_b() {
-int32 r = regs.y.l - rd.l;
-  regs.p.n = !!(r & 0x80);
-  regs.p.z = ((uint8)r == 0);
-  regs.p.c = (r >= 0);
+  int r = regs.y.l - rd.l;
+  regs.p.n = r & 0x80;
+  regs.p.z = (uint8)r == 0;
+  regs.p.c = r >= 0;
 }
 
 inline void sCPU::op_cpy_w() {
-int32 r = regs.y.w - rd.w;
-  regs.p.n = !!(r & 0x8000);
-  regs.p.z = ((uint16)r == 0);
-  regs.p.c = (r >= 0);
+  int r = regs.y.w - rd.w;
+  regs.p.n = r & 0x8000;
+  regs.p.z = (uint16)r == 0;
+  regs.p.c = r >= 0;
 }
 
 inline void sCPU::op_eor_b() {
   regs.a.l ^= rd.l;
-  regs.p.n = !!(regs.a.l & 0x80);
-  regs.p.z = (regs.a.l == 0);
+  regs.p.n = regs.a.l & 0x80;
+  regs.p.z = regs.a.l == 0;
 }
 
 inline void sCPU::op_eor_w() {
   regs.a.w ^= rd.w;
-  regs.p.n = !!(regs.a.w & 0x8000);
-  regs.p.z = (regs.a.w == 0);
+  regs.p.n = regs.a.w & 0x8000;
+  regs.p.z = regs.a.w == 0;
 }
 
 inline void sCPU::op_lda_b() {
   regs.a.l = rd.l;
-  regs.p.n = !!(regs.a.l & 0x80);
-  regs.p.z = (regs.a.l == 0);
+  regs.p.n = regs.a.l & 0x80;
+  regs.p.z = regs.a.l == 0;
 }
 
 inline void sCPU::op_lda_w() {
   regs.a.w = rd.w;
-  regs.p.n = !!(regs.a.w & 0x8000);
-  regs.p.z = (regs.a.w == 0);
+  regs.p.n = regs.a.w & 0x8000;
+  regs.p.z = regs.a.w == 0;
 }
 
 inline void sCPU::op_ldx_b() {
   regs.x.l = rd.l;
-  regs.p.n = !!(regs.x.l & 0x80);
-  regs.p.z = (regs.x.l == 0);
+  regs.p.n = regs.x.l & 0x80;
+  regs.p.z = regs.x.l == 0;
 }
 
 inline void sCPU::op_ldx_w() {
   regs.x.w = rd.w;
-  regs.p.n = !!(regs.x.w & 0x8000);
-  regs.p.z = (regs.x.w == 0);
+  regs.p.n = regs.x.w & 0x8000;
+  regs.p.z = regs.x.w == 0;
 }
 
 inline void sCPU::op_ldy_b() {
   regs.y.l = rd.l;
-  regs.p.n = !!(regs.y.l & 0x80);
-  regs.p.z = (regs.y.l == 0);
+  regs.p.n = regs.y.l & 0x80;
+  regs.p.z = regs.y.l == 0;
 }
 
 inline void sCPU::op_ldy_w() {
   regs.y.w = rd.w;
-  regs.p.n = !!(regs.y.w & 0x8000);
-  regs.p.z = (regs.y.w == 0);
+  regs.p.n = regs.y.w & 0x8000;
+  regs.p.z = regs.y.w == 0;
 }
 
 inline void sCPU::op_ora_b() {
   regs.a.l |= rd.l;
-  regs.p.n = !!(regs.a.l & 0x80);
-  regs.p.z = (regs.a.l == 0);
+  regs.p.n = regs.a.l & 0x80;
+  regs.p.z = regs.a.l == 0;
 }
 
 inline void sCPU::op_ora_w() {
   regs.a.w |= rd.w;
-  regs.p.n = !!(regs.a.w & 0x8000);
-  regs.p.z = (regs.a.w == 0);
+  regs.p.n = regs.a.w & 0x8000;
+  regs.p.z = regs.a.w == 0;
 }
 
 inline void sCPU::op_sbc_b() {
-int32 r;
+  int r;
   if(regs.p.d) {
-  uint8 n0 = (regs.a.l     ) & 15;
-  uint8 n1 = (regs.a.l >> 4) & 15;
+    uint8 n0 = (regs.a.l     ) & 15;
+    uint8 n1 = (regs.a.l >> 4) & 15;
     n0 -= ((rd.l     ) & 15) + !regs.p.c;
     n1 -= ((rd.l >> 4) & 15);
     if(n0 > 9) {
@@ -219,21 +215,21 @@ int32 r;
     r = (n1 << 4) | (n0);
   } else {
     r = regs.a.l - rd.l - !regs.p.c;
-    regs.p.c = (r >= 0);
+    regs.p.c = r >= 0;
   }
-  regs.p.n = !!(r & 0x80);
-  regs.p.v = !!((regs.a.l ^ rd.l) & (regs.a.l ^ r) & 0x80);
-  regs.p.z = ((uint8)r == 0);
+  regs.p.n = r & 0x80;
+  regs.p.v = (regs.a.l ^ rd.l) & (regs.a.l ^ r) & 0x80;
+  regs.p.z = (uint8)r == 0;
   regs.a.l = r;
 }
 
 inline void sCPU::op_sbc_w() {
-int32 r;
+  int r;
   if(regs.p.d) {
-  uint8 n0 = (regs.a.w      ) & 15;
-  uint8 n1 = (regs.a.w >>  4) & 15;
-  uint8 n2 = (regs.a.w >>  8) & 15;
-  uint8 n3 = (regs.a.w >> 12) & 15;
+    uint8 n0 = (regs.a.w      ) & 15;
+    uint8 n1 = (regs.a.w >>  4) & 15;
+    uint8 n2 = (regs.a.w >>  8) & 15;
+    uint8 n3 = (regs.a.w >> 12) & 15;
     n0 -= ((rd.w      ) & 15) + !regs.p.c;
     n1 -= ((rd.w >>  4) & 15);
     n2 -= ((rd.w >>  8) & 15);
@@ -259,115 +255,117 @@ int32 r;
     r = (n3 << 12) | (n2 << 8) | (n1 << 4) | (n0);
   } else {
     r = regs.a.w - rd.w - !regs.p.c;
-    regs.p.c = (r >= 0);
+    regs.p.c = r >= 0;
   }
-  regs.p.n = !!(r & 0x8000);
-  regs.p.v = !!((regs.a.w ^ rd.w) & (regs.a.w ^ r) & 0x8000);
-  regs.p.z = ((uint16)r == 0);
+  regs.p.n = r & 0x8000;
+  regs.p.v = (regs.a.w ^ rd.w) & (regs.a.w ^ r) & 0x8000;
+  regs.p.z = (uint16)r == 0;
   regs.a.w = r;
 }
 
 //op_rmw
 inline void sCPU::op_inc_b() {
   rd.l++;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
+  regs.p.n = rd.l & 0x80;
+  regs.p.z = rd.l == 0;
 }
 
 inline void sCPU::op_inc_w() {
   rd.w++;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
+  regs.p.n = rd.w & 0x8000;
+  regs.p.z = rd.w == 0;
 }
 
 inline void sCPU::op_dec_b() {
   rd.l--;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
+  regs.p.n = rd.l & 0x80;
+  regs.p.z = rd.l == 0;
 }
 
 inline void sCPU::op_dec_w() {
   rd.w--;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
+  regs.p.n = rd.w & 0x8000;
+  regs.p.z = rd.w == 0;
 }
 
 inline void sCPU::op_asl_b() {
-  regs.p.c = !!(rd.l & 0x80);
+  regs.p.c = rd.l & 0x80;
   rd.l <<= 1;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
+  regs.p.n = rd.l & 0x80;
+  regs.p.z = rd.l == 0;
 }
 
 inline void sCPU::op_asl_w() {
-  regs.p.c = !!(rd.w & 0x8000);
+  regs.p.c = rd.w & 0x8000;
   rd.w <<= 1;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
+  regs.p.n = rd.w & 0x8000;
+  regs.p.z = rd.w == 0;
 }
 
 inline void sCPU::op_lsr_b() {
   regs.p.c = rd.l & 1;
   rd.l >>= 1;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
+  regs.p.n = rd.l & 0x80;
+  regs.p.z = rd.l == 0;
 }
 
 inline void sCPU::op_lsr_w() {
   regs.p.c = rd.w & 1;
   rd.w >>= 1;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
+  regs.p.n = rd.w & 0x8000;
+  regs.p.z = rd.w == 0;
 }
 
 inline void sCPU::op_rol_b() {
-uint16 carry = (uint16)regs.p.c;
-  regs.p.c = !!(rd.l & 0x80);
+  unsigned carry = (unsigned)regs.p.c;
+  regs.p.c = rd.l & 0x80;
   rd.l = (rd.l << 1) | carry;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
+  regs.p.n = rd.l & 0x80;
+  regs.p.z = rd.l == 0;
 }
 
 inline void sCPU::op_rol_w() {
-uint16 carry = (uint16)regs.p.c;
-  regs.p.c = !!(rd.w & 0x8000);
+  unsigned carry = (unsigned)regs.p.c;
+  regs.p.c = rd.w & 0x8000;
   rd.w = (rd.w << 1) | carry;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
+  regs.p.n = rd.w & 0x8000;
+  regs.p.z = rd.w == 0;
 }
 
 inline void sCPU::op_ror_b() {
-uint16 carry = (uint16)regs.p.c << 7;
+  unsigned carry = (unsigned)regs.p.c << 7;
   regs.p.c = rd.l & 1;
   rd.l = carry | (rd.l >> 1);
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
+  regs.p.n = rd.l & 0x80;
+  regs.p.z = rd.l == 0;
 }
 
 inline void sCPU::op_ror_w() {
-uint16 carry = (uint16)regs.p.c << 15;
+  unsigned carry = (unsigned)regs.p.c << 15;
   regs.p.c = rd.w & 1;
   rd.w = carry | (rd.w >> 1);
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
+  regs.p.n = rd.w & 0x8000;
+  regs.p.z = rd.w == 0;
 }
 
 inline void sCPU::op_trb_b() {
-  regs.p.z = ((rd.l & regs.a.l) == 0);
+  regs.p.z = (rd.l & regs.a.l) == 0;
   rd.l &= ~regs.a.l;
 }
 
 inline void sCPU::op_trb_w() {
-  regs.p.z = ((rd.w & regs.a.w) == 0);
+  regs.p.z = (rd.w & regs.a.w) == 0;
   rd.w &= ~regs.a.w;
 }
 
 inline void sCPU::op_tsb_b() {
-  regs.p.z = ((rd.l & regs.a.l) == 0);
+  regs.p.z = (rd.l & regs.a.l) == 0;
   rd.l |= regs.a.l;
 }
 
 inline void sCPU::op_tsb_w() {
-  regs.p.z = ((rd.w & regs.a.w) == 0);
+  regs.p.z = (rd.w & regs.a.w) == 0;
   rd.w |= regs.a.w;
 }
+
+#endif //ifdef SCPU_CPP

src/cpu/scpu/core/optable.cpp

@@ -1,256 +0,0 @@
-optbl[0x69] = &sCPU::op_adc_const;
-optbl[0x29] = &sCPU::op_and_const;
-optbl[0xc9] = &sCPU::op_cmp_const;
-optbl[0xe0] = &sCPU::op_cpx_const;
-optbl[0xc0] = &sCPU::op_cpy_const;
-optbl[0x49] = &sCPU::op_eor_const;
-optbl[0xa9] = &sCPU::op_lda_const;
-optbl[0xa2] = &sCPU::op_ldx_const;
-optbl[0xa0] = &sCPU::op_ldy_const;
-optbl[0x09] = &sCPU::op_ora_const;
-optbl[0xe9] = &sCPU::op_sbc_const;
-optbl[0x6d] = &sCPU::op_adc_addr;
-optbl[0x2d] = &sCPU::op_and_addr;
-optbl[0x2c] = &sCPU::op_bit_addr;
-optbl[0xcd] = &sCPU::op_cmp_addr;
-optbl[0xec] = &sCPU::op_cpx_addr;
-optbl[0xcc] = &sCPU::op_cpy_addr;
-optbl[0x4d] = &sCPU::op_eor_addr;
-optbl[0xad] = &sCPU::op_lda_addr;
-optbl[0xae] = &sCPU::op_ldx_addr;
-optbl[0xac] = &sCPU::op_ldy_addr;
-optbl[0x0d] = &sCPU::op_ora_addr;
-optbl[0xed] = &sCPU::op_sbc_addr;
-optbl[0x7d] = &sCPU::op_adc_addrx;
-optbl[0x3d] = &sCPU::op_and_addrx;
-optbl[0x3c] = &sCPU::op_bit_addrx;
-optbl[0xdd] = &sCPU::op_cmp_addrx;
-optbl[0x5d] = &sCPU::op_eor_addrx;
-optbl[0xbd] = &sCPU::op_lda_addrx;
-optbl[0xbc] = &sCPU::op_ldy_addrx;
-optbl[0x1d] = &sCPU::op_ora_addrx;
-optbl[0xfd] = &sCPU::op_sbc_addrx;
-optbl[0x79] = &sCPU::op_adc_addry;
-optbl[0x39] = &sCPU::op_and_addry;
-optbl[0xd9] = &sCPU::op_cmp_addry;
-optbl[0x59] = &sCPU::op_eor_addry;
-optbl[0xb9] = &sCPU::op_lda_addry;
-optbl[0xbe] = &sCPU::op_ldx_addry;
-optbl[0x19] = &sCPU::op_ora_addry;
-optbl[0xf9] = &sCPU::op_sbc_addry;
-optbl[0x6f] = &sCPU::op_adc_long;
-optbl[0x2f] = &sCPU::op_and_long;
-optbl[0xcf] = &sCPU::op_cmp_long;
-optbl[0x4f] = &sCPU::op_eor_long;
-optbl[0xaf] = &sCPU::op_lda_long;
-optbl[0x0f] = &sCPU::op_ora_long;
-optbl[0xef] = &sCPU::op_sbc_long;
-optbl[0x7f] = &sCPU::op_adc_longx;
-optbl[0x3f] = &sCPU::op_and_longx;
-optbl[0xdf] = &sCPU::op_cmp_longx;
-optbl[0x5f] = &sCPU::op_eor_longx;
-optbl[0xbf] = &sCPU::op_lda_longx;
-optbl[0x1f] = &sCPU::op_ora_longx;
-optbl[0xff] = &sCPU::op_sbc_longx;
-optbl[0x65] = &sCPU::op_adc_dp;
-optbl[0x25] = &sCPU::op_and_dp;
-optbl[0x24] = &sCPU::op_bit_dp;
-optbl[0xc5] = &sCPU::op_cmp_dp;
-optbl[0xe4] = &sCPU::op_cpx_dp;
-optbl[0xc4] = &sCPU::op_cpy_dp;
-optbl[0x45] = &sCPU::op_eor_dp;
-optbl[0xa5] = &sCPU::op_lda_dp;
-optbl[0xa6] = &sCPU::op_ldx_dp;
-optbl[0xa4] = &sCPU::op_ldy_dp;
-optbl[0x05] = &sCPU::op_ora_dp;
-optbl[0xe5] = &sCPU::op_sbc_dp;
-optbl[0x75] = &sCPU::op_adc_dpx;
-optbl[0x35] = &sCPU::op_and_dpx;
-optbl[0x34] = &sCPU::op_bit_dpx;
-optbl[0xd5] = &sCPU::op_cmp_dpx;
-optbl[0x55] = &sCPU::op_eor_dpx;
-optbl[0xb5] = &sCPU::op_lda_dpx;
-optbl[0xb4] = &sCPU::op_ldy_dpx;
-optbl[0x15] = &sCPU::op_ora_dpx;
-optbl[0xf5] = &sCPU::op_sbc_dpx;
-optbl[0xb6] = &sCPU::op_ldx_dpy;
-optbl[0x72] = &sCPU::op_adc_idp;
-optbl[0x32] = &sCPU::op_and_idp;
-optbl[0xd2] = &sCPU::op_cmp_idp;
-optbl[0x52] = &sCPU::op_eor_idp;
-optbl[0xb2] = &sCPU::op_lda_idp;
-optbl[0x12] = &sCPU::op_ora_idp;
-optbl[0xf2] = &sCPU::op_sbc_idp;
-optbl[0x61] = &sCPU::op_adc_idpx;
-optbl[0x21] = &sCPU::op_and_idpx;
-optbl[0xc1] = &sCPU::op_cmp_idpx;
-optbl[0x41] = &sCPU::op_eor_idpx;
-optbl[0xa1] = &sCPU::op_lda_idpx;
-optbl[0x01] = &sCPU::op_ora_idpx;
-optbl[0xe1] = &sCPU::op_sbc_idpx;
-optbl[0x71] = &sCPU::op_adc_idpy;
-optbl[0x31] = &sCPU::op_and_idpy;
-optbl[0xd1] = &sCPU::op_cmp_idpy;
-optbl[0x51] = &sCPU::op_eor_idpy;
-optbl[0xb1] = &sCPU::op_lda_idpy;
-optbl[0x11] = &sCPU::op_ora_idpy;
-optbl[0xf1] = &sCPU::op_sbc_idpy;
-optbl[0x67] = &sCPU::op_adc_ildp;
-optbl[0x27] = &sCPU::op_and_ildp;
-optbl[0xc7] = &sCPU::op_cmp_ildp;
-optbl[0x47] = &sCPU::op_eor_ildp;
-optbl[0xa7] = &sCPU::op_lda_ildp;
-optbl[0x07] = &sCPU::op_ora_ildp;
-optbl[0xe7] = &sCPU::op_sbc_ildp;
-optbl[0x77] = &sCPU::op_adc_ildpy;
-optbl[0x37] = &sCPU::op_and_ildpy;
-optbl[0xd7] = &sCPU::op_cmp_ildpy;
-optbl[0x57] = &sCPU::op_eor_ildpy;
-optbl[0xb7] = &sCPU::op_lda_ildpy;
-optbl[0x17] = &sCPU::op_ora_ildpy;
-optbl[0xf7] = &sCPU::op_sbc_ildpy;
-optbl[0x63] = &sCPU::op_adc_sr;
-optbl[0x23] = &sCPU::op_and_sr;
-optbl[0xc3] = &sCPU::op_cmp_sr;
-optbl[0x43] = &sCPU::op_eor_sr;
-optbl[0xa3] = &sCPU::op_lda_sr;
-optbl[0x03] = &sCPU::op_ora_sr;
-optbl[0xe3] = &sCPU::op_sbc_sr;
-optbl[0x73] = &sCPU::op_adc_isry;
-optbl[0x33] = &sCPU::op_and_isry;
-optbl[0xd3] = &sCPU::op_cmp_isry;
-optbl[0x53] = &sCPU::op_eor_isry;
-optbl[0xb3] = &sCPU::op_lda_isry;
-optbl[0x13] = &sCPU::op_ora_isry;
-optbl[0xf3] = &sCPU::op_sbc_isry;
-optbl[0x89] = &sCPU::op_bit_const;
-optbl[0x8d] = &sCPU::op_sta_addr;
-optbl[0x8e] = &sCPU::op_stx_addr;
-optbl[0x8c] = &sCPU::op_sty_addr;
-optbl[0x9c] = &sCPU::op_stz_addr;
-optbl[0x9d] = &sCPU::op_sta_addrx;
-optbl[0x9e] = &sCPU::op_stz_addrx;
-optbl[0x99] = &sCPU::op_sta_addry;
-optbl[0x8f] = &sCPU::op_sta_long;
-optbl[0x9f] = &sCPU::op_sta_longx;
-optbl[0x85] = &sCPU::op_sta_dp;
-optbl[0x86] = &sCPU::op_stx_dp;
-optbl[0x84] = &sCPU::op_sty_dp;
-optbl[0x64] = &sCPU::op_stz_dp;
-optbl[0x95] = &sCPU::op_sta_dpx;
-optbl[0x94] = &sCPU::op_sty_dpx;
-optbl[0x74] = &sCPU::op_stz_dpx;
-optbl[0x96] = &sCPU::op_stx_dpy;
-optbl[0x92] = &sCPU::op_sta_idp;
-optbl[0x87] = &sCPU::op_sta_ildp;
-optbl[0x81] = &sCPU::op_sta_idpx;
-optbl[0x91] = &sCPU::op_sta_idpy;
-optbl[0x97] = &sCPU::op_sta_ildpy;
-optbl[0x83] = &sCPU::op_sta_sr;
-optbl[0x93] = &sCPU::op_sta_isry;
-optbl[0x1a] = &sCPU::op_inc;
-optbl[0xe8] = &sCPU::op_inx;
-optbl[0xc8] = &sCPU::op_iny;
-optbl[0x3a] = &sCPU::op_dec;
-optbl[0xca] = &sCPU::op_dex;
-optbl[0x88] = &sCPU::op_dey;
-optbl[0x0a] = &sCPU::op_asl;
-optbl[0x4a] = &sCPU::op_lsr;
-optbl[0x2a] = &sCPU::op_rol;
-optbl[0x6a] = &sCPU::op_ror;
-optbl[0xee] = &sCPU::op_inc_addr;
-optbl[0xce] = &sCPU::op_dec_addr;
-optbl[0x0e] = &sCPU::op_asl_addr;
-optbl[0x4e] = &sCPU::op_lsr_addr;
-optbl[0x2e] = &sCPU::op_rol_addr;
-optbl[0x6e] = &sCPU::op_ror_addr;
-optbl[0x1c] = &sCPU::op_trb_addr;
-optbl[0x0c] = &sCPU::op_tsb_addr;
-optbl[0xfe] = &sCPU::op_inc_addrx;
-optbl[0xde] = &sCPU::op_dec_addrx;
-optbl[0x1e] = &sCPU::op_asl_addrx;
-optbl[0x5e] = &sCPU::op_lsr_addrx;
-optbl[0x3e] = &sCPU::op_rol_addrx;
-optbl[0x7e] = &sCPU::op_ror_addrx;
-optbl[0xe6] = &sCPU::op_inc_dp;
-optbl[0xc6] = &sCPU::op_dec_dp;
-optbl[0x06] = &sCPU::op_asl_dp;
-optbl[0x46] = &sCPU::op_lsr_dp;
-optbl[0x26] = &sCPU::op_rol_dp;
-optbl[0x66] = &sCPU::op_ror_dp;
-optbl[0x14] = &sCPU::op_trb_dp;
-optbl[0x04] = &sCPU::op_tsb_dp;
-optbl[0xf6] = &sCPU::op_inc_dpx;
-optbl[0xd6] = &sCPU::op_dec_dpx;
-optbl[0x16] = &sCPU::op_asl_dpx;
-optbl[0x56] = &sCPU::op_lsr_dpx;
-optbl[0x36] = &sCPU::op_rol_dpx;
-optbl[0x76] = &sCPU::op_ror_dpx;
-optbl[0x90] = &sCPU::op_bcc;
-optbl[0xb0] = &sCPU::op_bcs;
-optbl[0xd0] = &sCPU::op_bne;
-optbl[0xf0] = &sCPU::op_beq;
-optbl[0x10] = &sCPU::op_bpl;
-optbl[0x30] = &sCPU::op_bmi;
-optbl[0x50] = &sCPU::op_bvc;
-optbl[0x70] = &sCPU::op_bvs;
-optbl[0x80] = &sCPU::op_bra;
-optbl[0x82] = &sCPU::op_brl;
-optbl[0x4c] = &sCPU::op_jmp_addr;
-optbl[0x5c] = &sCPU::op_jmp_long;
-optbl[0x6c] = &sCPU::op_jmp_iaddr;
-optbl[0x7c] = &sCPU::op_jmp_iaddrx;
-optbl[0xdc] = &sCPU::op_jmp_iladdr;
-optbl[0x20] = &sCPU::op_jsr_addr;
-optbl[0x22] = &sCPU::op_jsr_long;
-optbl[0xfc] = &sCPU::op_jsr_iaddrx;
-optbl[0x40] = &sCPU::op_rti;
-optbl[0x60] = &sCPU::op_rts;
-optbl[0x6b] = &sCPU::op_rtl;
-optbl[0xea] = &sCPU::op_nop;
-optbl[0x42] = &sCPU::op_wdm;
-optbl[0xeb] = &sCPU::op_xba;
-optbl[0x54] = &sCPU::op_mvn;
-optbl[0x44] = &sCPU::op_mvp;
-optbl[0x00] = &sCPU::op_brk;
-optbl[0x02] = &sCPU::op_cop;
-optbl[0xdb] = &sCPU::op_stp;
-optbl[0xcb] = &sCPU::op_wai;
-optbl[0xfb] = &sCPU::op_xce;
-optbl[0x18] = &sCPU::op_clc;
-optbl[0xd8] = &sCPU::op_cld;
-optbl[0x58] = &sCPU::op_cli;
-optbl[0xb8] = &sCPU::op_clv;
-optbl[0x38] = &sCPU::op_sec;
-optbl[0xf8] = &sCPU::op_sed;
-optbl[0x78] = &sCPU::op_sei;
-optbl[0xc2] = &sCPU::op_rep;
-optbl[0xe2] = &sCPU::op_sep;
-optbl[0xaa] = &sCPU::op_tax;
-optbl[0xa8] = &sCPU::op_tay;
-optbl[0x8a] = &sCPU::op_txa;
-optbl[0x9b] = &sCPU::op_txy;
-optbl[0x98] = &sCPU::op_tya;
-optbl[0xbb] = &sCPU::op_tyx;
-optbl[0x5b] = &sCPU::op_tcd;
-optbl[0x1b] = &sCPU::op_tcs;
-optbl[0x7b] = &sCPU::op_tdc;
-optbl[0x3b] = &sCPU::op_tsc;
-optbl[0xba] = &sCPU::op_tsx;
-optbl[0x9a] = &sCPU::op_txs;
-optbl[0x48] = &sCPU::op_pha;
-optbl[0xda] = &sCPU::op_phx;
-optbl[0x5a] = &sCPU::op_phy;
-optbl[0x0b] = &sCPU::op_phd;
-optbl[0x8b] = &sCPU::op_phb;
-optbl[0x4b] = &sCPU::op_phk;
-optbl[0x08] = &sCPU::op_php;
-optbl[0x68] = &sCPU::op_pla;
-optbl[0xfa] = &sCPU::op_plx;
-optbl[0x7a] = &sCPU::op_ply;
-optbl[0x2b] = &sCPU::op_pld;
-optbl[0xab] = &sCPU::op_plb;
-optbl[0x28] = &sCPU::op_plp;
-optbl[0xf4] = &sCPU::op_pea;
-optbl[0xd4] = &sCPU::op_pei;
-optbl[0x62] = &sCPU::op_per;

src/cpu/scpu/core/scpugen.cpp

@@ -1,18 +1,12 @@
 #define CLASS_NAME "sCPU"
-#include "../../../lib/opgen_so.cpp"
+#include <tool/opgen_switch.cpp>
 
 int main() {
-  fph = fopen("op.h", "wb");
-  fpt = fopen("optable.cpp", "wb");
-
   generate("op_read.cpp",  "op_read.b");
   generate("op_write.cpp", "op_write.b");
   generate("op_rmw.cpp",   "op_rmw.b");
   generate("op_pc.cpp",    "op_pc.b");
   generate("op_misc.cpp",  "op_misc.b");
 
-  fclose(fph);
-  fclose(fpt);
-
   return 0;
 }

src/cpu/scpu/dma/dma.cpp

@@ -1,273 +1,289 @@
-void sCPU::dma_add_clocks(uint clocks) {
-  status.dma_clocks += clocks;
-  add_clocks(clocks);
-}
-
-/*****
- * used by both DMA and HDMA
- *
- * DMA address bus A cannot read from or write to the following addresses :
- * $[00-3f|80-bf]:43[00-7f] <DMA control registers>
- * $[00-3f|80-bf]:420b      <DMA enable register>
- * $[00-3f|80-bf]:420c      <HDMA enable register>
- * WRAM<>WRAM transfers via $2180
- *****/
-void sCPU::dma_transfer(bool direction, uint8 bbus, uint32 abus) {
-uint8 r;
-  if(direction == 0) { //a->b
-    if((abus & 0x40ff00) == 0x2100 || (abus & 0x40ff80) == 0x4300 ||
-       (abus & 0x40ffff) == 0x420b || (abus & 0x40ffff) == 0x420c) {
-      r = regs.mdr;
-    } else {
-      r = bus.read(abus);
-    }
-    bus.write(0x2100 | bbus, r);
-  } else { //b->a
-    if(bbus == 0x80 && ((abus & 0x7e0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000)) {
-    //prevent WRAM->WRAM transfers
-      r = regs.mdr;
-    } else {
-      r = bus.read(0x2100 | bbus);
-    }
-    if((abus & 0x40ff00) == 0x2100 || (abus & 0x40ff80) == 0x4300 ||
-       (abus & 0x40ffff) == 0x420b || (abus & 0x40ffff) == 0x420c)return;
-    bus.write(abus, r);
-  }
-
-  dma_add_clocks(8);
-  cycle_edge();
-}
-
-/*****
- * address calculation functions
- *****/
-
-uint8 sCPU::dma_bbus(uint8 i, uint8 index) {
-  switch(channel[i].xfermode) {
-  default:
-  case 0: return (channel[i].destaddr);                      break; //0
-  case 1: return (channel[i].destaddr + (index & 1));        break; //0,1
-  case 2: return (channel[i].destaddr);                      break; //0,0
-  case 3: return (channel[i].destaddr + ((index >> 1) & 1)); break; //0,0,1,1
-  case 4: return (channel[i].destaddr + (index & 3));        break; //0,1,2,3
-  case 5: return (channel[i].destaddr + (index & 1));        break; //0,1,0,1
-  case 6: return (channel[i].destaddr);                      break; //0,0     [2]
-  case 7: return (channel[i].destaddr + ((index >> 1) & 1)); break; //0,0,1,1 [3]
-  }
-}
-
-inline uint32 sCPU::dma_addr(uint8 i) {
-uint32 r = (channel[i].srcbank << 16) | (channel[i].srcaddr);
-
-  if(channel[i].fixedxfer == false) {
-    if(channel[i].reversexfer == false) {
-      channel[i].srcaddr++;
-    } else {
-      channel[i].srcaddr--;
-    }
-  }
-
-  return r;
-}
-
-inline uint32 sCPU::hdma_addr(uint8 i) {
-  return (channel[i].srcbank << 16) | (channel[i].hdma_addr++);
-}
-
-inline uint32 sCPU::hdma_iaddr(uint8 i) {
-  return (channel[i].hdma_ibank << 16) | (channel[i].hdma_iaddr++);
-}
-
-/*****
- * DMA functions
- *****/
-
-void sCPU::dma_transfertobusb(uint8 i, uint8 bbus) {
-  if(cartridge.info.sdd1 == true && sdd1.dma_active() == true) {
-    bus.write(0x2100 | bbus, sdd1.dma_read());
-  } else {
-    dma_transfer(0, bbus, dma_addr(i));
-  }
-  channel[i].xfersize--;
-}
-
-void sCPU::dma_transfertobusa(uint8 i, uint8 bbus) {
-  dma_transfer(1, bbus, dma_addr(i));
-  channel[i].xfersize--;
-}
-
-inline void sCPU::dma_write(uint8 i, uint8 index) {
-//cannot use dma_transfer() directly, due to current S-DD1 implementation
-  if(channel[i].direction == 0) {
-    dma_transfertobusb(i, index);
-  } else {
-    dma_transfertobusa(i, index);
-  }
-}
-
-void sCPU::dma_run() {
-  for(int i = 0; i < 8; i++) {
-    if(channel[i].dma_enabled == false)continue;
-    dma_add_clocks(8);
-
-    if(cartridge.info.sdd1 == true) {
-      sdd1.dma_begin(i, (channel[i].srcbank << 16) | (channel[i].srcaddr), channel[i].xfersize);
-    }
-
-    if(tracer.enabled() == true && tracer.cpudma_enabled() == true) {
-      tprintf("[DMA] channel:%d direction:%s reverse:%c fixed:%c mode:%d b_addr:$21%0.2x "
-              "a_addr:$%0.2x%0.4x length:$%0.4x (%5d)",
-        i, channel[i].direction ? "b->a" : "a->b", channel[i].reversexfer ? '1' : '0',
-        channel[i].fixedxfer ? '1' : '0', channel[i].xfermode, channel[i].destaddr,
-        channel[i].srcbank, channel[i].srcaddr,
-        channel[i].xfersize, channel[i].xfersize ? channel[i].xfersize : 65536);
-    }
-
-  uint index = 0;
-    do {
-      dma_write(i, dma_bbus(i, index++));
-    } while(channel[i].dma_enabled && channel[i].xfersize);
-
-    channel[i].dma_enabled = false;
-  }
-
-  counter.set(counter.irq_delay, 2);
-}
-
-/*****
- * HDMA functions
- *****/
-
-inline bool sCPU::hdma_active(uint8 i) {
-  return (channel[i].hdma_enabled && !channel[i].hdma_completed);
-}
-
-inline bool sCPU::hdma_active_after(uint8 i) {
-  for(int n = i + 1; n < 8; n++) {
-    if(hdma_active(n) == true) { return true; }
-  }
-
-  return false;
-}
-
-inline uint8 sCPU::hdma_enabled_channels() {
-uint8 r = 0;
-  for(int i = 0; i < 8; i++) {
-    if(channel[i].hdma_enabled)r++;
-  }
-  return r;
-}
-
-inline uint8 sCPU::hdma_active_channels() {
-uint8 r = 0;
-  for(int i = 0; i < 8; i++) {
-    if(hdma_active(i) == true)r++;
-  }
-  return r;
-}
-
-void sCPU::hdma_update(uint8 i) {
-  channel[i].hdma_line_counter = bus.read(hdma_addr(i));
-  dma_add_clocks(8);
-
-  channel[i].hdma_completed   = (channel[i].hdma_line_counter == 0);
-  channel[i].hdma_do_transfer = !channel[i].hdma_completed;
-
-  if(channel[i].hdma_indirect) {
-    channel[i].hdma_iaddr = bus.read(hdma_addr(i)) << 8;
-    dma_add_clocks(8);
-
-    if(!channel[i].hdma_completed || hdma_active_after(i)) {
-      channel[i].hdma_iaddr >>= 8;
-      channel[i].hdma_iaddr  |= bus.read(hdma_addr(i)) << 8;
-      dma_add_clocks(8);
-    }
-  }
-}
-
-void sCPU::hdma_run() {
-static uint8 hdma_xferlen[8] = { 1, 2, 2, 4, 4, 4, 2, 4 };
-  for(int i = 0; i < 8; i++) {
-    if(hdma_active(i) == false)continue;
-    channel[i].dma_enabled = false; //HDMA run during DMA will stop DMA mid-transfer
-    dma_add_clocks(8);
-
-    if(channel[i].hdma_do_transfer) {
-    int xferlen = hdma_xferlen[channel[i].xfermode];
-      for(int index = 0; index < xferlen; index++) {
-        if(bool(config::cpu.hdma_enable) == true) {
-          dma_transfer(channel[i].direction, dma_bbus(i, index),
-            !channel[i].hdma_indirect ? hdma_addr(i) : hdma_iaddr(i));
-        } else {
-          dma_add_clocks(8);
-          cycle_edge();
-        }
-      }
-    }
-
-    channel[i].hdma_line_counter--;
-    channel[i].hdma_do_transfer = bool(channel[i].hdma_line_counter & 0x80);
-    if((channel[i].hdma_line_counter & 0x7f) == 0) {
-      hdma_update(i);
-    }
-  }
-
-  counter.set(counter.irq_delay, 2);
-}
-
-void sCPU::hdma_init_reset() {
-  for(int i = 0; i < 8; i++) {
-    channel[i].hdma_completed   = false;
-    channel[i].hdma_do_transfer = false;
-  }
-}
-
-void sCPU::hdma_init() {
-  for(int i = 0; i < 8; i++) {
-    if(!channel[i].hdma_enabled)continue;
-    channel[i].dma_enabled = false; //HDMA init during DMA will stop DMA mid-transfer
-
-    channel[i].hdma_addr = channel[i].srcaddr;
-    hdma_update(i);
-  }
-
-  counter.set(counter.irq_delay, 2);
-}
-
-/*****
- * power / reset functions
- *****/
-
-void sCPU::dma_power() {
-  for(int i = 0; i < 8; i++) {
-    channel[i].dmap              = 0xff;
-    channel[i].direction         = 1;
-    channel[i].hdma_indirect     = true;
-    channel[i].reversexfer       = true;
-    channel[i].fixedxfer         = true;
-    channel[i].xfermode          = 7;
-
-    channel[i].destaddr          = 0xff;
-
-    channel[i].srcaddr           = 0xffff;
-    channel[i].srcbank           = 0xff;
-
-    channel[i].xfersize          = 0xffff;
-  //channel[i].hdma_iaddr        = 0xffff; //union with xfersize
-    channel[i].hdma_ibank        = 0xff;
-
-    channel[i].hdma_addr         = 0xffff;
-    channel[i].hdma_line_counter = 0xff;
-    channel[i].unknown           = 0xff;
-  }
-}
-
-void sCPU::dma_reset() {
-  for(int i = 0; i < 8; i++) {
-    channel[i].dma_enabled       = false;
-    channel[i].hdma_enabled      = false;
-
-    channel[i].hdma_completed    = false;
-    channel[i].hdma_do_transfer  = false;
-  }
-}
+#ifdef SCPU_CPP
+
+void sCPU::dma_add_clocks(uint clocks) {
+  status.dma_clocks += clocks;
+  add_clocks(clocks);
+}
+
+/*****
+ * used by both DMA and HDMA
+ *
+ * DMA address bus A cannot read from or write to the following addresses :
+ * $[00-3f|80-bf]:43[00-7f] <DMA control registers>
+ * $[00-3f|80-bf]:420b      <DMA enable register>
+ * $[00-3f|80-bf]:420c      <HDMA enable register>
+ *
+ * WRAM<>WRAM transfers via $2180 are also illegal
+ *****/
+
+void sCPU::dma_transfer(bool direction, uint8 bbus, uint32 abus) {
+  if(direction == 0) {
+    //a->b transfer (to $21xx)
+    if(bbus == 0x80 && ((abus & 0xfe0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000)) {
+      //illegal WRAM->WRAM transfer
+      //read most likely occurs; no write occurs
+      //read is irrelevant, as it has no observable effect on emulation
+    } else if((abus & 0x40ff00) == 0x2100 || (abus & 0x40ff80) == 0x4300
+           || (abus & 0x40ffff) == 0x420b || (abus & 0x40ffff) == 0x420c) {
+      //illegal register access
+      bus.write(0x2100 | bbus, regs.mdr); //TODO: verify if MDR is written here
+    } else {
+      //valid transfer
+      bus.write(0x2100 | bbus, bus.read(abus));
+    }
+  } else {
+    //b->a transfer (from $21xx)
+    if(bbus == 0x80 && ((abus & 0xfe0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000)) {
+      //illegal WRAM->WRAM transfer
+      //no read occurs; write does occur
+      //does not write MDR as expected
+      //TODO: 0x00 was observed on hardware; verify if other values are possible
+      bus.write(abus, 0x00);
+    } else if((abus & 0x40ff00) == 0x2100 || (abus & 0x40ff80) == 0x4300
+           || (abus & 0x40ffff) == 0x420b || (abus & 0x40ffff) == 0x420c) {
+      //illegal register access
+      bus.write(abus, regs.mdr); //TODO: verify if MDR is written here
+    } else {
+      //valid transfer
+      bus.write(abus, bus.read(0x2100 | bbus));
+    }
+  }
+
+  //each byte *always* consumes 8 clocks, even if transfer is invalid and no read and/or write occurs
+  dma_add_clocks(8);
+  cycle_edge();
+}
+
+/*****
+ * address calculation functions
+ *****/
+
+uint8 sCPU::dma_bbus(uint8 i, uint8 index) {
+  switch(channel[i].xfermode) { default:
+    case 0: return (channel[i].destaddr);                      //0
+    case 1: return (channel[i].destaddr + (index & 1));        //0,1
+    case 2: return (channel[i].destaddr);                      //0,0
+    case 3: return (channel[i].destaddr + ((index >> 1) & 1)); //0,0,1,1
+    case 4: return (channel[i].destaddr + (index & 3));        //0,1,2,3
+    case 5: return (channel[i].destaddr + (index & 1));        //0,1,0,1
+    case 6: return (channel[i].destaddr);                      //0,0     [2]
+    case 7: return (channel[i].destaddr + ((index >> 1) & 1)); //0,0,1,1 [3]
+  }
+}
+
+inline uint32 sCPU::dma_addr(uint8 i) {
+  uint32 r = (channel[i].srcbank << 16) | (channel[i].srcaddr);
+
+  if(channel[i].fixedxfer == false) {
+    if(channel[i].reversexfer == false) {
+      channel[i].srcaddr++;
+    } else {
+      channel[i].srcaddr--;
+    }
+  }
+
+  return r;
+}
+
+inline uint32 sCPU::hdma_addr(uint8 i) {
+  return (channel[i].srcbank << 16) | (channel[i].hdma_addr++);
+}
+
+inline uint32 sCPU::hdma_iaddr(uint8 i) {
+  return (channel[i].hdma_ibank << 16) | (channel[i].hdma_iaddr++);
+}
+
+/*****
+ * DMA functions
+ *****/
+
+void sCPU::dma_transfertobusb(uint8 i, uint8 bbus) {
+  if(cartridge.info.sdd1 == true && sdd1.dma_active() == true) {
+    bus.write(0x2100 | bbus, sdd1.dma_read());
+  } else {
+    dma_transfer(0, bbus, dma_addr(i));
+  }
+  channel[i].xfersize--;
+}
+
+void sCPU::dma_transfertobusa(uint8 i, uint8 bbus) {
+  dma_transfer(1, bbus, dma_addr(i));
+  channel[i].xfersize--;
+}
+
+inline void sCPU::dma_write(uint8 i, uint8 index) {
+  //cannot use dma_transfer() directly, due to current S-DD1 implementation
+  if(channel[i].direction == 0) {
+    dma_transfertobusb(i, index);
+  } else {
+    dma_transfertobusa(i, index);
+  }
+}
+
+void sCPU::dma_run() {
+  for(int i = 0; i < 8; i++) {
+    if(channel[i].dma_enabled == false) continue;
+    dma_add_clocks(8);
+
+    if(cartridge.info.sdd1 == true) {
+      sdd1.dma_begin(i, (channel[i].srcbank << 16) | (channel[i].srcaddr), channel[i].xfersize);
+    }
+
+    if(tracer.enabled() == true && tracer.cpudma_enabled() == true) {
+      tprintf("[DMA] channel:%d direction:%s reverse:%c fixed:%c mode:%d b_addr:$21%0.2x "
+              "a_addr:$%0.2x%0.4x length:$%0.4x (%5d)",
+        i, channel[i].direction ? "b->a" : "a->b", channel[i].reversexfer ? '1' : '0',
+        channel[i].fixedxfer ? '1' : '0', channel[i].xfermode, channel[i].destaddr,
+        channel[i].srcbank, channel[i].srcaddr,
+        channel[i].xfersize, channel[i].xfersize ? channel[i].xfersize : 65536);
+    }
+
+    uint index = 0;
+    do {
+      dma_write(i, dma_bbus(i, index++));
+    } while(channel[i].dma_enabled && channel[i].xfersize);
+
+    channel[i].dma_enabled = false;
+  }
+
+  counter.set(counter.irq_delay, 2);
+}
+
+/*****
+ * HDMA functions
+ *****/
+
+inline bool sCPU::hdma_active(uint8 i) {
+  return (channel[i].hdma_enabled && !channel[i].hdma_completed);
+}
+
+inline bool sCPU::hdma_active_after(uint8 i) {
+  for(int n = i + 1; n < 8; n++) {
+    if(hdma_active(n) == true) return true;
+  }
+  return false;
+}
+
+inline uint8 sCPU::hdma_enabled_channels() {
+  uint8 r = 0;
+  for(int i = 0; i < 8; i++) {
+    if(channel[i].hdma_enabled) r++;
+  }
+  return r;
+}
+
+inline uint8 sCPU::hdma_active_channels() {
+  uint8 r = 0;
+  for(int i = 0; i < 8; i++) {
+    if(hdma_active(i) == true) r++;
+  }
+  return r;
+}
+
+void sCPU::hdma_update(uint8 i) {
+  channel[i].hdma_line_counter = bus.read(hdma_addr(i));
+  dma_add_clocks(8);
+
+  channel[i].hdma_completed   = (channel[i].hdma_line_counter == 0);
+  channel[i].hdma_do_transfer = !channel[i].hdma_completed;
+
+  if(channel[i].hdma_indirect) {
+    channel[i].hdma_iaddr = bus.read(hdma_addr(i)) << 8;
+    dma_add_clocks(8);
+
+    if(!channel[i].hdma_completed || hdma_active_after(i)) {
+      channel[i].hdma_iaddr >>= 8;
+      channel[i].hdma_iaddr  |= bus.read(hdma_addr(i)) << 8;
+      dma_add_clocks(8);
+    }
+  }
+}
+
+void sCPU::hdma_run() {
+  static uint8 hdma_xferlen[8] = { 1, 2, 2, 4, 4, 4, 2, 4 };
+  for(int i = 0; i < 8; i++) {
+    if(hdma_active(i) == false) continue;
+    channel[i].dma_enabled = false; //HDMA run during DMA will stop DMA mid-transfer
+    dma_add_clocks(8);
+
+    if(channel[i].hdma_do_transfer) {
+      int xferlen = hdma_xferlen[channel[i].xfermode];
+      for(int index = 0; index < xferlen; index++) {
+        if(bool(config::cpu.hdma_enable) == true) {
+          dma_transfer(channel[i].direction, dma_bbus(i, index),
+            !channel[i].hdma_indirect ? hdma_addr(i) : hdma_iaddr(i));
+        } else {
+          dma_add_clocks(8);
+          cycle_edge();
+        }
+      }
+    }
+
+    channel[i].hdma_line_counter--;
+    channel[i].hdma_do_transfer = bool(channel[i].hdma_line_counter & 0x80);
+    if((channel[i].hdma_line_counter & 0x7f) == 0) {
+      hdma_update(i);
+    }
+  }
+
+  counter.set(counter.irq_delay, 2);
+}
+
+void sCPU::hdma_init_reset() {
+  for(int i = 0; i < 8; i++) {
+    channel[i].hdma_completed   = false;
+    channel[i].hdma_do_transfer = false;
+  }
+}
+
+void sCPU::hdma_init() {
+  for(int i = 0; i < 8; i++) {
+    if(!channel[i].hdma_enabled)continue;
+    channel[i].dma_enabled = false; //HDMA init during DMA will stop DMA mid-transfer
+
+    channel[i].hdma_addr = channel[i].srcaddr;
+    hdma_update(i);
+  }
+
+  counter.set(counter.irq_delay, 2);
+}
+
+/*****
+ * power / reset functions
+ *****/
+
+void sCPU::dma_power() {
+  for(int i = 0; i < 8; i++) {
+    channel[i].dmap              = 0xff;
+    channel[i].direction         = 1;
+    channel[i].hdma_indirect     = true;
+    channel[i].reversexfer       = true;
+    channel[i].fixedxfer         = true;
+    channel[i].xfermode          = 7;
+
+    channel[i].destaddr          = 0xff;
+
+    channel[i].srcaddr           = 0xffff;
+    channel[i].srcbank           = 0xff;
+
+    channel[i].xfersize          = 0xffff;
+  //channel[i].hdma_iaddr        = 0xffff; //union with xfersize
+    channel[i].hdma_ibank        = 0xff;
+
+    channel[i].hdma_addr         = 0xffff;
+    channel[i].hdma_line_counter = 0xff;
+    channel[i].unknown           = 0xff;
+  }
+}
+
+void sCPU::dma_reset() {
+  for(int i = 0; i < 8; i++) {
+    channel[i].dma_enabled       = false;
+    channel[i].hdma_enabled      = false;
+
+    channel[i].hdma_completed    = false;
+    channel[i].hdma_do_transfer  = false;
+  }
+}
+
+#endif //ifdef SCPU_CPP

src/cpu/scpu/dma/dma.h

@@ -1,71 +1,71 @@
-struct {
-//$420b
-  bool   dma_enabled;
+  struct {
+    //$420b
+    bool   dma_enabled;
 
-//$420c
-  bool   hdma_enabled;
+    //$420c
+    bool   hdma_enabled;
 
-//$43x0
-  uint8  dmap;
-  bool   direction;
-  bool   hdma_indirect;
-  bool   reversexfer;
-  bool   fixedxfer;
-  uint8  xfermode;
+    //$43x0
+    uint8  dmap;
+    bool   direction;
+    bool   hdma_indirect;
+    bool   reversexfer;
+    bool   fixedxfer;
+    uint8  xfermode;
 
-//$43x1
-  uint8  destaddr;
+    //$43x1
+    uint8  destaddr;
 
-//$43x2-$43x3
-  uint16 srcaddr;
+    //$43x2-$43x3
+    uint16 srcaddr;
 
-//$43x4
-  uint8  srcbank;
+    //$43x4
+    uint8  srcbank;
 
-//$43x5-$43x6
-  union {
-  uint16 xfersize;
-  uint16 hdma_iaddr;
-  };
+    //$43x5-$43x6
+    union {
+      uint16 xfersize;
+      uint16 hdma_iaddr;
+    };
 
-//$43x7
-  uint8  hdma_ibank;
+    //$43x7
+    uint8  hdma_ibank;
 
-//$43x8-$43x9
-  uint16 hdma_addr;
+    //$43x8-$43x9
+    uint16 hdma_addr;
 
-//$43xa
-  uint8  hdma_line_counter;
+    //$43xa
+    uint8  hdma_line_counter;
 
-//$43xb/$43xf
-  uint8  unknown;
+    //$43xb/$43xf
+    uint8  unknown;
 
-//internal variables
-  bool   hdma_completed;
-  bool   hdma_do_transfer;
-} channel[8];
+    //internal variables
+    bool   hdma_completed;
+    bool   hdma_do_transfer;
+  } channel[8];
 
-  void   dma_add_clocks(uint clocks);
-  void   dma_transfer(bool direction, uint8 bbus, uint32 abus);
+  void dma_add_clocks(uint clocks);
+  void dma_transfer(bool direction, uint8 bbus, uint32 abus);
 
-  uint8  dma_bbus(uint8 i, uint8 index);
+  uint8 dma_bbus(uint8 i, uint8 index);
   uint32 dma_addr(uint8 i);
   uint32 hdma_addr(uint8 i);
   uint32 hdma_iaddr(uint8 i);
 
-  void   dma_transfertobusb(uint8 i, uint8 bbus);
-  void   dma_transfertobusa(uint8 i, uint8 bbus);
-  void   dma_write(uint8 i, uint8 index);
-  void   dma_run();
+  void dma_transfertobusb(uint8 i, uint8 bbus);
+  void dma_transfertobusa(uint8 i, uint8 bbus);
+  void dma_write(uint8 i, uint8 index);
+  void dma_run();
 
-  bool   hdma_active(uint8 i);
-  bool   hdma_active_after(uint8 i);
-  uint8  hdma_enabled_channels();
-  uint8  hdma_active_channels();
-  void   hdma_update(uint8 i);
-  void   hdma_run();
-  void   hdma_init_reset();
-  void   hdma_init();
+  bool hdma_active(uint8 i);
+  bool hdma_active_after(uint8 i);
+  uint8 hdma_enabled_channels();
+  uint8 hdma_active_channels();
+  void hdma_update(uint8 i);
+  void hdma_run();
+  void hdma_init_reset();
+  void hdma_init();
 
-  void   dma_power();
-  void   dma_reset();
+  void dma_power();
+  void dma_reset();

src/cpu/scpu/memory/memory.cpp

@@ -1,3 +1,5 @@
+#ifdef SCPU_CPP
+
 /*****
  * These 3 functions control bus timing for the CPU.
  * cpu_io is an I/O cycle, and always 6 clock cycles long.
@@ -119,3 +121,5 @@ alwaysinline void sCPU::op_writedp(uint32 addr, uint8 data) {
 alwaysinline void sCPU::op_writesp(uint32 addr, uint8 data) {
   op_write((regs.s + (addr & 0xffff)) & 0xffff, data);
 }
+
+#endif //ifdef SCPU_CPP

src/cpu/scpu/memory/memory.h

@@ -1,35 +1,35 @@
-/*****
- * CPU<>APU communication ports
- *****/
-uint8 apu_port[4];
-  uint8  port_read (uint8 port)             { return apu_port[port & 3]; }
-  void   port_write(uint8 port, uint8 data) { apu_port[port & 3] = data; }
+  /*****
+   * CPU<>APU communication ports
+   *****/
+  uint8 apu_port[4];
+  uint8 port_read(uint8 port) { return apu_port[port & 3]; }
+  void port_write(uint8 port, uint8 data) { apu_port[port & 3] = data; }
 
-/*****
- * core CPU bus functions
- *****/
-  void   op_io();
-  uint8  op_read (uint32 addr);
-  void   op_write(uint32 addr, uint8 data);
+  /*****
+   * core CPU bus functions
+   *****/
+  void op_io();
+  uint8 op_read(uint32 addr);
+  void op_write(uint32 addr, uint8 data);
 
-/*****
- * helper memory addressing functions used by CPU core
- *****/
-  uint8  op_readpc    ();
-  uint8  op_readstack ();
-  uint8  op_readstackn();
-  uint8  op_readaddr  (uint32 addr);
-  uint8  op_readlong  (uint32 addr);
-  uint8  op_readdbr   (uint32 addr);
-  uint8  op_readpbr   (uint32 addr);
-  uint8  op_readdp    (uint32 addr);
-  uint8  op_readsp    (uint32 addr);
+  /*****
+   * helper memory addressing functions used by CPU core
+   *****/
+  uint8 op_readpc    ();
+  uint8 op_readstack ();
+  uint8 op_readstackn();
+  uint8 op_readaddr  (uint32 addr);
+  uint8 op_readlong  (uint32 addr);
+  uint8 op_readdbr   (uint32 addr);
+  uint8 op_readpbr   (uint32 addr);
+  uint8 op_readdp    (uint32 addr);
+  uint8 op_readsp    (uint32 addr);
 
-  void   op_writestack (uint8  data);
-  void   op_writestackn(uint8  data);
-  void   op_writeaddr  (uint32 addr, uint8 data);
-  void   op_writelong  (uint32 addr, uint8 data);
-  void   op_writedbr   (uint32 addr, uint8 data);
-  void   op_writepbr   (uint32 addr, uint8 data);
-  void   op_writedp    (uint32 addr, uint8 data);
-  void   op_writesp    (uint32 addr, uint8 data);
+  void op_writestack (uint8  data);
+  void op_writestackn(uint8  data);
+  void op_writeaddr  (uint32 addr, uint8 data);
+  void op_writelong  (uint32 addr, uint8 data);
+  void op_writedbr   (uint32 addr, uint8 data);
+  void op_writepbr   (uint32 addr, uint8 data);
+  void op_writedp    (uint32 addr, uint8 data);
+  void op_writesp    (uint32 addr, uint8 data);

src/cpu/scpu/mmio/mmio.cpp

@@ -1,10 +1,12 @@
+#ifdef SCPU_CPP
+
 uint8 sCPU::pio_status() {
   return status.pio;
 }
 
 //WMDATA
 uint8 sCPU::mmio_r2180() {
-uint8 r = bus.read(0x7e0000 | status.wram_addr);
+  uint8 r = bus.read(0x7e0000 | status.wram_addr);
   status.wram_addr = (status.wram_addr + 1) & 0x01ffff;
   return r;
 }
@@ -41,7 +43,7 @@ void sCPU::mmio_w4016(uint8 data) {
   status.joypad_strobe_latch = !!(data & 1);
 
   if(status.joypad_strobe_latch == 1) {
-    snes.poll_input();
+    snes.input.poll();
   }
 }
 
@@ -52,8 +54,8 @@ void sCPU::mmio_w4016(uint8 data) {
 //TODO: test whether strobe latch of zero returns
 //realtime or buffered status of joypadN.b
 uint8 sCPU::mmio_r4016() {
-uint8 r = regs.mdr & 0xfc;
-  r |= (uint8)snes.port_read(0);
+  uint8 r = regs.mdr & 0xfc;
+  r |= (uint8)snes.input.port_read(0);
   return r;
 }
 
@@ -62,8 +64,8 @@ uint8 r = regs.mdr & 0xfc;
 //4-2 = Always 1 (pins are connected to GND)
 //1-0 = Joypad serial data
 uint8 sCPU::mmio_r4017() {
-uint8 r = (regs.mdr & 0xe0) | 0x1c;
-  r |= (uint8)snes.port_read(1);
+  uint8 r = (regs.mdr & 0xe0) | 0x1c;
+  r |= (uint8)snes.input.port_read(1);
   return r;
 }
 
@@ -167,7 +169,7 @@ void sCPU::mmio_w420d(uint8 data) {
 //6-4 = MDR
 //3-0 = CPU (5a22) version
 uint8 sCPU::mmio_r4210() {
-uint8 r = (regs.mdr & 0x70);
+  uint8 r = (regs.mdr & 0x70);
   r |= (uint8)(rdnmi()) << 7;
   r |= (cpu_version & 0x0f);
   return r;
@@ -177,7 +179,7 @@ uint8 r = (regs.mdr & 0x70);
 //7   = IRQ acknowledge
 //6-0 = MDR
 uint8 sCPU::mmio_r4211() {
-uint8 r = (regs.mdr & 0x7f);
+  uint8 r = (regs.mdr & 0x7f);
   r |= (uint8)(timeup()) << 7;
   return r;
 }
@@ -188,16 +190,16 @@ uint8 r = (regs.mdr & 0x7f);
 //5-1 = MDR
 //0   = JOYPAD acknowledge
 uint8 sCPU::mmio_r4212() {
-uint8 r = (regs.mdr & 0x3e);
-uint16 vs = !overscan() ? 225 : 240;
+  uint8 r = (regs.mdr & 0x3e);
+  uint16 vs = ppu.overscan() == false ? 225 : 240;
 
-//auto joypad polling
+  //auto joypad polling
   if(status.vcounter >= vs && status.vcounter <= (vs + 2))r |= 0x01;
 
-//hblank
-  if(status.hclock <= 2 || status.hclock >= 1096)r |= 0x40;
+  //hblank
+  if(status.hcounter <= 2 || status.hcounter >= 1096)r |= 0x40;
 
-//vblank
+  //vblank
   if(status.vcounter >= vs)r |= 0x80;
 
   return r;
@@ -375,40 +377,40 @@ void sCPU::mmio_power() {
 }
 
 void sCPU::mmio_reset() {
-//$2181-$2183
+  //$2181-$2183
   status.wram_addr = 0x000000;
 
-//$4016-$4017
+  //$4016-$4017
   status.joypad_strobe_latch = 0;
   status.joypad1_bits = ~0;
   status.joypad2_bits = ~0;
 
-//$4200
+  //$4200
   status.nmi_enabled      = false;
   status.hirq_enabled     = false;
   status.virq_enabled     = false;
   status.auto_joypad_poll = false;
 
-//$4201
+  //$4201
   status.pio = 0xff;
 
-//$4202-$4203
+  //$4202-$4203
   status.mul_a = 0xff;
   status.mul_b = 0xff;
 
-//$4204-$4206
+  //$4204-$4206
   status.div_a = 0xffff;
   status.div_b = 0xff;
 
-//$4207-$420a
+  //$4207-$420a
   status.hirq_pos = 0x01ff;
   status.virq_pos = 0x01ff;
 
-//$4214-$4217
+  //$4214-$4217
   status.r4214 = 0x0000;
   status.r4216 = 0x0000;
 
-//$4218-$421f
+  //$4218-$421f
   status.joy1l = 0x00;
   status.joy1h = 0x00;
   status.joy2l = 0x00;
@@ -422,55 +424,55 @@ void sCPU::mmio_reset() {
 uint8 sCPU::mmio_read(uint addr) {
   addr &= 0xffff;
 
-//APU
+  //APU
   if((addr & 0xffc0) == 0x2140) { //$2140-$217f
     scheduler.sync_cpusmp();
     return smp.port_read(addr & 3);
   }
 
-//DMA
+  //DMA
   if((addr & 0xff80) == 0x4300) { //$4300-$437f
-  uint i = (addr >> 4) & 7;
+    uint i = (addr >> 4) & 7;
     switch(addr & 0xf) {
-    case 0x0: return mmio_r43x0(i);
-    case 0x1: return mmio_r43x1(i);
-    case 0x2: return mmio_r43x2(i);
-    case 0x3: return mmio_r43x3(i);
-    case 0x4: return mmio_r43x4(i);
-    case 0x5: return mmio_r43x5(i);
-    case 0x6: return mmio_r43x6(i);
-    case 0x7: return mmio_r43x7(i);
-    case 0x8: return mmio_r43x8(i);
-    case 0x9: return mmio_r43x9(i);
-    case 0xa: return mmio_r43xa(i);
-    case 0xb: return mmio_r43xb(i);
-    case 0xc: return regs.mdr; //unmapped
-    case 0xd: return regs.mdr; //unmapped
-    case 0xe: return regs.mdr; //unmapped
-    case 0xf: return mmio_r43xb(i); //mirror of $43xb
+      case 0x0: return mmio_r43x0(i);
+      case 0x1: return mmio_r43x1(i);
+      case 0x2: return mmio_r43x2(i);
+      case 0x3: return mmio_r43x3(i);
+      case 0x4: return mmio_r43x4(i);
+      case 0x5: return mmio_r43x5(i);
+      case 0x6: return mmio_r43x6(i);
+      case 0x7: return mmio_r43x7(i);
+      case 0x8: return mmio_r43x8(i);
+      case 0x9: return mmio_r43x9(i);
+      case 0xa: return mmio_r43xa(i);
+      case 0xb: return mmio_r43xb(i);
+      case 0xc: return regs.mdr; //unmapped
+      case 0xd: return regs.mdr; //unmapped
+      case 0xe: return regs.mdr; //unmapped
+      case 0xf: return mmio_r43xb(i); //mirror of $43xb
     }
   }
 
   switch(addr) {
-  case 0x2180: return mmio_r2180();
-  case 0x4016: return mmio_r4016();
-  case 0x4017: return mmio_r4017();
-  case 0x4210: return mmio_r4210();
-  case 0x4211: return mmio_r4211();
-  case 0x4212: return mmio_r4212();
-  case 0x4213: return mmio_r4213();
-  case 0x4214: return mmio_r4214();
-  case 0x4215: return mmio_r4215();
-  case 0x4216: return mmio_r4216();
-  case 0x4217: return mmio_r4217();
-  case 0x4218: return mmio_r4218();
-  case 0x4219: return mmio_r4219();
-  case 0x421a: return mmio_r421a();
-  case 0x421b: return mmio_r421b();
-  case 0x421c: return mmio_r421c();
-  case 0x421d: return mmio_r421d();
-  case 0x421e: return mmio_r421e();
-  case 0x421f: return mmio_r421f();
+    case 0x2180: return mmio_r2180();
+    case 0x4016: return mmio_r4016();
+    case 0x4017: return mmio_r4017();
+    case 0x4210: return mmio_r4210();
+    case 0x4211: return mmio_r4211();
+    case 0x4212: return mmio_r4212();
+    case 0x4213: return mmio_r4213();
+    case 0x4214: return mmio_r4214();
+    case 0x4215: return mmio_r4215();
+    case 0x4216: return mmio_r4216();
+    case 0x4217: return mmio_r4217();
+    case 0x4218: return mmio_r4218();
+    case 0x4219: return mmio_r4219();
+    case 0x421a: return mmio_r421a();
+    case 0x421b: return mmio_r421b();
+    case 0x421c: return mmio_r421c();
+    case 0x421d: return mmio_r421d();
+    case 0x421e: return mmio_r421e();
+    case 0x421f: return mmio_r421f();
   }
 
   return regs.mdr;
@@ -479,56 +481,58 @@ uint8 sCPU::mmio_read(uint addr) {
 void sCPU::mmio_write(uint addr, uint8 data) {
   addr &= 0xffff;
 
-//APU
+  //APU
   if((addr & 0xffc0) == 0x2140) { //$2140-$217f
     scheduler.sync_cpusmp();
     port_write(addr & 3, data);
     return;
   }
 
-//DMA
+  //DMA
   if((addr & 0xff80) == 0x4300) { //$4300-$437f
   uint i = (addr >> 4) & 7;
     switch(addr & 0xf) {
-    case 0x0: mmio_w43x0(i, data); return;
-    case 0x1: mmio_w43x1(i, data); return;
-    case 0x2: mmio_w43x2(i, data); return;
-    case 0x3: mmio_w43x3(i, data); return;
-    case 0x4: mmio_w43x4(i, data); return;
-    case 0x5: mmio_w43x5(i, data); return;
-    case 0x6: mmio_w43x6(i, data); return;
-    case 0x7: mmio_w43x7(i, data); return;
-    case 0x8: mmio_w43x8(i, data); return;
-    case 0x9: mmio_w43x9(i, data); return;
-    case 0xa: mmio_w43xa(i, data); return;
-    case 0xb: mmio_w43xb(i, data); return;
-    case 0xc: return; //unmapped
-    case 0xd: return; //unmapped
-    case 0xe: return; //unmapped
-    case 0xf: mmio_w43xb(i, data); return; //mirror of $43xb
+      case 0x0: mmio_w43x0(i, data); return;
+      case 0x1: mmio_w43x1(i, data); return;
+      case 0x2: mmio_w43x2(i, data); return;
+      case 0x3: mmio_w43x3(i, data); return;
+      case 0x4: mmio_w43x4(i, data); return;
+      case 0x5: mmio_w43x5(i, data); return;
+      case 0x6: mmio_w43x6(i, data); return;
+      case 0x7: mmio_w43x7(i, data); return;
+      case 0x8: mmio_w43x8(i, data); return;
+      case 0x9: mmio_w43x9(i, data); return;
+      case 0xa: mmio_w43xa(i, data); return;
+      case 0xb: mmio_w43xb(i, data); return;
+      case 0xc: return; //unmapped
+      case 0xd: return; //unmapped
+      case 0xe: return; //unmapped
+      case 0xf: mmio_w43xb(i, data); return; //mirror of $43xb
     }
   }
 
   switch(addr) {
-  case 0x2180: mmio_w2180(data); return;
-  case 0x2181: mmio_w2181(data); return;
-  case 0x2182: mmio_w2182(data); return;
-  case 0x2183: mmio_w2183(data); return;
-  case 0x4016: mmio_w4016(data); return;
-  case 0x4017: return; //unmapped
-  case 0x4200: mmio_w4200(data); return;
-  case 0x4201: mmio_w4201(data); return;
-  case 0x4202: mmio_w4202(data); return;
-  case 0x4203: mmio_w4203(data); return;
-  case 0x4204: mmio_w4204(data); return;
-  case 0x4205: mmio_w4205(data); return;
-  case 0x4206: mmio_w4206(data); return;
-  case 0x4207: mmio_w4207(data); return;
-  case 0x4208: mmio_w4208(data); return;
-  case 0x4209: mmio_w4209(data); return;
-  case 0x420a: mmio_w420a(data); return;
-  case 0x420b: mmio_w420b(data); return;
-  case 0x420c: mmio_w420c(data); return;
-  case 0x420d: mmio_w420d(data); return;
+    case 0x2180: mmio_w2180(data); return;
+    case 0x2181: mmio_w2181(data); return;
+    case 0x2182: mmio_w2182(data); return;
+    case 0x2183: mmio_w2183(data); return;
+    case 0x4016: mmio_w4016(data); return;
+    case 0x4017: return; //unmapped
+    case 0x4200: mmio_w4200(data); return;
+    case 0x4201: mmio_w4201(data); return;
+    case 0x4202: mmio_w4202(data); return;
+    case 0x4203: mmio_w4203(data); return;
+    case 0x4204: mmio_w4204(data); return;
+    case 0x4205: mmio_w4205(data); return;
+    case 0x4206: mmio_w4206(data); return;
+    case 0x4207: mmio_w4207(data); return;
+    case 0x4208: mmio_w4208(data); return;
+    case 0x4209: mmio_w4209(data); return;
+    case 0x420a: mmio_w420a(data); return;
+    case 0x420b: mmio_w420b(data); return;
+    case 0x420c: mmio_w420c(data); return;
+    case 0x420d: mmio_w420d(data); return;
   }
 }
+
+#endif //ifdef SCPU_CPP

src/cpu/scpu/mmio/mmio.h

@@ -1,70 +1,70 @@
-  void   mmio_power();
-  void   mmio_reset();
-  uint8  mmio_read (uint addr);
-  void   mmio_write(uint addr, uint8 data);
+  void mmio_power();
+  void mmio_reset();
+  uint8 mmio_read(uint addr);
+  void mmio_write(uint addr, uint8 data);
 
-  uint8  pio_status();
+  uint8 pio_status();
 
-  uint8  mmio_r2180();
-  uint8  mmio_r4016();
-  uint8  mmio_r4017();
-  uint8  mmio_r4210();
-  uint8  mmio_r4211();
-  uint8  mmio_r4212();
-  uint8  mmio_r4213();
-  uint8  mmio_r4214();
-  uint8  mmio_r4215();
-  uint8  mmio_r4216();
-  uint8  mmio_r4217();
-  uint8  mmio_r4218();
-  uint8  mmio_r4219();
-  uint8  mmio_r421a();
-  uint8  mmio_r421b();
-  uint8  mmio_r421c();
-  uint8  mmio_r421d();
-  uint8  mmio_r421e();
-  uint8  mmio_r421f();
-  uint8  mmio_r43x0(uint8 i);
-  uint8  mmio_r43x1(uint8 i);
-  uint8  mmio_r43x2(uint8 i);
-  uint8  mmio_r43x3(uint8 i);
-  uint8  mmio_r43x4(uint8 i);
-  uint8  mmio_r43x5(uint8 i);
-  uint8  mmio_r43x6(uint8 i);
-  uint8  mmio_r43x7(uint8 i);
-  uint8  mmio_r43x8(uint8 i);
-  uint8  mmio_r43x9(uint8 i);
-  uint8  mmio_r43xa(uint8 i);
-  uint8  mmio_r43xb(uint8 i);
+  uint8 mmio_r2180();
+  uint8 mmio_r4016();
+  uint8 mmio_r4017();
+  uint8 mmio_r4210();
+  uint8 mmio_r4211();
+  uint8 mmio_r4212();
+  uint8 mmio_r4213();
+  uint8 mmio_r4214();
+  uint8 mmio_r4215();
+  uint8 mmio_r4216();
+  uint8 mmio_r4217();
+  uint8 mmio_r4218();
+  uint8 mmio_r4219();
+  uint8 mmio_r421a();
+  uint8 mmio_r421b();
+  uint8 mmio_r421c();
+  uint8 mmio_r421d();
+  uint8 mmio_r421e();
+  uint8 mmio_r421f();
+  uint8 mmio_r43x0(uint8 i);
+  uint8 mmio_r43x1(uint8 i);
+  uint8 mmio_r43x2(uint8 i);
+  uint8 mmio_r43x3(uint8 i);
+  uint8 mmio_r43x4(uint8 i);
+  uint8 mmio_r43x5(uint8 i);
+  uint8 mmio_r43x6(uint8 i);
+  uint8 mmio_r43x7(uint8 i);
+  uint8 mmio_r43x8(uint8 i);
+  uint8 mmio_r43x9(uint8 i);
+  uint8 mmio_r43xa(uint8 i);
+  uint8 mmio_r43xb(uint8 i);
 
-  void   mmio_w2180(uint8 data);
-  void   mmio_w2181(uint8 data);
-  void   mmio_w2182(uint8 data);
-  void   mmio_w2183(uint8 data);
-  void   mmio_w4016(uint8 data);
-  void   mmio_w4200(uint8 data);
-  void   mmio_w4201(uint8 data);
-  void   mmio_w4202(uint8 data);
-  void   mmio_w4203(uint8 data);
-  void   mmio_w4204(uint8 data);
-  void   mmio_w4205(uint8 data);
-  void   mmio_w4206(uint8 data);
-  void   mmio_w4207(uint8 data);
-  void   mmio_w4208(uint8 data);
-  void   mmio_w4209(uint8 data);
-  void   mmio_w420a(uint8 data);
-  void   mmio_w420b(uint8 data);
-  void   mmio_w420c(uint8 data);
-  void   mmio_w420d(uint8 data);
-  void   mmio_w43x0(uint8 i, uint8 data);
-  void   mmio_w43x1(uint8 i, uint8 data);
-  void   mmio_w43x2(uint8 i, uint8 data);
-  void   mmio_w43x3(uint8 i, uint8 data);
-  void   mmio_w43x4(uint8 i, uint8 data);
-  void   mmio_w43x5(uint8 i, uint8 data);
-  void   mmio_w43x6(uint8 i, uint8 data);
-  void   mmio_w43x7(uint8 i, uint8 data);
-  void   mmio_w43x8(uint8 i, uint8 data);
-  void   mmio_w43x9(uint8 i, uint8 data);
-  void   mmio_w43xa(uint8 i, uint8 data);
-  void   mmio_w43xb(uint8 i, uint8 data);
+  void mmio_w2180(uint8 data);
+  void mmio_w2181(uint8 data);
+  void mmio_w2182(uint8 data);
+  void mmio_w2183(uint8 data);
+  void mmio_w4016(uint8 data);
+  void mmio_w4200(uint8 data);
+  void mmio_w4201(uint8 data);
+  void mmio_w4202(uint8 data);
+  void mmio_w4203(uint8 data);
+  void mmio_w4204(uint8 data);
+  void mmio_w4205(uint8 data);
+  void mmio_w4206(uint8 data);
+  void mmio_w4207(uint8 data);
+  void mmio_w4208(uint8 data);
+  void mmio_w4209(uint8 data);
+  void mmio_w420a(uint8 data);
+  void mmio_w420b(uint8 data);
+  void mmio_w420c(uint8 data);
+  void mmio_w420d(uint8 data);
+  void mmio_w43x0(uint8 i, uint8 data);
+  void mmio_w43x1(uint8 i, uint8 data);
+  void mmio_w43x2(uint8 i, uint8 data);
+  void mmio_w43x3(uint8 i, uint8 data);
+  void mmio_w43x4(uint8 i, uint8 data);
+  void mmio_w43x5(uint8 i, uint8 data);
+  void mmio_w43x6(uint8 i, uint8 data);
+  void mmio_w43x7(uint8 i, uint8 data);
+  void mmio_w43x8(uint8 i, uint8 data);
+  void mmio_w43x9(uint8 i, uint8 data);
+  void mmio_w43xa(uint8 i, uint8 data);
+  void mmio_w43xb(uint8 i, uint8 data);

src/cpu/scpu/scpu.cpp

@@ -1,4 +1,5 @@
-#include "../../base.h"
+#include "../../base.h"
+#define SCPU_CPP
 
 #include "core/core.cpp"
 #include "dma/dma.cpp"
@@ -7,8 +8,6 @@
 #include "timing/timing.cpp"
 
 void sCPU::power() {
-  status.region = (bool)snes.region();
-
   regs.a = regs.x = regs.y = 0x0000;
   regs.s = 0x01ff;
 
@@ -24,7 +23,7 @@ void sCPU::reset() {
   regs.pc.l = bus.read(0xfffc);
   regs.pc.h = bus.read(0xfffd);
 
-//note: some registers are not fully reset by SNES
+  //note: some registers are not fully reset by SNES
   regs.x.h  = 0x00;
   regs.y.h  = 0x00;
   regs.s.h  = 0x01;
@@ -49,7 +48,6 @@ void sCPU::reset() {
 }
 
 sCPU::sCPU() {
-  #include "core/optable.cpp"
 }
 
 sCPU::~sCPU() {

src/cpu/scpu/scpu.h

@@ -1,138 +1,132 @@
-class sCPU : public CPU { public:
+class sCPU : public CPU {
+public:
   void enter();
 
-#include "core/core.h"
-#include "dma/dma.h"
-#include "memory/memory.h"
-#include "mmio/mmio.h"
-#include "timing/timing.h"
+  #include "core/core.h"
+  #include "dma/dma.h"
+  #include "memory/memory.h"
+  #include "mmio/mmio.h"
+  #include "timing/timing.h"
 
-struct {
-  bool   wai;
-  bool   irq;
-  uint16 irq_vector;
-} event;
+  struct {
+    bool wai;
+    bool irq;
+    uint16 irq_vector;
+  } event;
 
-struct {
-  uint   nmi_hold;
-  uint   irq_hold;
+  struct {
+    uint   nmi_hold;
+    uint   irq_hold;
 
-  uint   nmi_fire;
-  uint   irq_fire;
-  uint   irq_delay;
-  uint   hw_math;
+    uint   nmi_fire;
+    uint   irq_fire;
+    uint   irq_delay;
+    uint   hw_math;
 
-  alwaysinline void set(uint &ctr, uint clocks) {
-    if(clocks >= ctr) { ctr = clocks; }
-  }
-
-  alwaysinline void sub(uint &ctr, uint clocks) {
-    if(ctr >= clocks) {
-      ctr -= clocks;
-    } else {
-      ctr  = 0;
+    alwaysinline void set(uint &ctr, uint clocks) {
+      if(clocks >= ctr) { ctr = clocks; }
     }
-  }
-} counter;
 
-enum {
-  DMASTATE_INACTIVE,
-  DMASTATE_DMASYNC,
-  DMASTATE_RUN,
-  DMASTATE_CPUSYNC,
-};
+    alwaysinline void sub(uint &ctr, uint clocks) {
+      if(ctr >= clocks) {
+        ctr -= clocks;
+      } else {
+        ctr  = 0;
+      }
+    }
+  } counter;
 
-struct {
-//core
-  uint8  opcode;
-  bool   in_opcode;
+  enum {
+    DMASTATE_INACTIVE,
+    DMASTATE_DMASYNC,
+    DMASTATE_RUN,
+    DMASTATE_CPUSYNC,
+  };
 
-  uint   clock_count;
+  struct {
+    //core
+    uint8  opcode;
+    bool   in_opcode;
 
-//timing
-  bool   region;
-  uint16 region_scanlines;
-  uint16 vcounter, hcounter, hclock;
-  bool   interlace, interlace_field;
-  bool   overscan;
-  uint16 field_lines, line_clocks;
-  uint16 prev_field_lines, prev_line_clocks;
-  uint16 vblstart;
+    uint   clock_count;
 
-  bool   line_rendered;
-  uint16 line_render_position;
+    //timing
+    uint16 vcounter, hcounter;
+    uint16 field_lines, line_clocks;
 
-  bool   dram_refreshed;
-  uint16 dram_refresh_position;
+    bool   line_rendered;
+    uint16 line_render_position;
 
-  bool   hdmainit_triggered;
-  uint16 hdmainit_trigger_position;
+    bool   dram_refreshed;
+    uint16 dram_refresh_position;
 
-  bool   hdma_triggered;
+    bool   hdmainit_triggered;
+    uint16 hdmainit_trigger_position;
 
-  uint16 irq_delay;
+    bool   hdma_triggered;
 
-  uint16 vnmi_trigger_pos;
-  bool   nmi_valid;
-  bool   nmi_line;
-  bool   nmi_transition;
-  bool   nmi_pending;
+    uint16 irq_delay;
 
-  uint16 virq_trigger_pos, hirq_trigger_pos;
-  bool   irq_valid;
-  bool   irq_line;
-  bool   irq_transition;
-  bool   irq_pending;
+    bool   nmi_valid;
+    bool   nmi_line;
+    bool   nmi_transition;
+    bool   nmi_pending;
 
-//dma
-  uint   dma_counter;
-  uint   dma_clocks;
-  uint   dma_state;
-  bool   dma_pending;
-  bool   hdma_pending;
-  bool   hdmainit_pending;
+    uint16 virq_trigger_pos, hirq_trigger_pos;
+    bool   irq_valid;
+    bool   irq_line;
+    bool   irq_transition;
+    bool   irq_pending;
 
-//mmio
+    //dma
+    uint   dma_counter;
+    uint   dma_clocks;
+    uint   dma_state;
+    bool   dma_pending;
+    bool   hdma_pending;
+    bool   hdmainit_pending;
 
-//$2181-$2183
-  uint32 wram_addr;
+    //mmio
 
-//$4016-$4017
-  bool   joypad_strobe_latch;
-  uint32 joypad1_bits;
-  uint32 joypad2_bits;
+    //$2181-$2183
+    uint32 wram_addr;
 
-//$4200
-  bool   nmi_enabled;
-  bool   hirq_enabled, virq_enabled;
-  bool   auto_joypad_poll;
+    //$4016-$4017
+    bool   joypad_strobe_latch;
+    uint32 joypad1_bits;
+    uint32 joypad2_bits;
 
-//$4201
-  uint8  pio;
+    //$4200
+    bool   nmi_enabled;
+    bool   hirq_enabled, virq_enabled;
+    bool   auto_joypad_poll;
 
-//$4202-$4203
-  uint8  mul_a, mul_b;
+    //$4201
+    uint8  pio;
 
-//$4204-$4206
-  uint16 div_a;
-  uint8  div_b;
+    //$4202-$4203
+    uint8  mul_a, mul_b;
 
-//$4207-$420a
-  uint16 hirq_pos, virq_pos;
+    //$4204-$4206
+    uint16 div_a;
+    uint8  div_b;
 
-//$4214-$4217
-  uint16 r4214;
-  uint16 r4216;
+    //$4207-$420a
+    uint16 hirq_pos, virq_pos;
 
-//$4218-$421f
-  uint8  joy1l, joy1h;
-  uint8  joy2l, joy2h;
-  uint8  joy3l, joy3h;
-  uint8  joy4l, joy4h;
-} status;
+    //$4214-$4217
+    uint16 r4214;
+    uint16 r4216;
 
-  void   power();
-  void   reset();
+    //$4218-$421f
+    uint8  joy1l, joy1h;
+    uint8  joy2l, joy2h;
+    uint8  joy3l, joy3h;
+    uint8  joy4l, joy4h;
+  } status;
+
+  void power();
+  void reset();
 
   sCPU();
   ~sCPU();

src/cpu/scpu/timing/irq.cpp

@@ -1,60 +1,137 @@
-#include "irqtiming.cpp"
-
-bool sCPU::irq_pos_valid() {
-uint vpos   = status.virq_pos;
-uint hpos   = (status.hirq_enabled) ? status.hirq_pos : 0;
-uint vlimit = region_scanlines() >> 1;
-//positions that can never be latched
-//vlimit = 262/NTSC, 312/PAL
-//PAL results are unverified on hardware
-  if(vpos == 240 && hpos == 339 && interlace() == false && interlace_field() == 1)return false;
-  if(vpos == (vlimit - 1) && hpos == 339 && interlace() == false)return false;
-  if(vpos == vlimit && interlace() == false)return false;
-  if(vpos == vlimit && hpos == 339)return false;
-  if(vpos  > vlimit)return false;
-  if(hpos  > 339)return false;
-
-  return true;
+#ifdef SCPU_CPP
+
+void sCPU::update_interrupts() {
+  if(irq_pos_valid() == true) {
+    status.virq_trigger_pos = status.virq_pos;
+    status.hirq_trigger_pos = 4 * ((status.hirq_enabled) ? (status.hirq_pos + 1) : 0);
+  } else {
+    status.virq_trigger_pos = IRQ_TRIGGER_NEVER;
+    status.hirq_trigger_pos = IRQ_TRIGGER_NEVER;
+  }
 }
 
-alwaysinline
-bool sCPU::nmi_test() {
-  if(status.nmi_transition == false) { return false; }
-  status.nmi_transition = false;
+alwaysinline void sCPU::poll_interrupts() {
+  uint16_t vpos, hpos;
 
-  event.wai = false;
-  return true;
-}
-
-alwaysinline
-bool sCPU::irq_test() {
-  if(status.irq_transition == false) { return false; }
-  status.irq_transition = false;
-
-  event.wai = false;
-  return (regs.p.i) ? false : true;
-}
-
-/*
-  if(status.irq_transition == 1)goto irq_trigger;
-
-  if(status.irq_read == 0) {
-    if(status.irq_line == 1 && irq_edge()) {
-      return false;
+  //NMI hold
+  if(counter.nmi_hold) {
+    counter.nmi_hold -= 2;
+    if(counter.nmi_hold == 0) {
+      if(status.nmi_enabled == true) status.nmi_transition = true;
     }
-    goto irq_trigger;
   }
 
-  if(status.irq_line == 0) {
-    status.irq_line = 1;
-    goto irq_trigger;
+  //NMI test
+  history.query(2, vpos, hpos);
+  bool nmi_valid = (vpos >= (!ppu.overscan() ? 225 : 240));
+  if(status.nmi_valid == false && nmi_valid == true) {
+    //0->1 edge sensitive transition
+    status.nmi_line = true;
+    counter.nmi_hold = 4;
+  } else if(status.nmi_valid == true && nmi_valid == false) {
+    //1->0 edge sensitive transition
+    status.nmi_line = false;
+  }
+  status.nmi_valid = nmi_valid;
+
+  //IRQ hold
+  if(counter.irq_hold) counter.irq_hold -= 2;
+  if(status.irq_line == true && counter.irq_hold == 0) {
+    if(status.virq_enabled == true || status.hirq_enabled == true) status.irq_transition = true;
   }
 
-  return false;
-
-irq_trigger:
-  status.irq_transition = 0;
-  event.wai = false;
-  return (regs.p.i) ? false : true;
+  //IRQ test
+  history.query(10, vpos, hpos);
+  bool irq_valid = (status.virq_enabled == true || status.hirq_enabled == true);
+  if(irq_valid == true) {
+    if(status.virq_enabled == true && vpos != status.virq_trigger_pos) irq_valid = false;
+    if(status.hirq_enabled == true && hpos != status.hirq_trigger_pos) irq_valid = false;
+  }
+  if(status.irq_valid == false && irq_valid == true) {
+    //0->1 edge sensitive transition
+    status.irq_line = true;
+    counter.irq_hold = 4;
+  }
+  status.irq_valid = irq_valid;
 }
-*/
+
+void sCPU::nmitimen_update(uint8 data) {
+  bool nmi_enabled  = status.nmi_enabled;
+  bool virq_enabled = status.virq_enabled;
+  bool hirq_enabled = status.hirq_enabled;
+  status.nmi_enabled  = !!(data & 0x80);
+  status.virq_enabled = !!(data & 0x20);
+  status.hirq_enabled = !!(data & 0x10);
+
+  //0->1 edge sensitive transition
+  if(nmi_enabled == false && status.nmi_enabled == true && status.nmi_line == true) {
+    status.nmi_transition = true;
+  }
+
+  //?->1 level sensitive transition
+  if(status.virq_enabled == true && status.hirq_enabled == false && status.irq_line == true) {
+    status.irq_transition = true;
+  }
+
+  if(status.virq_enabled == false && status.hirq_enabled == false) {
+    status.irq_line = false;
+    status.irq_transition = false;
+  }
+
+  update_interrupts();
+  counter.set(counter.irq_delay, 2);
+}
+
+void sCPU::hvtime_update(uint16 addr) {
+  update_interrupts();
+}
+
+bool sCPU::rdnmi() {
+  bool result = status.nmi_line;
+  if(counter.nmi_hold == 0) {
+    status.nmi_line = false;
+  }
+  return result;
+}
+
+bool sCPU::timeup() {
+  bool result = status.irq_line;
+  if(counter.irq_hold == 0) {
+    status.irq_line = false;
+    status.irq_transition = false;
+  }
+  return result;
+}
+
+bool sCPU::irq_pos_valid() {
+  uint vpos = status.virq_pos;
+  uint hpos = (status.hirq_enabled) ? status.hirq_pos : 0;
+  uint vlimit = (snes.region() == SNES::NTSC ? 525 : 625) >> 1;
+  //positions that can never be latched
+  //vlimit = 262/NTSC, 312/PAL
+  //PAL results are unverified on hardware
+  if(vpos == 240 && hpos == 339 && ppu.interlace() == false && ppu.field() == 1) return false;
+  if(vpos == (vlimit - 1) && hpos == 339 && ppu.interlace() == false) return false;
+  if(vpos == vlimit && ppu.interlace() == false) return false;
+  if(vpos == vlimit && hpos == 339) return false;
+  if(vpos  > vlimit) return false;
+  if(hpos  > 339) return false;
+
+  return true;
+}
+
+alwaysinline bool sCPU::nmi_test() {
+  if(status.nmi_transition == false) return false;
+  status.nmi_transition = false;
+  event.wai = false;
+  return true;
+}
+
+alwaysinline bool sCPU::irq_test() {
+  if(status.irq_transition == false) return false;
+  status.irq_transition = false;
+  event.wai = false;
+  return regs.p.i ? false : true;
+}
+
+#endif //ifdef SCPU_CPP

src/cpu/scpu/timing/irqtiming.cpp

@@ -1,105 +0,0 @@
-void sCPU::update_interrupts() {
-  status.vnmi_trigger_pos = status.vblstart;
-
-  if(irq_pos_valid() == true) {
-    status.virq_trigger_pos = status.virq_pos;
-    status.hirq_trigger_pos = 4 * ((status.hirq_enabled) ? (status.hirq_pos + 1) : 0);
-  } else {
-    status.virq_trigger_pos = IRQ_TRIGGER_NEVER;
-    status.hirq_trigger_pos = IRQ_TRIGGER_NEVER;
-  }
-}
-
-alwaysinline
-void sCPU::poll_interrupts() {
-uint vpos = status.vcounter, hpos = status.hclock;
-
-//NMI test
-  timeshift_backward(2, vpos, hpos);
-bool nmi_valid = (vpos >= status.vnmi_trigger_pos);
-  if(status.nmi_valid == false && nmi_valid == true) {
-  //0->1 edge sensitive transition
-    status.nmi_line = true;
-    counter.nmi_hold = 6;
-  } else if(status.nmi_valid == true && nmi_valid == false) {
-  //1->0 edge sensitive transition
-    status.nmi_line = false;
-  }
-  status.nmi_valid = nmi_valid;
-
-//NMI hold
-  if(counter.nmi_hold) {
-    counter.nmi_hold -= 2;
-    if(counter.nmi_hold == 0) {
-      if(status.nmi_enabled == true) { status.nmi_transition = true; }
-    }
-  }
-
-//IRQ test
-  timeshift_backward(8, vpos, hpos);
-bool irq_valid = (status.virq_enabled == true || status.hirq_enabled == true);
-  if(irq_valid == true) {
-    if(status.virq_enabled == true && vpos != status.virq_trigger_pos) { irq_valid = false; }
-    if(status.hirq_enabled == true && hpos != status.hirq_trigger_pos) { irq_valid = false; }
-  }
-  if(status.irq_valid == false && irq_valid == true) {
-  //0->1 edge sensitive transition
-    status.irq_line = true;
-    counter.irq_hold = 6;
-  }
-  status.irq_valid = irq_valid;
-
-//IRQ hold
-  if(counter.irq_hold) { counter.irq_hold -= 2; }
-  if(status.irq_line == true && counter.irq_hold == 0) {
-    if(status.virq_enabled == true || status.hirq_enabled == true) { status.irq_transition = true; }
-  }
-}
-
-void sCPU::nmitimen_update(uint8 data) {
-bool nmi_enabled  = status.nmi_enabled;
-bool virq_enabled = status.virq_enabled;
-bool hirq_enabled = status.hirq_enabled;
-  status.nmi_enabled  = !!(data & 0x80);
-  status.virq_enabled = !!(data & 0x20);
-  status.hirq_enabled = !!(data & 0x10);
-
-//0->1 edge sensitive transition
-  if(nmi_enabled == false && status.nmi_enabled == true && status.nmi_line == true) {
-    status.nmi_transition = true;
-  }
-
-//?->1 level sensitive transition
-  if(status.virq_enabled == true && status.hirq_enabled == false && status.irq_line == true) {
-    status.irq_transition = true;
-  }
-
-  if(status.virq_enabled == false && status.hirq_enabled == false) {
-    status.irq_line = false;
-    status.irq_transition = false;
-  }
-
-  update_interrupts();
-  counter.set(counter.irq_delay, 2);
-}
-
-void sCPU::hvtime_update(uint16 addr) {
-  update_interrupts();
-}
-
-bool sCPU::rdnmi() {
-bool result = status.nmi_line;
-  if(counter.nmi_hold == 0) {
-    status.nmi_line = false;
-  }
-  return result;
-}
-
-bool sCPU::timeup() {
-bool result = status.irq_line;
-  if(counter.irq_hold == 0) {
-    status.irq_line = false;
-    status.irq_transition = false;
-  }
-  return result;
-}

src/cpu/scpu/timing/joypad.cpp

@@ -1,8 +1,10 @@
+#ifdef SCPU_CPP
+
 void sCPU::run_auto_joypad_poll() {
-uint16 joy1 = 0, joy2 = 0;
-  for(int i = 0; i < 16; i++) {
-    joy1 |= (uint16)snes.port_read(0) ? (0x8000 >> i) : 0;
-    joy2 |= (uint16)snes.port_read(1) ? (0x8000 >> i) : 0;
+  uint16_t joy1 = 0, joy2 = 0;
+  for(unsigned i = 0; i < 16; i++) {
+    joy1 |= (uint16_t)snes.input.port_read(0) ? (0x8000 >> i) : 0;
+    joy2 |= (uint16_t)snes.input.port_read(1) ? (0x8000 >> i) : 0;
   }
 
   status.joy1l = joy1;
@@ -17,3 +19,5 @@ uint16 joy1 = 0, joy2 = 0;
   status.joy4l = 0x00;
   status.joy4h = 0x00;
 }
+
+#endif //ifdef SCPU_CPP

src/cpu/scpu/timing/timeshift.cpp

@@ -1,22 +0,0 @@
-alwaysinline void sCPU::timeshift_forward(uint clocks, uint &vtime, uint &htime) {
-  htime += clocks;
-  if(htime >= status.line_clocks) {
-    htime -= status.line_clocks;
-    if(++vtime >= status.field_lines) {
-      vtime = 0;
-    }
-  }
-}
-
-alwaysinline void sCPU::timeshift_backward(uint clocks, uint &vtime, uint &htime) {
-  if(htime >= clocks) {
-    htime -= clocks;
-  } else {
-    htime += status.prev_line_clocks - clocks;
-    if(vtime > 0) {
-      vtime--;
-    } else {
-      vtime = status.prev_field_lines - 1;
-    }
-  }
-}

src/cpu/scpu/timing/timing.cpp

@@ -1,31 +1,16 @@
-#define ntsc_color_burst_phase_shift_scanline() \
-  (status.region == SNES::NTSC && status.vcounter == 240 && \
-   status.interlace == false && status.interlace_field == 1)
+#ifdef SCPU_CPP
+
+#define ntsc_color_burst_phase_shift_scanline() ( \
+  snes.region() == SNES::NTSC && status.vcounter == 240 && \
+  ppu.interlace() == false && ppu.field() == 1 \
+)
 
-#include "timeshift.cpp"
 #include "irq.cpp"
 #include "joypad.cpp"
 
-uint16 sCPU::vcounter() { return status.vcounter; }
-uint16 sCPU::hclock()   { return status.hclock;   }
-
-bool   sCPU::interlace()        { return status.interlace;        }
-bool   sCPU::interlace_field()  { return status.interlace_field;  }
-bool   sCPU::overscan()         { return status.overscan;         }
-uint16 sCPU::region_scanlines() { return status.region_scanlines; }
-
-uint   sCPU::dma_counter() { return (status.dma_counter + status.hclock) & 7; }
-
-void sCPU::set_interlace(bool r) {
-  status.interlace = r;
-  update_interrupts();
-}
-
-void sCPU::set_overscan (bool r) {
-  status.overscan = r;
-  status.vblstart = (status.overscan == false) ? 225 : 240;
-  update_interrupts();
-}
+uint16 sCPU::vcounter()  { return status.vcounter; }
+uint16 sCPU::hcounter()  { return status.hcounter; }
+uint sCPU::dma_counter() { return (status.dma_counter + status.hcounter) & 7; }
 
 /*****
  * One PPU dot = 4 CPU clocks
@@ -37,16 +22,14 @@ void sCPU::set_overscan (bool r) {
  * Dot 323 range = { 1292, 1294, 1296 }
  * Dot 327 range = { 1310, 1312, 1314 }
  *****/
-uint16 sCPU::hcounter() {
-  if(ntsc_color_burst_phase_shift_scanline() == true) {
-    return (status.hclock >> 2);
-  }
-  return (status.hclock - ((status.hclock > 1292) << 1) - ((status.hclock > 1310) << 1)) >> 2;
+uint16 sCPU::hdot() {
+  if(ntsc_color_burst_phase_shift_scanline() == true) return (status.hcounter >> 2);
+  return (status.hcounter - ((status.hcounter > 1292) << 1) - ((status.hcounter > 1310) << 1)) >> 2;
 }
 
 void sCPU::add_clocks(uint clocks) {
   if(status.dram_refreshed == false) {
-    if(status.hclock + clocks >= status.dram_refresh_position) {
+    if(status.hcounter + clocks >= status.dram_refresh_position) {
       status.dram_refreshed = true;
       clocks += 40;
     }
@@ -56,25 +39,21 @@ void sCPU::add_clocks(uint clocks) {
   scheduler.addclocks_cpu(clocks);
 
   clocks >>= 1;
-  while(clocks--) {
-    status.hclock += 2;
-    if(status.hclock >= status.line_clocks) { scanline(); }
+  while(clocks--) {
+    history.enqueue(status.vcounter, status.hcounter);
+    status.hcounter += 2;
+    if(status.hcounter >= status.line_clocks) scanline();
     poll_interrupts();
   }
 }
 
 void sCPU::scanline() {
-  status.hclock = 0;
+  status.hcounter = 0;
   status.dma_counter = (status.dma_counter + status.line_clocks) & 7;
-
-  if(++status.vcounter >= status.field_lines) {
-    frame();
-  }
-
-  status.prev_line_clocks = status.line_clocks;
+  if(++status.vcounter >= status.field_lines) frame();
   status.line_clocks = (ntsc_color_burst_phase_shift_scanline() == false) ? 1364 : 1360;
 
-//dram refresh occurs once every scanline
+  //dram refresh occurs once every scanline
   status.dram_refreshed = false;
   if(cpu_version == 2) {
     if(ntsc_color_burst_phase_shift_scanline() == false) {
@@ -86,29 +65,30 @@ void sCPU::scanline() {
     }
   }
 
-//hdma triggers once every visible scanline
+  //hdma triggers once every visible scanline
   status.line_rendered  = false;
-  status.hdma_triggered = (status.vcounter <= (!overscan() ? 224 : 239)) ? false : true;
+  status.hdma_triggered = (status.vcounter <= (ppu.overscan() == false ? 224 : 239)) ? false : true;
 
   ppu.scanline();
   snes.scanline();
 
   update_interrupts();
 
-  if(status.auto_joypad_poll == true && status.vcounter == (!overscan() ? 227 : 242)) {
-    snes.poll_input();
+  if(status.auto_joypad_poll == true && status.vcounter == (ppu.overscan() == false ? 227 : 242)) {
+    snes.input.poll();
     run_auto_joypad_poll();
   }
 }
 
-void sCPU::frame() {
+void sCPU::frame() {
+  ppu.frame();
+  snes.frame();
+
   status.vcounter = 0;
-  status.interlace_field ^= 1;
-  status.prev_field_lines = status.field_lines;
-  status.field_lines = (status.region_scanlines >> 1);
-//interlaced even fields have one extra scanline
-//(263+262=525 NTSC, 313+312=625 PAL)
-  if(status.interlace == true && status.interlace_field == 0)status.field_lines++;
+  status.field_lines = (snes.region() == SNES::NTSC ? 525 : 625) >> 1;
+  //interlaced even fields have one extra scanline
+  //(263+262=525 NTSC, 313+312=625 PAL)
+  if(ppu.interlace() == true && ppu.field() == 0) status.field_lines++;
 
   status.hdmainit_triggered = false;
   if(cpu_version == 1) {
@@ -116,9 +96,6 @@ void sCPU::frame() {
   } else {
     status.hdmainit_trigger_position = 12 + dma_counter();
   }
-
-  ppu.frame();
-  snes.frame();
 }
 
 /*****
@@ -129,7 +106,7 @@ void sCPU::frame() {
 alwaysinline void sCPU::precycle_edge() {
   if(status.dma_state == DMASTATE_CPUSYNC) {
     status.dma_state = DMASTATE_INACTIVE;
-  uint n = status.clock_count - (status.dma_clocks % status.clock_count);
+    uint n = status.clock_count - (status.dma_clocks % status.clock_count);
     add_clocks(n ? n : status.clock_count);
   }
 }
@@ -141,63 +118,58 @@ alwaysinline void sCPU::precycle_edge() {
  *****/
 void sCPU::cycle_edge() {
   if(status.line_rendered == false) {
-    if(status.hclock >= status.line_render_position) {
+    if(status.hcounter >= status.line_render_position) {
       status.line_rendered = true;
       ppu.render_scanline();
     }
   }
 
-  switch(status.dma_state) {
-  case DMASTATE_INACTIVE:
-    break;
-
-  case DMASTATE_DMASYNC:
-    status.dma_state = DMASTATE_RUN;
-    break;
-
-  case DMASTATE_RUN:
-    status.dma_state = DMASTATE_CPUSYNC;
-    status.dma_clocks = 8 - dma_counter() + 8;
-    add_clocks(status.dma_clocks);
-
-    if(status.hdmainit_pending) { hdma_init(); status.hdmainit_pending = false; }
-    if(status.hdma_pending)     { hdma_run();  status.hdma_pending     = false; }
-    if(status.dma_pending)      { dma_run();   status.dma_pending      = false; }
-
-    break;
-  }
-
   if(status.hdmainit_triggered == false) {
-    if(status.hclock >= status.hdmainit_trigger_position || status.vcounter) {
+    if(status.hcounter >= status.hdmainit_trigger_position || status.vcounter) {
       status.hdmainit_triggered = true;
       hdma_init_reset();
       if(hdma_enabled_channels()) {
-        add_clocks(18);
-        hdma_init();
-      //if(status.dma_state == DMASTATE_INACTIVE) {
-      //  status.dma_state = DMASTATE_DMASYNC;
-      //  status.hdmainit_pending = true;
-      //} else {
-      //  hdma_init();
-      //}
+        if(status.dma_state == DMASTATE_INACTIVE) {
+          status.dma_state = DMASTATE_DMASYNC;
+          status.hdmainit_pending = true;
+        } else {
+          hdma_init();
+        }
       }
     }
   }
 
   if(status.hdma_triggered == false) {
-    if(status.hclock >= 1106) {
+    if(status.hcounter >= 1106) {
       status.hdma_triggered = true;
       if(hdma_active_channels()) {
-        add_clocks(18);
-        hdma_run();
-      //if(status.dma_state == DMASTATE_INACTIVE) {
-      //  status.dma_state = DMASTATE_DMASYNC;
-      //  status.hdma_pending = true;
-      //} else {
-      //  hdma_run();
-      //}
+        if(status.dma_state == DMASTATE_INACTIVE) {
+          status.dma_state = DMASTATE_DMASYNC;
+          status.hdma_pending = true;
+        } else {
+          hdma_run();
+        }
       }
     }
+  }
+
+  switch(status.dma_state) {
+    case DMASTATE_INACTIVE: break;
+
+    case DMASTATE_DMASYNC: {
+      status.dma_state = DMASTATE_RUN;
+    } break;
+
+    case DMASTATE_RUN: {
+      status.dma_state = DMASTATE_CPUSYNC;
+      status.dma_clocks = 8 - dma_counter() + 8;
+      add_clocks(status.dma_clocks);
+
+      if(status.hdmainit_pending) { hdma_init(); status.hdmainit_pending = false; }
+      if(status.hdma_pending)     { hdma_run();  status.hdma_pending     = false; }
+      if(status.dma_pending)      { dma_run();   status.dma_pending      = false; }
+
+    } break;
   }
 }
 
@@ -211,7 +183,7 @@ void sCPU::cycle_edge() {
  * trigger during certain events (immediately after DMA, writes to $4200, etc)
  *****/
 void sCPU::last_cycle() {
-  if(counter.irq_delay) { return; }
+  if(counter.irq_delay) return;
 
   status.nmi_pending |= nmi_test();
   status.irq_pending |= irq_test();
@@ -235,27 +207,17 @@ void sCPU::timing_reset() {
 
   status.vcounter = 0;
   status.hcounter = 0;
-  status.hclock   = 0;
 
-  status.interlace        = 0;
-  status.interlace_field  = 0;
-  status.overscan         = false;
-  status.region_scanlines = (status.region == SNES::NTSC) ? 525 : 625;
-  status.vblstart         = 225;
-
-  status.field_lines = status.region_scanlines >> 1;
+  status.field_lines = (snes.region() == SNES::NTSC ? 525 : 625) >> 1;
   status.line_clocks = 1364;
 
-  status.prev_field_lines = status.region_scanlines >> 1;
-  status.prev_line_clocks = 1364;
-
-  status.line_rendered        = false;
+  status.line_rendered = false;
   status.line_render_position = min(1112U, (uint)config::ppu.hack.render_scanline_position);
 
-  status.dram_refreshed        = false;
+  status.dram_refreshed = false;
   status.dram_refresh_position = (cpu_version == 1) ? 530 : 538;
 
-  status.hdmainit_triggered        = false;
+  status.hdmainit_triggered = false;
   status.hdmainit_trigger_position = 0;
 
   status.hdma_triggered = false;
@@ -278,12 +240,16 @@ void sCPU::timing_reset() {
   status.dma_state        = DMASTATE_INACTIVE;
   status.dma_pending      = false;
   status.hdma_pending     = false;
-  status.hdmainit_pending = false;
+  status.hdmainit_pending = false;
+
+  history.reset();
 
-//initial latch values for $213c/$213d
-//[x]0035 : [y]0000 (53.0 -> 212) [lda $2137]
-//[x]0038 : [y]0000 (56.5 -> 226) [nop : lda $2137]
-//add_clocks(186);
+  //initial latch values for $213c/$213d
+  //[x]0035 : [y]0000 (53.0 -> 212) [lda $2137]
+  //[x]0038 : [y]0000 (56.5 -> 226) [nop : lda $2137]
+  add_clocks(186);
 }
 
 #undef ntsc_color_burst_phase_shift_scanline
+
+#endif //ifdef SCPU_CPP

src/cpu/scpu/timing/timing.h

@@ -1,45 +1,57 @@
   uint16 vcounter();
   uint16 hcounter();
-  uint16 hclock();
+  uint16 hdot();
+  uint dma_counter();
 
-  bool   interlace();
-  bool   interlace_field();
-  bool   overscan();
-  uint16 region_scanlines();
+  void add_clocks(uint clocks);
+  void scanline();
+  void frame();
 
-  void   set_interlace(bool r);
-  void   set_overscan(bool r);
-
-  uint   dma_counter();
-
-  void   add_clocks(uint clocks);
-  void   scanline();
-  void   frame();
-
-  void   precycle_edge();
-  void   cycle_edge();
-  void   last_cycle();
+  void precycle_edge();
+  void cycle_edge();
+  void last_cycle();
   uint32 clocks_executed();
 
-  void   timing_power();
-  void   timing_reset();
+  void timing_power();
+  void timing_reset();
+
+  //timeshifting -- needed by NMI and IRQ timing
+  struct History {
+    struct Time {
+      uint16 vcounter;
+      uint16 hcounter;
+    } time[32];
+    unsigned index;
+    alwaysinline void enqueue(uint16 vcounter, uint16 hcounter) {
+      Time &t = time[index++];
+      index &= 31;
+      t.vcounter = vcounter;
+      t.hcounter = hcounter;
+    }
+    alwaysinline void query(unsigned offset, uint16 &vcounter, uint16 &hcounter) {
+      Time &t = time[(index - (offset >> 1)) & 31];
+      vcounter = t.vcounter;
+      hcounter = t.hcounter;
+    }
+    void reset() {
+      index = 0;
+      for(unsigned i = 0; i < 32; i++) time[i].vcounter = time[i].hcounter = 0;
+    }
+    History() { reset(); }
+  } history;
 
-//timeshift.cpp
-  void   timeshift_forward (uint clocks, uint &v, uint &h);
-  void   timeshift_backward(uint clocks, uint &v, uint &h);
+  //irq.cpp
+  enum { IRQ_TRIGGER_NEVER = 0x3fff };
+  void update_interrupts();
+  void poll_interrupts();
+  void nmitimen_update(uint8 data);
+  void hvtime_update(uint16 addr);
+  bool rdnmi();
+  bool timeup();
 
-//irq.cpp
-enum { IRQ_TRIGGER_NEVER = 0x3fff };
-  void   update_interrupts();
-  void   poll_interrupts();
-  void   nmitimen_update(uint8 data);
-  void   hvtime_update(uint16 addr);
-  bool   rdnmi();
-  bool   timeup();
+  bool irq_pos_valid();
+  bool nmi_test();
+  bool irq_test();
 
-  bool   irq_pos_valid();
-  bool   nmi_test();
-  bool   irq_test();
-
-//joypad.cpp
-  void   run_auto_joypad_poll();
+  //joypad.cpp
+  void run_auto_joypad_poll();

src/data/icon48.h

@@ -0,0 +1,41 @@
+static char enc_icon48[] = {
+  "_gAB8AHwAfAB8AHwAfAB8P8B8AHwAfAB8AHwAfAB8AHw_wHwAfAB8AHwAfAB8AHw"
+  "AfD_AfAB8AHwAfAB8AHwAfAB8P8B8AHwAfAB8AHwAfAB8AHw_wHwAfAB8AHwAfAB"
+  "8AHwAfD_AfAB8AHwAfAB8AHwAfAB8P8B8AHwAfAB8AHwAfAB8AHw_wHwAfAB8AHw"
+  "AfAB8AHwAfD_AfAB8AHwAfAB8AHwAfABAAD_qgAD_p8VOwD_oRaI_qEWthD-oBbL"
+  "CADE_qEAFaP_oBZm_p38GBU28AHwAfAB8AHwAfBfAfAB8AFQuBCoAMe0AP4twAD_"
+  "BPAEIPAkAIX_-JkZCkLwAfAB8AHwAfBHAfAB8HSB_wABtABvPQQA-7DwBPAEECwA"
+  "0P74oBIbTvAB8AHwAfAB8EcB8AHweEGgFWwkAv0HqPAE8MSwFdX-oRr-E1LwAfAB"
+  "8AHwAfAB8Lzg6KEUMRAC96DwBPAE8P3EIKXAEVrwAfAB8AHwAfDzAfDAsBa3mPAE"
+  "8ATwwED_uAE4E1rwAfAB8AHwAfAB8PG8YKIVJDjyBPAE8ATA-KAWoF7wAfAB8AHw"
+  "AfB7AfD4gmmQ8ATwBPDM4-Z_XvAB8AHwAfAB8AHwwICPH_wSePQE8ATwBMClDxEB"
+  "YNBERP8PPz_-oEw-Pv56CACMCACCgggAXT8__yD2BA808wHwAfDAkKMSDv6AmxwS"
+  "_qQYH8QC6kjIAJTUAOug8ATwhOFDRABYUDw8_hWsAI9QPj7_8KwA_wTw_oL6BAC1"
+  "PT3-MpbwjwHwAfAB8AxmpRkUFAOOkxjzBPAEoJ8PEEAQdZQAOrwA47TwBPAoAPh9"
+  "yAB0hvAB8AHwAfBcsha6XFwC-KzwBPDsAOQ0EHWQAD0EAPSs8ATwBMCAn4LwAfAB"
+  "8AHwXLUVakz4gwTwKACbQkL-F0wBTuac8ATwiPH-_AQATh-C8AHwAfAB8ExifwAC"
+  "DcAAtbTwfKT8_qETejSAAJOc8ATwBPAUY9p9CAAIhvAB8AHwAfCEYZ4MGDWE8YCn"
+  "nEs8_3oRgAD1lPAE8ATwBKBVh4LwAQAUCwDNACQEAKBNAMwAaggAewgAoH8AywBz"
+  "CABbCABgNwDIAA458Nxp2IO88Hwhzf-ZEQ-0A15XjPAE8ATwhOGlfaDOVAA1oACY"
+  "sADhCAD9jQgA_wTwBEDMAPQEAHq7NABjCAAcq2QRvPAW9sUMXHwAiIzwBPAE8MDg"
+  "otZxIMsAGYQArQQATv6s8ATwzPAA4wQAUVcKAGQmYAR9MILpBAB3sP-qKgbgUPwC"
+  "mwQAevuAAP6U8ATwBPDAYO3QANEAHIQA3JjwBPCrBPAEoPwEAGyAQVRwAeCV_qIX"
+  "WPQWZNJ8AKoQgAQbSAI2hABtzAC6xAgA_aDwBPCIxOc4Ab6mjPAE8ATwBPAEAPYE"
+  "AK9YZwHwAfA2QwLAAEgEAK7dqPAE8MCAx8AA5Ijw_wTwBPAE8ExCFPQB8AHwAQDQ"
+  "Q0P-E5QAw6zwBPD1wECLcAC2iPAE8ATwBPD1BAD70AMqmvAB8AHwATDQODj-EpgA"
+  "1LDwxPbFBAAxcCDNAOyM8ATwewTwBOCGkvAB8AHwIOM8t-AzuPC8g66UasQwyJDw"
+  "VwTwBPAEIPHEBG4KAAJBDcYKAP7-LAQAT1UEAGUEAHAEAGoEAFd1BAA5BAASJAAY"
+  "-8Qg_gaytPB8Yeg7O_8eUTGgvwAEyABUUAK3XZAA9aTw6OJsFdgIAIOQAM8AG_11"
+  "_guUAKpgCAC1BADvDAD_BPAxBED-_vgIAEoA_nzDBAD4o0BA_lO88Lwgjuy4FPLw"
+  "AYDPABCYAKpCoABtBACKBACbEACKngQAk4wnzQBXoCd3qBe5plgh4azwBPDM8P76"
+  "9QQAiwwA1CjgGeQSvMD6yAQAKbHwAfAB8AHwvMC9RBH-nPAE8ATwBKDAxCFVVDXu"
+  "sADzCAC9dEgEX3nwAfAB8AHwvMAxBAD8X4zwBPAE8ATwTAB-3Ewh_bQADHHwAfAB"
+  "8AHwAfDAYL50iPAE8ATwBPDAQMRl8L8B8AHwAfAB8AHwcABMiPDvBPAE8ATwwECc"
+  "ZfAB8AHwrwHwAfAB8HQAAnQAsIzw9wTwBPC84OQIABy1AfAB8O8B8AHwAfDs1ZUI"
+  "8wTwBPD1vGDHBAAkXfAB8AHwAfCnAfAB8Mjw_zCEAJ8EAK7rpPAE8CgA9wQAvAQA"
+  "_lQQAJC1AfAB8AHwAfAB8FcB8MjwkBE6BABsBACPVQQApAQArwQAqQQAl_UgAHgI"
+  "AEsEANQsAfAB8P8B8AHwAfAB8AHwAfAB8AHw_wHwAfAB8AHwAfAB8AHwAfD_AfAB"
+  "8AHwAfAB8AHwAfAB8P8B8AHwAfAB8AHwAfAB8AHw_wHwAfAB8AHwAfAB8AHwAfD_"
+  "AfAB8AHwAfAB8AHwAfAB8P8B8AHwAfAB8AHwAfAB8AHw_wHwAfAB8AHwAfAB8AHw"
+  "AfD_AfAB8AHwAfAB8AHwAfAB8A8B8AHwAfABsA"
+};

src/dsp/adsp/adsp.cpp

@@ -1,4 +1,6 @@
-#include "../../base.h"
+#include "../../base.h"
+#define ADSP_CPP
+
 #include "adsp_tables.cpp"
 
 void aDSP::enter() { loop:
@@ -578,8 +580,8 @@ int32 fir_samplel, fir_sampler;
     msampler  = sclamp<16>(msampler);
   }
 
-  snes.audio_update(msamplel, msampler);
-  scheduler.addclocks_dsp(32 * 3);
+  snes.audio.update(msamplel, msampler);
+  scheduler.addclocks_dsp(32 * 3 * 8);
 }
 
 aDSP::aDSP()  {}

src/dsp/adsp/adsp_tables.cpp

@@ -1,3 +1,5 @@
+#ifdef ADSP_CPP
+
 const uint16 aDSP::rate_table[32] = {
   0x0000, 0x000F, 0x0014, 0x0018, 0x001E, 0x0028, 0x0030, 0x003C,
   0x0050, 0x0060, 0x0078, 0x00A0, 0x00C0, 0x00F0, 0x0140, 0x0180,
@@ -71,3 +73,5 @@ const int16 aDSP::gaussian_table[512] = {
   0x513, 0x514, 0x514, 0x515, 0x516, 0x516, 0x517, 0x517,
   0x517, 0x518, 0x518, 0x518, 0x518, 0x518, 0x519, 0x519
 };
+
+#endif //ifdef ADSP_CPP

src/dsp/bdsp/bdsp.cpp

@@ -469,7 +469,7 @@ void bDSP::enter()
 	{
 		// n is currently ignored
 		#define NEXT_CLOCK( n ) \
-			scheduler.addclocks_dsp( 3 );
+			scheduler.addclocks_dsp( 3 * 8 );
 		
 		// Execute clock for a particular voice
 		#define V( clock, voice )   voice_##clock( &m.voices [voice] );
@@ -563,7 +563,7 @@ void bDSP::enter()
 			}
 			
 			// Output sample to DAC
-			snes.audio_update( main_out_l, main_out_r );
+			snes.audio.update( main_out_l, main_out_r );
 			
 			m.t_main_out [0] = 0;
 			m.t_main_out [1] = 0;

src/dsp/dsp.h

@@ -1,11 +1,12 @@
-class DSP { public:
-  virtual void   enter() = 0;
+class DSP {
+public:
+  virtual void enter() = 0;
 
-  virtual uint8  read (uint8 addr) = 0;
-  virtual void   write(uint8 addr, uint8 data) = 0;
+  virtual uint8 read(uint8 addr) = 0;
+  virtual void write(uint8 addr, uint8 data) = 0;
 
-  virtual void   power() = 0;
-  virtual void   reset() = 0;
+  virtual void power() = 0;
+  virtual void reset() = 0;
 
   DSP() {}
   virtual ~DSP() {}

src/dsp/sdsp/brr.cpp

@@ -0,0 +1,62 @@
+#ifdef SDSP_CPP
+
+void sDSP::brr_decode(voice_t &v) {
+  //state.t_brr_byte = ram[v.brr_addr + v.brr_offset] cached from previous clock cycle
+  int nybbles = (state.t_brr_byte << 8) + ram[(uint16)(v.brr_addr + v.brr_offset + 1)];
+
+  const int filter = (state.t_brr_header >> 2) & 3;
+  const int scale  = (state.t_brr_header >> 4);
+
+  //decode four samples
+  for(unsigned i = 0; i < 4; i++) {
+    //bits 12-15 = current nybble; sign extend, then shift right to 4-bit precision
+    //result: s = 4-bit sign-extended sample value
+    int s = (int16)nybbles >> 12;
+    nybbles <<= 4; //slide nybble so that on next loop iteration, bits 12-15 = current nybble
+
+    if(scale <= 12) {
+      s <<= scale;
+      s >>= 1;
+    } else {
+      s &= ~0x7ff;
+    }
+
+    //apply IIR filter (2 is the most commonly used)
+    const int p1 = v.buffer[v.buf_pos - 1];
+    const int p2 = v.buffer[v.buf_pos - 2] >> 1;
+
+    switch(filter) {
+      case 0: break; //no filter
+
+      case 1: {
+        //s += p1 * 0.46875
+        s += p1 >> 1;
+        s += (-p1) >> 5;
+      } break;
+
+      case 2: {
+        //s += p1 * 0.953125 - p2 * 0.46875
+        s += p1;
+        s -= p2;
+        s += p2 >> 4;
+        s += (p1 * -3) >> 6;
+      } break;
+
+      case 3: {
+        //s += p1 * 0.8984375 - p2 * 0.40625
+        s += p1;
+        s -= p2;
+        s += (p1 * -13) >> 7;
+        s += (p2 * 3) >> 4;
+      } break;
+    }
+
+    //adjust and write sample
+    s = sclamp<16>(s);
+    s = (int16)(s << 1);
+    v.buffer.write(v.buf_pos++, s);
+    if(v.buf_pos >= brr_buf_size) v.buf_pos = 0;
+  }
+}
+
+#endif //ifdef SDSP_CPP

src/dsp/sdsp/counter.cpp

@@ -0,0 +1,52 @@
+#ifdef SDSP_CPP
+
+//counter_rate = number of samples per counter event
+//all rates are evenly divisible by counter_range (0x7800, 30720, or 2048 * 5 * 3)
+//note that rate[0] is a special case, which never triggers
+
+const uint16 sDSP::counter_rate[32] = {
+     0, 2048, 1536,
+  1280, 1024,  768,
+   640,  512,  384,
+   320,  256,  192,
+   160,  128,   96,
+    80,   64,   48,
+    40,   32,   24,
+    20,   16,   12,
+    10,    8,    6,
+     5,    4,    3,
+           2,
+           1,
+};
+
+//counter_offset = counter offset from zero
+//counters do not appear to be aligned at zero for all rates
+
+const uint16 sDSP::counter_offset[32] = {
+    0, 0, 1040,
+  536, 0, 1040,
+  536, 0, 1040,
+  536, 0, 1040,
+  536, 0, 1040,
+  536, 0, 1040,
+  536, 0, 1040,
+  536, 0, 1040,
+  536, 0, 1040,
+  536, 0, 1040,
+       0,
+       0,
+};
+
+inline void sDSP::counter_tick() {
+  state.counter--;
+  if(state.counter < 0) state.counter = counter_range - 1;
+}
+
+//return true if counter event should trigger
+
+inline bool sDSP::counter_poll(unsigned rate) {
+  if(rate == 0) return false;
+  return (((unsigned)state.counter + counter_offset[rate]) % counter_rate[rate]) == 0;
+}
+
+#endif //ifdef SDSP_CPP

src/dsp/sdsp/echo.cpp

@@ -0,0 +1,133 @@
+#ifdef SDSP_CPP
+
+int sDSP::calc_fir(int i, bool channel) {
+  int s = state.echo_hist[channel][state.echo_hist_pos + i + 1];
+  return (s * (int8)REG(fir + i * 0x10)) >> 6;
+}
+
+int sDSP::echo_output(bool channel) {
+  int output = (int16)((state.t_main_out[channel] * (int8)REG(mvoll + channel * 0x10)) >> 7)
+             + (int16)((state.t_echo_in [channel] * (int8)REG(evoll + channel * 0x10)) >> 7);
+  return sclamp<16>(output);
+}
+
+void sDSP::echo_read(bool channel) {
+  uint8 *in = &ram[state.t_echo_ptr + channel * 2];
+  int s = (int16)((in[1] << 8) + in[0]);
+  state.echo_hist[channel].write(state.echo_hist_pos, s >> 1);
+}
+
+void sDSP::echo_write(bool channel) {
+  if(!(state.t_echo_disabled & 0x20)) {
+    uint8 *out = &ram[state.t_echo_ptr + channel * 2];
+    int s = state.t_echo_out[channel];
+    out[0] = (uint8)(s);
+    out[1] = (uint8)(s >> 8);
+  }
+
+  state.t_echo_out[channel] = 0;
+}
+
+void sDSP::echo_22() {
+  //history
+  state.echo_hist_pos++;
+  if(state.echo_hist_pos >= echo_hist_size) state.echo_hist_pos = 0;
+
+  state.t_echo_ptr = (uint16)((state.t_esa << 8) + state.echo_offset);
+  echo_read(0);
+
+  //FIR
+  int l = calc_fir(0, 0);
+  int r = calc_fir(0, 1);
+
+  state.t_echo_in[0] = l;
+  state.t_echo_in[1] = r;
+}
+
+void sDSP::echo_23() {
+  int l = calc_fir(1, 0) + calc_fir(2, 0);
+  int r = calc_fir(1, 1) + calc_fir(2, 1);
+
+  state.t_echo_in[0] += l;
+  state.t_echo_in[1] += r;
+
+  echo_read(1);
+}
+
+void sDSP::echo_24() {
+  int l = calc_fir(3, 0) + calc_fir(4, 0) + calc_fir(5, 0);
+  int r = calc_fir(3, 1) + calc_fir(4, 1) + calc_fir(5, 1);
+
+  state.t_echo_in[0] += l;
+  state.t_echo_in[1] += r;
+}
+
+void sDSP::echo_25() {
+  int l = state.t_echo_in[0] + calc_fir(6, 0);
+  int r = state.t_echo_in[1] + calc_fir(6, 1);
+
+  l = (int16)l;
+  r = (int16)r;
+
+  l += (int16)calc_fir(7, 0);
+  r += (int16)calc_fir(7, 1);
+
+  state.t_echo_in[0] = sclamp<16>(l) & ~1;
+  state.t_echo_in[1] = sclamp<16>(r) & ~1;
+}
+
+void sDSP::echo_26() {
+  //left output volumes
+  //(save sample for next clock so we can output both together)
+  state.t_main_out[0] = echo_output(0);
+
+  //echo feedback
+  int l = state.t_echo_out[0] + (int16)((state.t_echo_in[0] * (int8)REG(efb)) >> 7);
+  int r = state.t_echo_out[1] + (int16)((state.t_echo_in[1] * (int8)REG(efb)) >> 7);
+
+  state.t_echo_out[0] = sclamp<16>(l) & ~1;
+  state.t_echo_out[1] = sclamp<16>(r) & ~1;
+}
+
+void sDSP::echo_27() {
+  //output
+  int outl = state.t_main_out[0];
+  int outr = echo_output(1);
+  state.t_main_out[0] = 0;
+  state.t_main_out[1] = 0;
+
+  //TODO: global muting isn't this simple
+  //(turns DAC on and off or something, causing small ~37-sample pulse when first muted)
+  if(REG(flg) & 0x40) {
+    outl = 0;
+    outr = 0;
+  }
+
+  //output sample to DAC
+  snes.audio.update(outl, outr);
+}
+
+void sDSP::echo_28() {
+  state.t_echo_disabled = REG(flg);
+}
+
+void sDSP::echo_29() {
+  state.t_esa = REG(esa);
+
+  if(!state.echo_offset) state.echo_length = (REG(edl) & 0x0f) << 11;
+
+  state.echo_offset += 4;
+  if(state.echo_offset >= state.echo_length) state.echo_offset = 0;
+
+  //write left echo
+  echo_write(0);
+
+  state.t_echo_disabled = REG(flg);
+}
+
+void sDSP::echo_30() {
+  //write right echo
+  echo_write(1);
+}
+
+#endif //ifdef SDSP_CPP